arch/arm/boot/dts/pxa3xx.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* The pxa3xx skeleton simply augments the 2xx version */
   3 #include "pxa2xx.dtsi"
   4
   5 #define MFP_PIN_PXA300(gpio)                            \
   6         ((gpio <= 2) ? (0x00b4 + 4 * gpio) :            \
   7          (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) :     \
   8          (gpio <= 98) ? (0x0400 + 4 * (gpio - 27)) :    \
   9          (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) :   \
  10          0)
  11 #define MFP_PIN_PXA300_2(gpio)                          \
  12         ((gpio <= 1) ? (0x674 + 4 * gpio) :             \
  13          (gpio <= 6) ? (0x2dc + 4 * gpio) :             \
  14          0)
  15
  16 #define MFP_PIN_PXA310(gpio)                            \
  17         ((gpio <= 2) ? (0x00b4 + 4 * gpio) :            \
  18          (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) :     \
  19          (gpio <= 29) ? (0x0400 + 4 * (gpio - 27)) :    \
  20          (gpio <= 98) ? (0x0418 + 4 * (gpio - 30)) :    \
  21          (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) :   \
  22          (gpio <= 262) ? 0 :                            \
  23          (gpio <= 268) ? (0x052c + 4 * (gpio - 263)) :  \
  24          0)
  25 #define MFP_PIN_PXA310_2(gpio)                          \
  26         ((gpio <= 1) ? (0x674 + 4 * gpio) :             \
  27          (gpio <= 6) ? (0x2dc + 4 * gpio) :             \
  28          (gpio <= 10) ? (0x52c + 4 * gpio) :            \
  29          0)
  30
  31 #define MFP_PIN_PXA320(gpio)                            \
  32         ((gpio <= 4) ? (0x0124 + 4 * gpio) :            \
  33          (gpio <= 9) ? (0x028c + 4 * (gpio - 5)) :      \
  34          (gpio <= 10) ? (0x0458 + 4 * (gpio - 10)) :    \
  35          (gpio <= 26) ? (0x02a0 + 4 * (gpio - 11)) :    \
  36          (gpio <= 48) ? (0x0400 + 4 * (gpio - 27)) :    \
  37          (gpio <= 62) ? (0x045c + 4 * (gpio - 49)) :    \
  38          (gpio <= 73) ? (0x04b4 + 4 * (gpio - 63)) :    \
  39          (gpio <= 98) ? (0x04f0 + 4 * (gpio - 74)) :    \
  40          (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) :   \
  41          0)
  42 #define MFP_PIN_PXA320_2(gpio)                          \
  43         ((gpio <= 3) ? (0x674 + 4 * gpio) :             \
  44          (gpio <= 5) ? (0x284 + 4 * gpio) :             \
  45          0)
  46
  47 /*
  48  * MFP Alternate functions for pins having a gpio.
  49  * Example of use: pinctrl-single,pins = < MFP_PIN_PXA310(21) MFP_AF1 >
  50  */
  51 #define MFP_AF0         (0 << 0)
  52 #define MFP_AF1         (1 << 0)
  53 #define MFP_AF2         (2 << 0)
  54 #define MFP_AF3         (3 << 0)
  55 #define MFP_AF4         (4 << 0)
  56 #define MFP_AF5         (5 << 0)
  57 #define MFP_AF6         (6 << 0)
  58
  59 /*
  60  * MFP drive strength functions for pins.
  61  * Example of use: pinctrl-single,drive-strength = MFP_DS03X;
  62  */
  63 #define MFP_DSMSK       (0x7 << 10)
  64 #define MFP_DS01X       < (0x0 << 10) MFP_DSMSK >
  65 #define MFP_DS02X       < (0x1 << 10) MFP_DSMSK >
  66 #define MFP_DS03X       < (0x2 << 10) MFP_DSMSK >
  67 #define MFP_DS04X       < (0x3 << 10) MFP_DSMSK >
  68 #define MFP_DS06X       < (0x4 << 10) MFP_DSMSK >
  69 #define MFP_DS08X       < (0x5 << 10) MFP_DSMSK >
  70 #define MFP_DS10X       < (0x6 << 10) MFP_DSMSK >
  71 #define MFP_DS13X       < (0x7 << 10) MFP_DSMSK >
  72
  73 /*
  74  * MFP low power mode for pins.
  75  * Example of use:
  76  *   pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW|MFP_LPM_EDGE_FALL);
  77  *
  78  * Table that determines the low power modes outputs, with actual settings
  79  * used in parentheses for don't-care values. Except for the float output,
  80  * the configured driven and pulled levels match, so if there is a need for
  81  * non-LPM pulled output, the same configuration could probably be used.
  82  *
  83  * Output value  sleep_oe_n  sleep_data  pullup_en  pulldown_en  pull_sel
  84  *                 (bit 7)    (bit 8)    (bit 14)     (bit 13)   (bit 15)
  85  *
  86  * Input            0          X(0)        X(0)        X(0)       0
  87  * Drive 0          0          0           0           X(1)       0
  88  * Drive 1          0          1           X(1)        0          0
  89  * Pull hi (1)      1          X(1)        1           0          0
  90  * Pull lo (0)      1          X(0)        0           1          0
  91  * Z (float)        1          X(0)        0           0          0
  92  */
  93 #define MFP_LPM(x)              < (x) MFP_LPM_MSK >
  94
  95 #define MFP_LPM_MSK             0xe1f0
  96 #define MFP_LPM_INPUT           0x0000
  97 #define MFP_LPM_DRIVE_LOW       0x2000
  98 #define MFP_LPM_DRIVE_HIGH      0x4100
  99 #define MFP_LPM_PULL_LOW        0x2080
 100 #define MFP_LPM_PULL_HIGH       0x4180
 101 #define MFP_LPM_FLOAT           0x0080
 102
 103 #define MFP_LPM_EDGE_NONE       0x0000
 104 #define MFP_LPM_EDGE_RISE       0x0010
 105 #define MFP_LPM_EDGE_FALL       0x0020
 106 #define MFP_LPM_EDGE_BOTH       0x0030
 107
 108 / {
 109         model = "Marvell PXA3xx familiy SoC";
 110         compatible = "marvell,pxa3xx";
 111
 112         pxabus {
 113                 pdma: dma-controller@40000000 {
 114                         compatible = "marvell,pdma-1.0";
 115                         reg = <0x40000000 0x10000>;
 116                         interrupts = <25>;
 117                         #dma-channels = <32>;
 118                         #dma-cells = <2>;
 119                         #dma-requests = <100>;
 120                         status = "okay";
 121                 };
 122
 123                 pwri2c: i2c@40f500c0 {
 124                         compatible = "mrvl,pwri2c";
 125                         reg = <0x40f500c0 0x30>;
 126                         interrupts = <6>;
 127                         clocks = <&clks CLK_PWRI2C>;
 128                         #address-cells = <0x1>;
 129                         #size-cells = <0>;
 130                         status = "disabled";
 131                 };
 132
 133                 nand_controller: nand-controller@43100000 {
 134                         compatible = "marvell,pxa3xx-nand-controller";
 135                         reg = <0x43100000 90>;
 136                         interrupts = <45>;
 137                         clocks = <&clks CLK_NAND>;
 138                         dmas = <&pdma 97 3>;
 139                         dma-names = "data";
 140                         #address-cells = <1>;
 141                         #size-cells = <0>;
 142                         status = "disabled";
 143                 };
 144
 145                 pxairq: interrupt-controller@40d00000 {
 146                         marvell,intc-priority;
 147                         marvell,intc-nr-irqs = <56>;
 148                 };
 149
 150                 pinctrl: pinctrl@40e10000 {
 151                         compatible = "pinconf-single";
 152                         reg = <0x40e10000 0xffff>;
 153                         #address-cells = <1>;
 154                         #size-cells = <0>;
 155                         #pinctrl-cells = <1>;
 156                         pinctrl-single,register-width = <32>;
 157                         pinctrl-single,function-mask = <0x7>;
 158                 };
 159
 160                 gpio: gpio@40e00000 {
 161                         compatible = "intel,pxa3xx-gpio";
 162                         reg = <0x40e00000 0x10000>;
 163                         clocks = <&clks CLK_GPIO>;
 164                         gpio-ranges = <&pinctrl 0 0 128>;
 165                         interrupt-names = "gpio0", "gpio1", "gpio_mux";
 166                         interrupts = <8 9 10>;
 167                         gpio-controller;
 168                         #gpio-cells = <0x2>;
 169                         interrupt-controller;
 170                         #interrupt-cells = <0x2>;
 171                 };
 172
 173                 mmc0: mmc@41100000 {
 174                         compatible = "marvell,pxa-mmc";
 175                         reg = <0x41100000 0x1000>;
 176                         interrupts = <23>;
 177                         clocks = <&clks CLK_MMC>;
 178                         dmas = <&pdma 21 3
 179                                 &pdma 22 3>;
 180                         dma-names = "rx", "tx";
 181                         status = "disabled";
 182                 };
 183
 184                 mmc1: mmc@42000000 {
 185                         compatible = "marvell,pxa-mmc";
 186                         reg = <0x42000000 0x1000>;
 187                         interrupts = <41>;
 188                         clocks = <&clks CLK_MMC1>;
 189                         dmas = <&pdma 93 3
 190                                 &pdma 94 3>;
 191                         dma-names = "rx", "tx";
 192                         status = "disabled";
 193                 };
 194
 195                 mmc2: mmc@42500000 {
 196                         compatible = "marvell,pxa-mmc";
 197                         reg = <0x42500000 0x1000>;
 198                         interrupts = <55>;
 199                         clocks = <&clks CLK_MMC2>;
 200                         dmas = <&pdma 46 3
 201                                 &pdma 47 3>;
 202                         dma-names = "rx", "tx";
 203                         status = "disabled";
 204                 };
 205
 206                 pxa3xx_ohci: usb@4c000000 {
 207                         compatible = "marvell,pxa-ohci";
 208                         reg = <0x4c000000 0x10000>;
 209                         interrupts = <3>;
 210                         clocks = <&clks CLK_USBH>;
 211                         status = "disabled";
 212                 };
 213
 214                 pwm0: pwm@40b00000 {
 215                         compatible = "marvell,pxa270-pwm";
 216                         reg = <0x40b00000 0x10>;
 217                         #pwm-cells = <1>;
 218                         clocks = <&clks CLK_PWM0>;
 219                         status = "disabled";
 220                 };
 221
 222                 pwm1: pwm@40b00010 {
 223                         compatible = "marvell,pxa270-pwm";
 224                         reg = <0x40b00010 0x10>;
 225                         #pwm-cells = <1>;
 226                         clocks = <&clks CLK_PWM1>;
 227                         status = "disabled";
 228                 };
 229
 230                 pwm2: pwm@40c00000 {
 231                         compatible = "marvell,pxa270-pwm";
 232                         reg = <0x40c00000 0x10>;
 233                         #pwm-cells = <1>;
 234                         clocks = <&clks CLK_PWM0>;
 235                         status = "disabled";
 236                 };
 237
 238                 pwm3: pwm@40c00010 {
 239                         compatible = "marvell,pxa270-pwm";
 240                         reg = <0x40c00010 0x10>;
 241                         #pwm-cells = <1>;
 242                         clocks = <&clks CLK_PWM1>;
 243                         status = "disabled";
 244                 };
 245         };
 246
 247         clocks {
 248                /*
 249                 * The muxing of external clocks/internal dividers for osc* clock
 250                 * sources has been hidden under the carpet by now.
 251                 */
 252                 #address-cells = <1>;
 253                 #size-cells = <1>;
 254                 ranges;
 255
 256                 clks: pxa3xx_clks@41300004 {
 257                         compatible = "marvell,pxa300-clocks";
 258                         #clock-cells = <1>;
 259                         status = "okay";
 260                 };
 261         };
 262
 263         timer@40a00000 {
 264                 compatible = "marvell,pxa-timer";
 265                 reg = <0x40a00000 0x20>;
 266                 interrupts = <26>;
 267                 clocks = <&clks CLK_OSTIMER>;
 268                 status = "okay";
 269         };
 270 };