2 * Copyright (C) 2012 Marvell Technology Group Ltd.
3 * Author: Haojian Zhuang <haojian.zhuang@marvell.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
10 #include <dt-bindings/clock/marvell,pxa910.h>
27 compatible = "simple-bus";
28 interrupt-parent = <&intc>;
32 compatible = "marvell,tauros2-cache";
33 marvell,tauros2-cache-features = <0x3>;
36 axi@d4200000 { /* AXI */
37 compatible = "mrvl,axi-bus", "simple-bus";
40 reg = <0xd4200000 0x00200000>;
43 intc: interrupt-controller@d4282000 {
44 compatible = "mrvl,mmp-intc";
46 #interrupt-cells = <1>;
47 reg = <0xd4282000 0x1000>;
48 mrvl,intc-nr-irqs = <64>;
53 apb@d4000000 { /* APB */
54 compatible = "mrvl,apb-bus", "simple-bus";
57 reg = <0xd4000000 0x00200000>;
60 timer0: timer@d4014000 {
61 compatible = "mrvl,mmp-timer";
62 reg = <0xd4014000 0x100>;
66 timer1: timer@d4016000 {
67 compatible = "mrvl,mmp-timer";
68 reg = <0xd4016000 0x100>;
73 uart1: uart@d4017000 {
74 compatible = "mrvl,mmp-uart";
75 reg = <0xd4017000 0x1000>;
77 clocks = <&soc_clocks PXA910_CLK_UART0>;
78 resets = <&soc_clocks PXA910_CLK_UART0>;
82 uart2: uart@d4018000 {
83 compatible = "mrvl,mmp-uart";
84 reg = <0xd4018000 0x1000>;
86 clocks = <&soc_clocks PXA910_CLK_UART1>;
87 resets = <&soc_clocks PXA910_CLK_UART1>;
91 uart3: uart@d4036000 {
92 compatible = "mrvl,mmp-uart";
93 reg = <0xd4036000 0x1000>;
95 clocks = <&soc_clocks PXA910_CLK_UART2>;
96 resets = <&soc_clocks PXA910_CLK_UART2>;
101 compatible = "marvell,mmp-gpio";
102 #address-cells = <1>;
104 reg = <0xd4019000 0x1000>;
108 interrupt-names = "gpio_mux";
109 clocks = <&soc_clocks PXA910_CLK_GPIO>;
110 resets = <&soc_clocks PXA910_CLK_GPIO>;
111 interrupt-controller;
112 #interrupt-cells = <1>;
115 gcb0: gpio@d4019000 {
116 reg = <0xd4019000 0x4>;
119 gcb1: gpio@d4019004 {
120 reg = <0xd4019004 0x4>;
123 gcb2: gpio@d4019008 {
124 reg = <0xd4019008 0x4>;
127 gcb3: gpio@d4019100 {
128 reg = <0xd4019100 0x4>;
132 twsi1: i2c@d4011000 {
133 compatible = "mrvl,mmp-twsi";
134 #address-cells = <1>;
136 reg = <0xd4011000 0x1000>;
138 clocks = <&soc_clocks PXA910_CLK_TWSI0>;
139 resets = <&soc_clocks PXA910_CLK_TWSI0>;
144 twsi2: i2c@d4037000 {
145 compatible = "mrvl,mmp-twsi";
146 #address-cells = <1>;
148 reg = <0xd4037000 0x1000>;
150 clocks = <&soc_clocks PXA910_CLK_TWSI1>;
151 resets = <&soc_clocks PXA910_CLK_TWSI1>;
156 compatible = "mrvl,mmp-rtc";
157 reg = <0xd4010000 0x1000>;
159 interrupt-names = "rtc 1Hz", "rtc alarm";
160 clocks = <&soc_clocks PXA910_CLK_RTC>;
161 resets = <&soc_clocks PXA910_CLK_RTC>;
167 compatible = "marvell,pxa910-clock";
168 reg = <0xd4050000 0x1000>,
172 reg-names = "mpmu", "apmu", "apbc", "apbcp";