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[mirror_ubuntu-kernels.git] / arch / arm / boot / dts / qcom-apq8064.dtsi
1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
3
4 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
5 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
6 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
7 #include <dt-bindings/clock/qcom,rpmcc.h>
8 #include <dt-bindings/soc/qcom,gsbi.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 / {
12 #address-cells = <1>;
13 #size-cells = <1>;
14 model = "Qualcomm APQ8064";
15 compatible = "qcom,apq8064";
16 interrupt-parent = <&intc>;
17
18 reserved-memory {
19 #address-cells = <1>;
20 #size-cells = <1>;
21 ranges;
22
23 smem_region: smem@80000000 {
24 reg = <0x80000000 0x200000>;
25 no-map;
26 };
27
28 wcnss_mem: wcnss@8f000000 {
29 reg = <0x8f000000 0x700000>;
30 no-map;
31 };
32 };
33
34 cpus {
35 #address-cells = <1>;
36 #size-cells = <0>;
37
38 CPU0: cpu@0 {
39 compatible = "qcom,krait";
40 enable-method = "qcom,kpss-acc-v1";
41 device_type = "cpu";
42 reg = <0>;
43 next-level-cache = <&L2>;
44 qcom,acc = <&acc0>;
45 qcom,saw = <&saw0>;
46 cpu-idle-states = <&CPU_SPC>;
47 };
48
49 CPU1: cpu@1 {
50 compatible = "qcom,krait";
51 enable-method = "qcom,kpss-acc-v1";
52 device_type = "cpu";
53 reg = <1>;
54 next-level-cache = <&L2>;
55 qcom,acc = <&acc1>;
56 qcom,saw = <&saw1>;
57 cpu-idle-states = <&CPU_SPC>;
58 };
59
60 CPU2: cpu@2 {
61 compatible = "qcom,krait";
62 enable-method = "qcom,kpss-acc-v1";
63 device_type = "cpu";
64 reg = <2>;
65 next-level-cache = <&L2>;
66 qcom,acc = <&acc2>;
67 qcom,saw = <&saw2>;
68 cpu-idle-states = <&CPU_SPC>;
69 };
70
71 CPU3: cpu@3 {
72 compatible = "qcom,krait";
73 enable-method = "qcom,kpss-acc-v1";
74 device_type = "cpu";
75 reg = <3>;
76 next-level-cache = <&L2>;
77 qcom,acc = <&acc3>;
78 qcom,saw = <&saw3>;
79 cpu-idle-states = <&CPU_SPC>;
80 };
81
82 L2: l2-cache {
83 compatible = "cache";
84 cache-level = <2>;
85 };
86
87 idle-states {
88 CPU_SPC: spc {
89 compatible = "qcom,idle-state-spc",
90 "arm,idle-state";
91 entry-latency-us = <400>;
92 exit-latency-us = <900>;
93 min-residency-us = <3000>;
94 };
95 };
96 };
97
98 memory {
99 device_type = "memory";
100 reg = <0x0 0x0>;
101 };
102
103 thermal-zones {
104 cpu-thermal0 {
105 polling-delay-passive = <250>;
106 polling-delay = <1000>;
107
108 thermal-sensors = <&gcc 7>;
109 coefficients = <1199 0>;
110
111 trips {
112 cpu_alert0: trip0 {
113 temperature = <75000>;
114 hysteresis = <2000>;
115 type = "passive";
116 };
117 cpu_crit0: trip1 {
118 temperature = <110000>;
119 hysteresis = <2000>;
120 type = "critical";
121 };
122 };
123 };
124
125 cpu-thermal1 {
126 polling-delay-passive = <250>;
127 polling-delay = <1000>;
128
129 thermal-sensors = <&gcc 8>;
130 coefficients = <1132 0>;
131
132 trips {
133 cpu_alert1: trip0 {
134 temperature = <75000>;
135 hysteresis = <2000>;
136 type = "passive";
137 };
138 cpu_crit1: trip1 {
139 temperature = <110000>;
140 hysteresis = <2000>;
141 type = "critical";
142 };
143 };
144 };
145
146 cpu-thermal2 {
147 polling-delay-passive = <250>;
148 polling-delay = <1000>;
149
150 thermal-sensors = <&gcc 9>;
151 coefficients = <1199 0>;
152
153 trips {
154 cpu_alert2: trip0 {
155 temperature = <75000>;
156 hysteresis = <2000>;
157 type = "passive";
158 };
159 cpu_crit2: trip1 {
160 temperature = <110000>;
161 hysteresis = <2000>;
162 type = "critical";
163 };
164 };
165 };
166
167 cpu-thermal3 {
168 polling-delay-passive = <250>;
169 polling-delay = <1000>;
170
171 thermal-sensors = <&gcc 10>;
172 coefficients = <1132 0>;
173
174 trips {
175 cpu_alert3: trip0 {
176 temperature = <75000>;
177 hysteresis = <2000>;
178 type = "passive";
179 };
180 cpu_crit3: trip1 {
181 temperature = <110000>;
182 hysteresis = <2000>;
183 type = "critical";
184 };
185 };
186 };
187 };
188
189 cpu-pmu {
190 compatible = "qcom,krait-pmu";
191 interrupts = <1 10 0x304>;
192 };
193
194 clocks {
195 cxo_board: cxo_board {
196 compatible = "fixed-clock";
197 #clock-cells = <0>;
198 clock-frequency = <19200000>;
199 };
200
201 pxo_board {
202 compatible = "fixed-clock";
203 #clock-cells = <0>;
204 clock-frequency = <27000000>;
205 };
206
207 sleep_clk: sleep_clk {
208 compatible = "fixed-clock";
209 #clock-cells = <0>;
210 clock-frequency = <32768>;
211 };
212 };
213
214 sfpb_mutex: hwmutex {
215 compatible = "qcom,sfpb-mutex";
216 syscon = <&sfpb_wrapper_mutex 0x604 0x4>;
217 #hwlock-cells = <1>;
218 };
219
220 smem {
221 compatible = "qcom,smem";
222 memory-region = <&smem_region>;
223
224 hwlocks = <&sfpb_mutex 3>;
225 };
226
227 smd {
228 compatible = "qcom,smd";
229
230 modem@0 {
231 interrupts = <0 37 IRQ_TYPE_EDGE_RISING>;
232
233 qcom,ipc = <&l2cc 8 3>;
234 qcom,smd-edge = <0>;
235
236 status = "disabled";
237 };
238
239 q6@1 {
240 interrupts = <0 90 IRQ_TYPE_EDGE_RISING>;
241
242 qcom,ipc = <&l2cc 8 15>;
243 qcom,smd-edge = <1>;
244
245 status = "disabled";
246 };
247
248 dsps@3 {
249 interrupts = <0 138 IRQ_TYPE_EDGE_RISING>;
250
251 qcom,ipc = <&sps_sic_non_secure 0x4080 0>;
252 qcom,smd-edge = <3>;
253
254 status = "disabled";
255 };
256
257 riva@6 {
258 interrupts = <0 198 IRQ_TYPE_EDGE_RISING>;
259
260 qcom,ipc = <&l2cc 8 25>;
261 qcom,smd-edge = <6>;
262
263 status = "disabled";
264 };
265 };
266
267 smsm {
268 compatible = "qcom,smsm";
269
270 #address-cells = <1>;
271 #size-cells = <0>;
272
273 qcom,ipc-1 = <&l2cc 8 4>;
274 qcom,ipc-2 = <&l2cc 8 14>;
275 qcom,ipc-3 = <&l2cc 8 23>;
276 qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>;
277
278 apps_smsm: apps@0 {
279 reg = <0>;
280 #qcom,smem-state-cells = <1>;
281 };
282
283 modem_smsm: modem@1 {
284 reg = <1>;
285 interrupts = <0 38 IRQ_TYPE_EDGE_RISING>;
286
287 interrupt-controller;
288 #interrupt-cells = <2>;
289 };
290
291 q6_smsm: q6@2 {
292 reg = <2>;
293 interrupts = <0 89 IRQ_TYPE_EDGE_RISING>;
294
295 interrupt-controller;
296 #interrupt-cells = <2>;
297 };
298
299 wcnss_smsm: wcnss@3 {
300 reg = <3>;
301 interrupts = <0 204 IRQ_TYPE_EDGE_RISING>;
302
303 interrupt-controller;
304 #interrupt-cells = <2>;
305 };
306
307 dsps_smsm: dsps@4 {
308 reg = <4>;
309 interrupts = <0 137 IRQ_TYPE_EDGE_RISING>;
310
311 interrupt-controller;
312 #interrupt-cells = <2>;
313 };
314 };
315
316 firmware {
317 scm {
318 compatible = "qcom,scm-apq8064";
319
320 clocks = <&rpmcc RPM_DAYTONA_FABRIC_CLK>;
321 clock-names = "core";
322 };
323 };
324
325
326 /*
327 * These channels from the ADC are simply hardware monitors.
328 * That is why the ADC is referred to as "HKADC" - HouseKeeping
329 * ADC.
330 */
331 iio-hwmon {
332 compatible = "iio-hwmon";
333 io-channels = <&xoadc 0x00 0x01>, /* Battery */
334 <&xoadc 0x00 0x02>, /* DC in (charger) */
335 <&xoadc 0x00 0x04>, /* VPH the main system voltage */
336 <&xoadc 0x00 0x0b>, /* Die temperature */
337 <&xoadc 0x00 0x0c>, /* Reference voltage 1.25V */
338 <&xoadc 0x00 0x0d>, /* Reference voltage 0.625V */
339 <&xoadc 0x00 0x0e>; /* Charger temperature */
340 };
341
342 soc: soc {
343 #address-cells = <1>;
344 #size-cells = <1>;
345 ranges;
346 compatible = "simple-bus";
347
348 tlmm_pinmux: pinctrl@800000 {
349 compatible = "qcom,apq8064-pinctrl";
350 reg = <0x800000 0x4000>;
351
352 gpio-controller;
353 #gpio-cells = <2>;
354 interrupt-controller;
355 #interrupt-cells = <2>;
356 interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
357
358 pinctrl-names = "default";
359 pinctrl-0 = <&ps_hold>;
360 };
361
362 sfpb_wrapper_mutex: syscon@1200000 {
363 compatible = "syscon";
364 reg = <0x01200000 0x8000>;
365 };
366
367 intc: interrupt-controller@2000000 {
368 compatible = "qcom,msm-qgic2";
369 interrupt-controller;
370 #interrupt-cells = <3>;
371 reg = <0x02000000 0x1000>,
372 <0x02002000 0x1000>;
373 };
374
375 timer@200a000 {
376 compatible = "qcom,kpss-timer",
377 "qcom,kpss-wdt-apq8064", "qcom,msm-timer";
378 interrupts = <1 1 0x301>,
379 <1 2 0x301>,
380 <1 3 0x301>;
381 reg = <0x0200a000 0x100>;
382 clock-frequency = <27000000>,
383 <32768>;
384 cpu-offset = <0x80000>;
385 };
386
387 acc0: clock-controller@2088000 {
388 compatible = "qcom,kpss-acc-v1";
389 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
390 };
391
392 acc1: clock-controller@2098000 {
393 compatible = "qcom,kpss-acc-v1";
394 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
395 };
396
397 acc2: clock-controller@20a8000 {
398 compatible = "qcom,kpss-acc-v1";
399 reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
400 };
401
402 acc3: clock-controller@20b8000 {
403 compatible = "qcom,kpss-acc-v1";
404 reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
405 };
406
407 saw0: power-controller@2089000 {
408 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
409 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
410 regulator;
411 };
412
413 saw1: power-controller@2099000 {
414 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
415 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
416 regulator;
417 };
418
419 saw2: power-controller@20a9000 {
420 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
421 reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
422 regulator;
423 };
424
425 saw3: power-controller@20b9000 {
426 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
427 reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
428 regulator;
429 };
430
431 sps_sic_non_secure: sps-sic-non-secure@12100000 {
432 compatible = "syscon";
433 reg = <0x12100000 0x10000>;
434 };
435
436 gsbi1: gsbi@12440000 {
437 status = "disabled";
438 compatible = "qcom,gsbi-v1.0.0";
439 cell-index = <1>;
440 reg = <0x12440000 0x100>;
441 clocks = <&gcc GSBI1_H_CLK>;
442 clock-names = "iface";
443 #address-cells = <1>;
444 #size-cells = <1>;
445 ranges;
446
447 syscon-tcsr = <&tcsr>;
448
449 gsbi1_serial: serial@12450000 {
450 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
451 reg = <0x12450000 0x100>,
452 <0x12400000 0x03>;
453 interrupts = <0 193 IRQ_TYPE_LEVEL_HIGH>;
454 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
455 clock-names = "core", "iface";
456 status = "disabled";
457 };
458
459 gsbi1_i2c: i2c@12460000 {
460 compatible = "qcom,i2c-qup-v1.1.1";
461 pinctrl-0 = <&i2c1_pins>;
462 pinctrl-1 = <&i2c1_pins_sleep>;
463 pinctrl-names = "default", "sleep";
464 reg = <0x12460000 0x1000>;
465 interrupts = <0 194 IRQ_TYPE_LEVEL_HIGH>;
466 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
467 clock-names = "core", "iface";
468 #address-cells = <1>;
469 #size-cells = <0>;
470 status = "disabled";
471 };
472
473 };
474
475 gsbi2: gsbi@12480000 {
476 status = "disabled";
477 compatible = "qcom,gsbi-v1.0.0";
478 cell-index = <2>;
479 reg = <0x12480000 0x100>;
480 clocks = <&gcc GSBI2_H_CLK>;
481 clock-names = "iface";
482 #address-cells = <1>;
483 #size-cells = <1>;
484 ranges;
485
486 syscon-tcsr = <&tcsr>;
487
488 gsbi2_i2c: i2c@124a0000 {
489 compatible = "qcom,i2c-qup-v1.1.1";
490 reg = <0x124a0000 0x1000>;
491 pinctrl-0 = <&i2c2_pins>;
492 pinctrl-1 = <&i2c2_pins_sleep>;
493 pinctrl-names = "default", "sleep";
494 interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>;
495 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
496 clock-names = "core", "iface";
497 #address-cells = <1>;
498 #size-cells = <0>;
499 status = "disabled";
500 };
501 };
502
503 gsbi3: gsbi@16200000 {
504 status = "disabled";
505 compatible = "qcom,gsbi-v1.0.0";
506 cell-index = <3>;
507 reg = <0x16200000 0x100>;
508 clocks = <&gcc GSBI3_H_CLK>;
509 clock-names = "iface";
510 #address-cells = <1>;
511 #size-cells = <1>;
512 ranges;
513 gsbi3_i2c: i2c@16280000 {
514 compatible = "qcom,i2c-qup-v1.1.1";
515 pinctrl-0 = <&i2c3_pins>;
516 pinctrl-1 = <&i2c3_pins_sleep>;
517 pinctrl-names = "default", "sleep";
518 reg = <0x16280000 0x1000>;
519 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
520 clocks = <&gcc GSBI3_QUP_CLK>,
521 <&gcc GSBI3_H_CLK>;
522 clock-names = "core", "iface";
523 #address-cells = <1>;
524 #size-cells = <0>;
525 status = "disabled";
526 };
527 };
528
529 gsbi4: gsbi@16300000 {
530 status = "disabled";
531 compatible = "qcom,gsbi-v1.0.0";
532 cell-index = <4>;
533 reg = <0x16300000 0x03>;
534 clocks = <&gcc GSBI4_H_CLK>;
535 clock-names = "iface";
536 #address-cells = <1>;
537 #size-cells = <1>;
538 ranges;
539
540 gsbi4_i2c: i2c@16380000 {
541 compatible = "qcom,i2c-qup-v1.1.1";
542 pinctrl-0 = <&i2c4_pins>;
543 pinctrl-1 = <&i2c4_pins_sleep>;
544 pinctrl-names = "default", "sleep";
545 reg = <0x16380000 0x1000>;
546 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
547 clocks = <&gcc GSBI4_QUP_CLK>,
548 <&gcc GSBI4_H_CLK>;
549 clock-names = "core", "iface";
550 status = "disabled";
551 };
552 };
553
554 gsbi5: gsbi@1a200000 {
555 status = "disabled";
556 compatible = "qcom,gsbi-v1.0.0";
557 cell-index = <5>;
558 reg = <0x1a200000 0x03>;
559 clocks = <&gcc GSBI5_H_CLK>;
560 clock-names = "iface";
561 #address-cells = <1>;
562 #size-cells = <1>;
563 ranges;
564
565 gsbi5_serial: serial@1a240000 {
566 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
567 reg = <0x1a240000 0x100>,
568 <0x1a200000 0x03>;
569 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
570 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
571 clock-names = "core", "iface";
572 status = "disabled";
573 };
574
575 gsbi5_spi: spi@1a280000 {
576 compatible = "qcom,spi-qup-v1.1.1";
577 reg = <0x1a280000 0x1000>;
578 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
579 pinctrl-0 = <&spi5_default>;
580 pinctrl-1 = <&spi5_sleep>;
581 pinctrl-names = "default", "sleep";
582 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
583 clock-names = "core", "iface";
584 status = "disabled";
585 #address-cells = <1>;
586 #size-cells = <0>;
587 };
588 };
589
590 gsbi6: gsbi@16500000 {
591 status = "disabled";
592 compatible = "qcom,gsbi-v1.0.0";
593 cell-index = <6>;
594 reg = <0x16500000 0x03>;
595 clocks = <&gcc GSBI6_H_CLK>;
596 clock-names = "iface";
597 #address-cells = <1>;
598 #size-cells = <1>;
599 ranges;
600
601 gsbi6_serial: serial@16540000 {
602 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
603 reg = <0x16540000 0x100>,
604 <0x16500000 0x03>;
605 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
606 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
607 clock-names = "core", "iface";
608 status = "disabled";
609 };
610
611 gsbi6_i2c: i2c@16580000 {
612 compatible = "qcom,i2c-qup-v1.1.1";
613 pinctrl-0 = <&i2c6_pins>;
614 pinctrl-1 = <&i2c6_pins_sleep>;
615 pinctrl-names = "default", "sleep";
616 reg = <0x16580000 0x1000>;
617 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
618 clocks = <&gcc GSBI6_QUP_CLK>,
619 <&gcc GSBI6_H_CLK>;
620 clock-names = "core", "iface";
621 status = "disabled";
622 };
623 };
624
625 gsbi7: gsbi@16600000 {
626 status = "disabled";
627 compatible = "qcom,gsbi-v1.0.0";
628 cell-index = <7>;
629 reg = <0x16600000 0x100>;
630 clocks = <&gcc GSBI7_H_CLK>;
631 clock-names = "iface";
632 #address-cells = <1>;
633 #size-cells = <1>;
634 ranges;
635 syscon-tcsr = <&tcsr>;
636
637 gsbi7_serial: serial@16640000 {
638 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
639 reg = <0x16640000 0x1000>,
640 <0x16600000 0x1000>;
641 interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
642 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
643 clock-names = "core", "iface";
644 status = "disabled";
645 };
646
647 gsbi7_i2c: i2c@16680000 {
648 compatible = "qcom,i2c-qup-v1.1.1";
649 pinctrl-0 = <&i2c7_pins>;
650 pinctrl-1 = <&i2c7_pins_sleep>;
651 pinctrl-names = "default", "sleep";
652 reg = <0x16680000 0x1000>;
653 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
654 clocks = <&gcc GSBI7_QUP_CLK>,
655 <&gcc GSBI7_H_CLK>;
656 clock-names = "core", "iface";
657 status = "disabled";
658 };
659 };
660
661 rng@1a500000 {
662 compatible = "qcom,prng";
663 reg = <0x1a500000 0x200>;
664 clocks = <&gcc PRNG_CLK>;
665 clock-names = "core";
666 };
667
668 ssbi@c00000 {
669 compatible = "qcom,ssbi";
670 reg = <0x00c00000 0x1000>;
671 qcom,controller-type = "pmic-arbiter";
672
673 pm8821: pmic@1 {
674 compatible = "qcom,pm8821";
675 interrupt-parent = <&tlmm_pinmux>;
676 interrupts = <76 IRQ_TYPE_LEVEL_LOW>;
677 #interrupt-cells = <2>;
678 interrupt-controller;
679 #address-cells = <1>;
680 #size-cells = <0>;
681
682 pm8821_mpps: mpps@50 {
683 compatible = "qcom,pm8821-mpp", "qcom,ssbi-mpp";
684 reg = <0x50>;
685 interrupts = <24 IRQ_TYPE_NONE>,
686 <25 IRQ_TYPE_NONE>,
687 <26 IRQ_TYPE_NONE>,
688 <27 IRQ_TYPE_NONE>;
689 gpio-controller;
690 #gpio-cells = <2>;
691 };
692 };
693 };
694
695 qcom,ssbi@500000 {
696 compatible = "qcom,ssbi";
697 reg = <0x00500000 0x1000>;
698 qcom,controller-type = "pmic-arbiter";
699
700 pmicintc: pmic@0 {
701 compatible = "qcom,pm8921";
702 interrupt-parent = <&tlmm_pinmux>;
703 interrupts = <74 8>;
704 #interrupt-cells = <2>;
705 interrupt-controller;
706 #address-cells = <1>;
707 #size-cells = <0>;
708
709 pm8921_gpio: gpio@150 {
710
711 compatible = "qcom,pm8921-gpio",
712 "qcom,ssbi-gpio";
713 reg = <0x150>;
714 interrupts = <192 IRQ_TYPE_NONE>,
715 <193 IRQ_TYPE_NONE>,
716 <194 IRQ_TYPE_NONE>,
717 <195 IRQ_TYPE_NONE>,
718 <196 IRQ_TYPE_NONE>,
719 <197 IRQ_TYPE_NONE>,
720 <198 IRQ_TYPE_NONE>,
721 <199 IRQ_TYPE_NONE>,
722 <200 IRQ_TYPE_NONE>,
723 <201 IRQ_TYPE_NONE>,
724 <202 IRQ_TYPE_NONE>,
725 <203 IRQ_TYPE_NONE>,
726 <204 IRQ_TYPE_NONE>,
727 <205 IRQ_TYPE_NONE>,
728 <206 IRQ_TYPE_NONE>,
729 <207 IRQ_TYPE_NONE>,
730 <208 IRQ_TYPE_NONE>,
731 <209 IRQ_TYPE_NONE>,
732 <210 IRQ_TYPE_NONE>,
733 <211 IRQ_TYPE_NONE>,
734 <212 IRQ_TYPE_NONE>,
735 <213 IRQ_TYPE_NONE>,
736 <214 IRQ_TYPE_NONE>,
737 <215 IRQ_TYPE_NONE>,
738 <216 IRQ_TYPE_NONE>,
739 <217 IRQ_TYPE_NONE>,
740 <218 IRQ_TYPE_NONE>,
741 <219 IRQ_TYPE_NONE>,
742 <220 IRQ_TYPE_NONE>,
743 <221 IRQ_TYPE_NONE>,
744 <222 IRQ_TYPE_NONE>,
745 <223 IRQ_TYPE_NONE>,
746 <224 IRQ_TYPE_NONE>,
747 <225 IRQ_TYPE_NONE>,
748 <226 IRQ_TYPE_NONE>,
749 <227 IRQ_TYPE_NONE>,
750 <228 IRQ_TYPE_NONE>,
751 <229 IRQ_TYPE_NONE>,
752 <230 IRQ_TYPE_NONE>,
753 <231 IRQ_TYPE_NONE>,
754 <232 IRQ_TYPE_NONE>,
755 <233 IRQ_TYPE_NONE>,
756 <234 IRQ_TYPE_NONE>,
757 <235 IRQ_TYPE_NONE>;
758 gpio-controller;
759 #gpio-cells = <2>;
760
761 };
762
763 pm8921_mpps: mpps@50 {
764 compatible = "qcom,pm8921-mpp",
765 "qcom,ssbi-mpp";
766 reg = <0x50>;
767 gpio-controller;
768 #gpio-cells = <2>;
769 interrupts =
770 <128 IRQ_TYPE_NONE>,
771 <129 IRQ_TYPE_NONE>,
772 <130 IRQ_TYPE_NONE>,
773 <131 IRQ_TYPE_NONE>,
774 <132 IRQ_TYPE_NONE>,
775 <133 IRQ_TYPE_NONE>,
776 <134 IRQ_TYPE_NONE>,
777 <135 IRQ_TYPE_NONE>,
778 <136 IRQ_TYPE_NONE>,
779 <137 IRQ_TYPE_NONE>,
780 <138 IRQ_TYPE_NONE>,
781 <139 IRQ_TYPE_NONE>;
782 };
783
784 rtc@11d {
785 compatible = "qcom,pm8921-rtc";
786 interrupt-parent = <&pmicintc>;
787 interrupts = <39 1>;
788 reg = <0x11d>;
789 allow-set-time;
790 };
791
792 pwrkey@1c {
793 compatible = "qcom,pm8921-pwrkey";
794 reg = <0x1c>;
795 interrupt-parent = <&pmicintc>;
796 interrupts = <50 1>, <51 1>;
797 debounce = <15625>;
798 pull-up;
799 };
800
801 xoadc: xoadc@197 {
802 compatible = "qcom,pm8921-adc";
803 reg = <197>;
804 interrupts-extended = <&pmicintc 78 IRQ_TYPE_EDGE_RISING>;
805 #address-cells = <2>;
806 #size-cells = <0>;
807 #io-channel-cells = <2>;
808
809 vcoin: adc-channel@00 {
810 reg = <0x00 0x00>;
811 };
812 vbat: adc-channel@01 {
813 reg = <0x00 0x01>;
814 };
815 dcin: adc-channel@02 {
816 reg = <0x00 0x02>;
817 };
818 vph_pwr: adc-channel@04 {
819 reg = <0x00 0x04>;
820 };
821 batt_therm: adc-channel@08 {
822 reg = <0x00 0x08>;
823 };
824 batt_id: adc-channel@09 {
825 reg = <0x00 0x09>;
826 };
827 usb_vbus: adc-channel@0a {
828 reg = <0x00 0x0a>;
829 };
830 die_temp: adc-channel@0b {
831 reg = <0x00 0x0b>;
832 };
833 ref_625mv: adc-channel@0c {
834 reg = <0x00 0x0c>;
835 };
836 ref_1250mv: adc-channel@0d {
837 reg = <0x00 0x0d>;
838 };
839 chg_temp: adc-channel@0e {
840 reg = <0x00 0x0e>;
841 };
842 ref_muxoff: adc-channel@0f {
843 reg = <0x00 0x0f>;
844 };
845 };
846 };
847 };
848
849 qfprom: qfprom@700000 {
850 compatible = "qcom,qfprom";
851 reg = <0x00700000 0x1000>;
852 #address-cells = <1>;
853 #size-cells = <1>;
854 ranges;
855 tsens_calib: calib {
856 reg = <0x404 0x10>;
857 };
858 tsens_backup: backup_calib {
859 reg = <0x414 0x10>;
860 };
861 };
862
863 gcc: clock-controller@900000 {
864 compatible = "qcom,gcc-apq8064";
865 reg = <0x00900000 0x4000>;
866 nvmem-cells = <&tsens_calib>, <&tsens_backup>;
867 nvmem-cell-names = "calib", "calib_backup";
868 #clock-cells = <1>;
869 #reset-cells = <1>;
870 #thermal-sensor-cells = <1>;
871 };
872
873 lcc: clock-controller@28000000 {
874 compatible = "qcom,lcc-apq8064";
875 reg = <0x28000000 0x1000>;
876 #clock-cells = <1>;
877 #reset-cells = <1>;
878 };
879
880 mmcc: clock-controller@4000000 {
881 compatible = "qcom,mmcc-apq8064";
882 reg = <0x4000000 0x1000>;
883 #clock-cells = <1>;
884 #reset-cells = <1>;
885 };
886
887 l2cc: clock-controller@2011000 {
888 compatible = "syscon";
889 reg = <0x2011000 0x1000>;
890 };
891
892 rpm@108000 {
893 compatible = "qcom,rpm-apq8064";
894 reg = <0x108000 0x1000>;
895 qcom,ipc = <&l2cc 0x8 2>;
896
897 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
898 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
899 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
900 interrupt-names = "ack", "err", "wakeup";
901
902 rpmcc: clock-controller {
903 compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc";
904 #clock-cells = <1>;
905 };
906
907 regulators {
908 compatible = "qcom,rpm-pm8921-regulators";
909
910 pm8921_s1: s1 {};
911 pm8921_s2: s2 {};
912 pm8921_s3: s3 {};
913 pm8921_s4: s4 {};
914 pm8921_s7: s7 {};
915 pm8921_s8: s8 {};
916
917 pm8921_l1: l1 {};
918 pm8921_l2: l2 {};
919 pm8921_l3: l3 {};
920 pm8921_l4: l4 {};
921 pm8921_l5: l5 {};
922 pm8921_l6: l6 {};
923 pm8921_l7: l7 {};
924 pm8921_l8: l8 {};
925 pm8921_l9: l9 {};
926 pm8921_l10: l10 {};
927 pm8921_l11: l11 {};
928 pm8921_l12: l12 {};
929 pm8921_l14: l14 {};
930 pm8921_l15: l15 {};
931 pm8921_l16: l16 {};
932 pm8921_l17: l17 {};
933 pm8921_l18: l18 {};
934 pm8921_l21: l21 {};
935 pm8921_l22: l22 {};
936 pm8921_l23: l23 {};
937 pm8921_l24: l24 {};
938 pm8921_l25: l25 {};
939 pm8921_l26: l26 {};
940 pm8921_l27: l27 {};
941 pm8921_l28: l28 {};
942 pm8921_l29: l29 {};
943
944 pm8921_lvs1: lvs1 {};
945 pm8921_lvs2: lvs2 {};
946 pm8921_lvs3: lvs3 {};
947 pm8921_lvs4: lvs4 {};
948 pm8921_lvs5: lvs5 {};
949 pm8921_lvs6: lvs6 {};
950 pm8921_lvs7: lvs7 {};
951
952 pm8921_usb_switch: usb-switch {};
953
954 pm8921_hdmi_switch: hdmi-switch {
955 bias-pull-down;
956 };
957
958 pm8921_ncp: ncp {};
959 };
960 };
961
962 usb1: usb@12500000 {
963 compatible = "qcom,ci-hdrc";
964 reg = <0x12500000 0x200>,
965 <0x12500200 0x200>;
966 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
967 clocks = <&gcc USB_HS1_XCVR_CLK>, <&gcc USB_HS1_H_CLK>;
968 clock-names = "core", "iface";
969 assigned-clocks = <&gcc USB_HS1_XCVR_CLK>;
970 assigned-clock-rates = <60000000>;
971 resets = <&gcc USB_HS1_RESET>;
972 reset-names = "core";
973 phy_type = "ulpi";
974 ahb-burst-config = <0>;
975 phys = <&usb_hs1_phy>;
976 phy-names = "usb-phy";
977 status = "disabled";
978 #reset-cells = <1>;
979
980 ulpi {
981 usb_hs1_phy: phy {
982 compatible = "qcom,usb-hs-phy-apq8064",
983 "qcom,usb-hs-phy";
984 clocks = <&sleep_clk>, <&cxo_board>;
985 clock-names = "sleep", "ref";
986 resets = <&usb1 0>;
987 reset-names = "por";
988 #phy-cells = <0>;
989 };
990 };
991 };
992
993 usb3: usb@12520000 {
994 compatible = "qcom,ci-hdrc";
995 reg = <0x12520000 0x200>,
996 <0x12520200 0x200>;
997 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
998 clocks = <&gcc USB_HS3_XCVR_CLK>, <&gcc USB_HS3_H_CLK>;
999 clock-names = "core", "iface";
1000 assigned-clocks = <&gcc USB_HS3_XCVR_CLK>;
1001 assigned-clock-rates = <60000000>;
1002 resets = <&gcc USB_HS3_RESET>;
1003 reset-names = "core";
1004 phy_type = "ulpi";
1005 ahb-burst-config = <0>;
1006 phys = <&usb_hs3_phy>;
1007 phy-names = "usb-phy";
1008 status = "disabled";
1009 #reset-cells = <1>;
1010
1011 ulpi {
1012 usb_hs3_phy: phy {
1013 compatible = "qcom,usb-hs-phy-apq8064",
1014 "qcom,usb-hs-phy";
1015 #phy-cells = <0>;
1016 clocks = <&sleep_clk>, <&cxo_board>;
1017 clock-names = "sleep", "ref";
1018 resets = <&usb3 0>;
1019 reset-names = "por";
1020 };
1021 };
1022 };
1023
1024 usb4: usb@12530000 {
1025 compatible = "qcom,ci-hdrc";
1026 reg = <0x12530000 0x200>,
1027 <0x12530200 0x200>;
1028 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
1029 clocks = <&gcc USB_HS4_XCVR_CLK>, <&gcc USB_HS4_H_CLK>;
1030 clock-names = "core", "iface";
1031 assigned-clocks = <&gcc USB_HS4_XCVR_CLK>;
1032 assigned-clock-rates = <60000000>;
1033 resets = <&gcc USB_HS4_RESET>;
1034 reset-names = "core";
1035 phy_type = "ulpi";
1036 ahb-burst-config = <0>;
1037 phys = <&usb_hs4_phy>;
1038 phy-names = "usb-phy";
1039 status = "disabled";
1040 #reset-cells = <1>;
1041
1042 ulpi {
1043 usb_hs4_phy: phy {
1044 compatible = "qcom,usb-hs-phy-apq8064",
1045 "qcom,usb-hs-phy";
1046 #phy-cells = <0>;
1047 clocks = <&sleep_clk>, <&cxo_board>;
1048 clock-names = "sleep", "ref";
1049 resets = <&usb4 0>;
1050 reset-names = "por";
1051 };
1052 };
1053 };
1054
1055 sata_phy0: phy@1b400000 {
1056 compatible = "qcom,apq8064-sata-phy";
1057 status = "disabled";
1058 reg = <0x1b400000 0x200>;
1059 reg-names = "phy_mem";
1060 clocks = <&gcc SATA_PHY_CFG_CLK>;
1061 clock-names = "cfg";
1062 #phy-cells = <0>;
1063 };
1064
1065 sata0: sata@29000000 {
1066 compatible = "qcom,apq8064-ahci", "generic-ahci";
1067 status = "disabled";
1068 reg = <0x29000000 0x180>;
1069 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
1070
1071 clocks = <&gcc SFAB_SATA_S_H_CLK>,
1072 <&gcc SATA_H_CLK>,
1073 <&gcc SATA_A_CLK>,
1074 <&gcc SATA_RXOOB_CLK>,
1075 <&gcc SATA_PMALIVE_CLK>;
1076 clock-names = "slave_iface",
1077 "iface",
1078 "bus",
1079 "rxoob",
1080 "core_pmalive";
1081
1082 assigned-clocks = <&gcc SATA_RXOOB_CLK>,
1083 <&gcc SATA_PMALIVE_CLK>;
1084 assigned-clock-rates = <100000000>, <100000000>;
1085
1086 phys = <&sata_phy0>;
1087 phy-names = "sata-phy";
1088 ports-implemented = <0x1>;
1089 };
1090
1091 /* Temporary fixed regulator */
1092 sdcc1bam:dma@12402000{
1093 compatible = "qcom,bam-v1.3.0";
1094 reg = <0x12402000 0x8000>;
1095 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
1096 clocks = <&gcc SDC1_H_CLK>;
1097 clock-names = "bam_clk";
1098 #dma-cells = <1>;
1099 qcom,ee = <0>;
1100 };
1101
1102 sdcc3bam:dma@12182000{
1103 compatible = "qcom,bam-v1.3.0";
1104 reg = <0x12182000 0x8000>;
1105 interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
1106 clocks = <&gcc SDC3_H_CLK>;
1107 clock-names = "bam_clk";
1108 #dma-cells = <1>;
1109 qcom,ee = <0>;
1110 };
1111
1112 sdcc4bam:dma@121c2000{
1113 compatible = "qcom,bam-v1.3.0";
1114 reg = <0x121c2000 0x8000>;
1115 interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
1116 clocks = <&gcc SDC4_H_CLK>;
1117 clock-names = "bam_clk";
1118 #dma-cells = <1>;
1119 qcom,ee = <0>;
1120 };
1121
1122 amba {
1123 compatible = "simple-bus";
1124 #address-cells = <1>;
1125 #size-cells = <1>;
1126 ranges;
1127 sdcc1: sdcc@12400000 {
1128 status = "disabled";
1129 compatible = "arm,pl18x", "arm,primecell";
1130 pinctrl-names = "default";
1131 pinctrl-0 = <&sdcc1_pins>;
1132 arm,primecell-periphid = <0x00051180>;
1133 reg = <0x12400000 0x2000>;
1134 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1135 interrupt-names = "cmd_irq";
1136 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
1137 clock-names = "mclk", "apb_pclk";
1138 bus-width = <8>;
1139 max-frequency = <96000000>;
1140 non-removable;
1141 cap-sd-highspeed;
1142 cap-mmc-highspeed;
1143 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
1144 dma-names = "tx", "rx";
1145 };
1146
1147 sdcc3: sdcc@12180000 {
1148 compatible = "arm,pl18x", "arm,primecell";
1149 arm,primecell-periphid = <0x00051180>;
1150 status = "disabled";
1151 reg = <0x12180000 0x2000>;
1152 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1153 interrupt-names = "cmd_irq";
1154 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
1155 clock-names = "mclk", "apb_pclk";
1156 bus-width = <4>;
1157 cap-sd-highspeed;
1158 cap-mmc-highspeed;
1159 max-frequency = <192000000>;
1160 no-1-8-v;
1161 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
1162 dma-names = "tx", "rx";
1163 };
1164
1165 sdcc4: sdcc@121c0000 {
1166 compatible = "arm,pl18x", "arm,primecell";
1167 arm,primecell-periphid = <0x00051180>;
1168 status = "disabled";
1169 reg = <0x121c0000 0x2000>;
1170 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1171 interrupt-names = "cmd_irq";
1172 clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
1173 clock-names = "mclk", "apb_pclk";
1174 bus-width = <4>;
1175 cap-sd-highspeed;
1176 cap-mmc-highspeed;
1177 max-frequency = <48000000>;
1178 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
1179 dma-names = "tx", "rx";
1180 pinctrl-names = "default";
1181 pinctrl-0 = <&sdc4_gpios>;
1182 };
1183 };
1184
1185 tcsr: syscon@1a400000 {
1186 compatible = "qcom,tcsr-apq8064", "syscon";
1187 reg = <0x1a400000 0x100>;
1188 };
1189
1190 gpu: adreno-3xx@4300000 {
1191 compatible = "qcom,adreno-3xx";
1192 reg = <0x04300000 0x20000>;
1193 reg-names = "kgsl_3d0_reg_memory";
1194 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1195 interrupt-names = "kgsl_3d0_irq";
1196 clock-names =
1197 "core_clk",
1198 "iface_clk",
1199 "mem_clk",
1200 "mem_iface_clk";
1201 clocks =
1202 <&mmcc GFX3D_CLK>,
1203 <&mmcc GFX3D_AHB_CLK>,
1204 <&mmcc GFX3D_AXI_CLK>,
1205 <&mmcc MMSS_IMEM_AHB_CLK>;
1206 qcom,chipid = <0x03020002>;
1207
1208 iommus = <&gfx3d 0
1209 &gfx3d 1
1210 &gfx3d 2
1211 &gfx3d 3
1212 &gfx3d 4
1213 &gfx3d 5
1214 &gfx3d 6
1215 &gfx3d 7
1216 &gfx3d 8
1217 &gfx3d 9
1218 &gfx3d 10
1219 &gfx3d 11
1220 &gfx3d 12
1221 &gfx3d 13
1222 &gfx3d 14
1223 &gfx3d 15
1224 &gfx3d 16
1225 &gfx3d 17
1226 &gfx3d 18
1227 &gfx3d 19
1228 &gfx3d 20
1229 &gfx3d 21
1230 &gfx3d 22
1231 &gfx3d 23
1232 &gfx3d 24
1233 &gfx3d 25
1234 &gfx3d 26
1235 &gfx3d 27
1236 &gfx3d 28
1237 &gfx3d 29
1238 &gfx3d 30
1239 &gfx3d 31
1240 &gfx3d1 0
1241 &gfx3d1 1
1242 &gfx3d1 2
1243 &gfx3d1 3
1244 &gfx3d1 4
1245 &gfx3d1 5
1246 &gfx3d1 6
1247 &gfx3d1 7
1248 &gfx3d1 8
1249 &gfx3d1 9
1250 &gfx3d1 10
1251 &gfx3d1 11
1252 &gfx3d1 12
1253 &gfx3d1 13
1254 &gfx3d1 14
1255 &gfx3d1 15
1256 &gfx3d1 16
1257 &gfx3d1 17
1258 &gfx3d1 18
1259 &gfx3d1 19
1260 &gfx3d1 20
1261 &gfx3d1 21
1262 &gfx3d1 22
1263 &gfx3d1 23
1264 &gfx3d1 24
1265 &gfx3d1 25
1266 &gfx3d1 26
1267 &gfx3d1 27
1268 &gfx3d1 28
1269 &gfx3d1 29
1270 &gfx3d1 30
1271 &gfx3d1 31>;
1272
1273 qcom,gpu-pwrlevels {
1274 compatible = "qcom,gpu-pwrlevels";
1275 qcom,gpu-pwrlevel@0 {
1276 qcom,gpu-freq = <450000000>;
1277 };
1278 qcom,gpu-pwrlevel@1 {
1279 qcom,gpu-freq = <27000000>;
1280 };
1281 };
1282 };
1283
1284 mmss_sfpb: syscon@5700000 {
1285 compatible = "syscon";
1286 reg = <0x5700000 0x70>;
1287 };
1288
1289 dsi0: mdss_dsi@4700000 {
1290 compatible = "qcom,mdss-dsi-ctrl";
1291 label = "MDSS DSI CTRL->0";
1292 #address-cells = <1>;
1293 #size-cells = <0>;
1294 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1295 reg = <0x04700000 0x200>;
1296 reg-names = "dsi_ctrl";
1297
1298 clocks = <&mmcc DSI_M_AHB_CLK>,
1299 <&mmcc DSI_S_AHB_CLK>,
1300 <&mmcc AMP_AHB_CLK>,
1301 <&mmcc DSI_CLK>,
1302 <&mmcc DSI1_BYTE_CLK>,
1303 <&mmcc DSI_PIXEL_CLK>,
1304 <&mmcc DSI1_ESC_CLK>;
1305 clock-names = "iface_clk", "bus_clk", "core_mmss_clk",
1306 "src_clk", "byte_clk", "pixel_clk",
1307 "core_clk";
1308
1309 assigned-clocks = <&mmcc DSI1_BYTE_SRC>,
1310 <&mmcc DSI1_ESC_SRC>,
1311 <&mmcc DSI_SRC>,
1312 <&mmcc DSI_PIXEL_SRC>;
1313 assigned-clock-parents = <&dsi0_phy 0>,
1314 <&dsi0_phy 0>,
1315 <&dsi0_phy 1>,
1316 <&dsi0_phy 1>;
1317 syscon-sfpb = <&mmss_sfpb>;
1318 phys = <&dsi0_phy>;
1319 ports {
1320 #address-cells = <1>;
1321 #size-cells = <0>;
1322
1323 port@0 {
1324 reg = <0>;
1325 dsi0_in: endpoint {
1326 };
1327 };
1328
1329 port@1 {
1330 reg = <1>;
1331 dsi0_out: endpoint {
1332 };
1333 };
1334 };
1335 };
1336
1337
1338 dsi0_phy: dsi-phy@4700200 {
1339 compatible = "qcom,dsi-phy-28nm-8960";
1340 #clock-cells = <1>;
1341 #phy-cells = <0>;
1342
1343 reg = <0x04700200 0x100>,
1344 <0x04700300 0x200>,
1345 <0x04700500 0x5c>;
1346 reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator";
1347 clock-names = "iface_clk";
1348 clocks = <&mmcc DSI_M_AHB_CLK>;
1349 };
1350
1351
1352 mdp_port0: iommu@7500000 {
1353 compatible = "qcom,apq8064-iommu";
1354 #iommu-cells = <1>;
1355 clock-names =
1356 "smmu_pclk",
1357 "iommu_clk";
1358 clocks =
1359 <&mmcc SMMU_AHB_CLK>,
1360 <&mmcc MDP_AXI_CLK>;
1361 reg = <0x07500000 0x100000>;
1362 interrupts =
1363 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
1364 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
1365 qcom,ncb = <2>;
1366 };
1367
1368 mdp_port1: iommu@7600000 {
1369 compatible = "qcom,apq8064-iommu";
1370 #iommu-cells = <1>;
1371 clock-names =
1372 "smmu_pclk",
1373 "iommu_clk";
1374 clocks =
1375 <&mmcc SMMU_AHB_CLK>,
1376 <&mmcc MDP_AXI_CLK>;
1377 reg = <0x07600000 0x100000>;
1378 interrupts =
1379 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
1380 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1381 qcom,ncb = <2>;
1382 };
1383
1384 gfx3d: iommu@7c00000 {
1385 compatible = "qcom,apq8064-iommu";
1386 #iommu-cells = <1>;
1387 clock-names =
1388 "smmu_pclk",
1389 "iommu_clk";
1390 clocks =
1391 <&mmcc SMMU_AHB_CLK>,
1392 <&mmcc GFX3D_AXI_CLK>;
1393 reg = <0x07c00000 0x100000>;
1394 interrupts =
1395 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
1396 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1397 qcom,ncb = <3>;
1398 };
1399
1400 gfx3d1: iommu@7d00000 {
1401 compatible = "qcom,apq8064-iommu";
1402 #iommu-cells = <1>;
1403 clock-names =
1404 "smmu_pclk",
1405 "iommu_clk";
1406 clocks =
1407 <&mmcc SMMU_AHB_CLK>,
1408 <&mmcc GFX3D_AXI_CLK>;
1409 reg = <0x07d00000 0x100000>;
1410 interrupts =
1411 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
1412 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
1413 qcom,ncb = <3>;
1414 };
1415
1416 pcie: pci@1b500000 {
1417 compatible = "qcom,pcie-apq8064", "snps,dw-pcie";
1418 reg = <0x1b500000 0x1000
1419 0x1b502000 0x80
1420 0x1b600000 0x100
1421 0x0ff00000 0x100000>;
1422 reg-names = "dbi", "elbi", "parf", "config";
1423 device_type = "pci";
1424 linux,pci-domain = <0>;
1425 bus-range = <0x00 0xff>;
1426 num-lanes = <1>;
1427 #address-cells = <3>;
1428 #size-cells = <2>;
1429 ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* I/O */
1430 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* memory */
1431 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
1432 interrupt-names = "msi";
1433 #interrupt-cells = <1>;
1434 interrupt-map-mask = <0 0 0 0x7>;
1435 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1436 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1437 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1438 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1439 clocks = <&gcc PCIE_A_CLK>,
1440 <&gcc PCIE_H_CLK>,
1441 <&gcc PCIE_PHY_REF_CLK>;
1442 clock-names = "core", "iface", "phy";
1443 resets = <&gcc PCIE_ACLK_RESET>,
1444 <&gcc PCIE_HCLK_RESET>,
1445 <&gcc PCIE_POR_RESET>,
1446 <&gcc PCIE_PCI_RESET>,
1447 <&gcc PCIE_PHY_RESET>;
1448 reset-names = "axi", "ahb", "por", "pci", "phy";
1449 status = "disabled";
1450 };
1451
1452 hdmi: hdmi-tx@4a00000 {
1453 compatible = "qcom,hdmi-tx-8960";
1454 pinctrl-names = "default";
1455 pinctrl-0 = <&hdmi_pinctrl>;
1456 reg = <0x04a00000 0x2f0>;
1457 reg-names = "core_physical";
1458 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1459 clocks = <&mmcc HDMI_APP_CLK>,
1460 <&mmcc HDMI_M_AHB_CLK>,
1461 <&mmcc HDMI_S_AHB_CLK>;
1462 clock-names = "core_clk",
1463 "master_iface_clk",
1464 "slave_iface_clk";
1465
1466 phys = <&hdmi_phy>;
1467 phy-names = "hdmi-phy";
1468
1469 ports {
1470 #address-cells = <1>;
1471 #size-cells = <0>;
1472
1473 port@0 {
1474 reg = <0>;
1475 hdmi_in: endpoint {
1476 };
1477 };
1478
1479 port@1 {
1480 reg = <1>;
1481 hdmi_out: endpoint {
1482 };
1483 };
1484 };
1485 };
1486
1487 hdmi_phy: hdmi-phy@4a00400 {
1488 compatible = "qcom,hdmi-phy-8960";
1489 reg = <0x4a00400 0x60>,
1490 <0x4a00500 0x100>;
1491 reg-names = "hdmi_phy",
1492 "hdmi_pll";
1493
1494 clocks = <&mmcc HDMI_S_AHB_CLK>;
1495 clock-names = "slave_iface_clk";
1496 #phy-cells = <0>;
1497 };
1498
1499 mdp: mdp@5100000 {
1500 compatible = "qcom,mdp4";
1501 reg = <0x05100000 0xf0000>;
1502 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1503 clocks = <&mmcc MDP_CLK>,
1504 <&mmcc MDP_AHB_CLK>,
1505 <&mmcc MDP_AXI_CLK>,
1506 <&mmcc MDP_LUT_CLK>,
1507 <&mmcc HDMI_TV_CLK>,
1508 <&mmcc MDP_TV_CLK>;
1509 clock-names = "core_clk",
1510 "iface_clk",
1511 "bus_clk",
1512 "lut_clk",
1513 "hdmi_clk",
1514 "tv_clk";
1515
1516 iommus = <&mdp_port0 0
1517 &mdp_port0 2
1518 &mdp_port1 0
1519 &mdp_port1 2>;
1520
1521 ports {
1522 #address-cells = <1>;
1523 #size-cells = <0>;
1524
1525 port@0 {
1526 reg = <0>;
1527 mdp_lvds_out: endpoint {
1528 };
1529 };
1530
1531 port@1 {
1532 reg = <1>;
1533 mdp_dsi1_out: endpoint {
1534 };
1535 };
1536
1537 port@2 {
1538 reg = <2>;
1539 mdp_dsi2_out: endpoint {
1540 };
1541 };
1542
1543 port@3 {
1544 reg = <3>;
1545 mdp_dtv_out: endpoint {
1546 };
1547 };
1548 };
1549 };
1550
1551 riva: riva-pil@3204000 {
1552 compatible = "qcom,riva-pil";
1553
1554 reg = <0x03200800 0x1000>, <0x03202000 0x2000>, <0x03204000 0x100>;
1555 reg-names = "ccu", "dxe", "pmu";
1556
1557 interrupts-extended = <&intc GIC_SPI 199 IRQ_TYPE_EDGE_RISING>,
1558 <&wcnss_smsm 6 IRQ_TYPE_EDGE_RISING>;
1559 interrupt-names = "wdog", "fatal";
1560
1561 memory-region = <&wcnss_mem>;
1562
1563 vddcx-supply = <&pm8921_s3>;
1564 vddmx-supply = <&pm8921_l24>;
1565 vddpx-supply = <&pm8921_s4>;
1566
1567 status = "disabled";
1568
1569 iris {
1570 compatible = "qcom,wcn3660";
1571
1572 clocks = <&cxo_board>;
1573 clock-names = "xo";
1574
1575 vddxo-supply = <&pm8921_l4>;
1576 vddrfa-supply = <&pm8921_s2>;
1577 vddpa-supply = <&pm8921_l10>;
1578 vdddig-supply = <&pm8921_lvs2>;
1579 };
1580
1581 smd-edge {
1582 interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>;
1583
1584 qcom,ipc = <&l2cc 8 25>;
1585 qcom,smd-edge = <6>;
1586
1587 label = "riva";
1588
1589 wcnss {
1590 compatible = "qcom,wcnss";
1591 qcom,smd-channels = "WCNSS_CTRL";
1592
1593 qcom,mmio = <&riva>;
1594
1595 bt {
1596 compatible = "qcom,wcnss-bt";
1597 };
1598
1599 wifi {
1600 compatible = "qcom,wcnss-wlan";
1601
1602 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
1603 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
1604 interrupt-names = "tx", "rx";
1605
1606 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
1607 qcom,smem-state-names = "tx-enable", "tx-rings-empty";
1608 };
1609 };
1610 };
1611 };
1612
1613 etb@1a01000 {
1614 compatible = "coresight-etb10", "arm,primecell";
1615 reg = <0x1a01000 0x1000>;
1616
1617 clocks = <&rpmcc RPM_QDSS_CLK>;
1618 clock-names = "apb_pclk";
1619
1620 in-ports {
1621 port {
1622 etb_in: endpoint {
1623 remote-endpoint = <&replicator_out0>;
1624 };
1625 };
1626 };
1627 };
1628
1629 tpiu@1a03000 {
1630 compatible = "arm,coresight-tpiu", "arm,primecell";
1631 reg = <0x1a03000 0x1000>;
1632
1633 clocks = <&rpmcc RPM_QDSS_CLK>;
1634 clock-names = "apb_pclk";
1635
1636 in-ports {
1637 port {
1638 tpiu_in: endpoint {
1639 remote-endpoint = <&replicator_out1>;
1640 };
1641 };
1642 };
1643 };
1644
1645 replicator {
1646 compatible = "arm,coresight-replicator";
1647
1648 clocks = <&rpmcc RPM_QDSS_CLK>;
1649 clock-names = "apb_pclk";
1650
1651 out-ports {
1652 #address-cells = <1>;
1653 #size-cells = <0>;
1654
1655 port@0 {
1656 reg = <0>;
1657 replicator_out0: endpoint {
1658 remote-endpoint = <&etb_in>;
1659 };
1660 };
1661 port@1 {
1662 reg = <1>;
1663 replicator_out1: endpoint {
1664 remote-endpoint = <&tpiu_in>;
1665 };
1666 };
1667 };
1668
1669 in-ports {
1670 port {
1671 replicator_in: endpoint {
1672 remote-endpoint = <&funnel_out>;
1673 };
1674 };
1675 };
1676 };
1677
1678 funnel@1a04000 {
1679 compatible = "arm,coresight-funnel", "arm,primecell";
1680 reg = <0x1a04000 0x1000>;
1681
1682 clocks = <&rpmcc RPM_QDSS_CLK>;
1683 clock-names = "apb_pclk";
1684
1685 in-ports {
1686 #address-cells = <1>;
1687 #size-cells = <0>;
1688
1689 /*
1690 * Not described input ports:
1691 * 2 - connected to STM component
1692 * 3 - not-connected
1693 * 6 - not-connected
1694 * 7 - not-connected
1695 */
1696 port@0 {
1697 reg = <0>;
1698 funnel_in0: endpoint {
1699 remote-endpoint = <&etm0_out>;
1700 };
1701 };
1702 port@1 {
1703 reg = <1>;
1704 funnel_in1: endpoint {
1705 remote-endpoint = <&etm1_out>;
1706 };
1707 };
1708 port@4 {
1709 reg = <4>;
1710 funnel_in4: endpoint {
1711 remote-endpoint = <&etm2_out>;
1712 };
1713 };
1714 port@5 {
1715 reg = <5>;
1716 funnel_in5: endpoint {
1717 remote-endpoint = <&etm3_out>;
1718 };
1719 };
1720 };
1721
1722 out-ports {
1723 port {
1724 funnel_out: endpoint {
1725 remote-endpoint = <&replicator_in>;
1726 };
1727 };
1728 };
1729 };
1730
1731 etm@1a1c000 {
1732 compatible = "arm,coresight-etm3x", "arm,primecell";
1733 reg = <0x1a1c000 0x1000>;
1734
1735 clocks = <&rpmcc RPM_QDSS_CLK>;
1736 clock-names = "apb_pclk";
1737
1738 cpu = <&CPU0>;
1739
1740 out-ports {
1741 port {
1742 etm0_out: endpoint {
1743 remote-endpoint = <&funnel_in0>;
1744 };
1745 };
1746 };
1747 };
1748
1749 etm@1a1d000 {
1750 compatible = "arm,coresight-etm3x", "arm,primecell";
1751 reg = <0x1a1d000 0x1000>;
1752
1753 clocks = <&rpmcc RPM_QDSS_CLK>;
1754 clock-names = "apb_pclk";
1755
1756 cpu = <&CPU1>;
1757
1758 out-ports {
1759 port {
1760 etm1_out: endpoint {
1761 remote-endpoint = <&funnel_in1>;
1762 };
1763 };
1764 };
1765 };
1766
1767 etm@1a1e000 {
1768 compatible = "arm,coresight-etm3x", "arm,primecell";
1769 reg = <0x1a1e000 0x1000>;
1770
1771 clocks = <&rpmcc RPM_QDSS_CLK>;
1772 clock-names = "apb_pclk";
1773
1774 cpu = <&CPU2>;
1775
1776 out-ports {
1777 port {
1778 etm2_out: endpoint {
1779 remote-endpoint = <&funnel_in4>;
1780 };
1781 };
1782 };
1783 };
1784
1785 etm@1a1f000 {
1786 compatible = "arm,coresight-etm3x", "arm,primecell";
1787 reg = <0x1a1f000 0x1000>;
1788
1789 clocks = <&rpmcc RPM_QDSS_CLK>;
1790 clock-names = "apb_pclk";
1791
1792 cpu = <&CPU3>;
1793
1794 out-ports {
1795 port {
1796 etm3_out: endpoint {
1797 remote-endpoint = <&funnel_in5>;
1798 };
1799 };
1800 };
1801 };
1802 };
1803 };
1804 #include "qcom-apq8064-pins.dtsi"
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