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Merge tag 'topic/designware-baytrail-2017-03-02' of git://anongit.freedesktop.org...
[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / qcom-apq8064.dtsi
1 /dts-v1/;
2
3 #include "skeleton.dtsi"
4 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
5 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
6 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
7 #include <dt-bindings/clock/qcom,rpmcc.h>
8 #include <dt-bindings/soc/qcom,gsbi.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 / {
12 model = "Qualcomm APQ8064";
13 compatible = "qcom,apq8064";
14 interrupt-parent = <&intc>;
15
16 reserved-memory {
17 #address-cells = <1>;
18 #size-cells = <1>;
19 ranges;
20
21 smem_region: smem@80000000 {
22 reg = <0x80000000 0x200000>;
23 no-map;
24 };
25
26 wcnss_mem: wcnss@8f000000 {
27 reg = <0x8f000000 0x700000>;
28 no-map;
29 };
30 };
31
32 cpus {
33 #address-cells = <1>;
34 #size-cells = <0>;
35
36 CPU0: cpu@0 {
37 compatible = "qcom,krait";
38 enable-method = "qcom,kpss-acc-v1";
39 device_type = "cpu";
40 reg = <0>;
41 next-level-cache = <&L2>;
42 qcom,acc = <&acc0>;
43 qcom,saw = <&saw0>;
44 cpu-idle-states = <&CPU_SPC>;
45 };
46
47 CPU1: cpu@1 {
48 compatible = "qcom,krait";
49 enable-method = "qcom,kpss-acc-v1";
50 device_type = "cpu";
51 reg = <1>;
52 next-level-cache = <&L2>;
53 qcom,acc = <&acc1>;
54 qcom,saw = <&saw1>;
55 cpu-idle-states = <&CPU_SPC>;
56 };
57
58 CPU2: cpu@2 {
59 compatible = "qcom,krait";
60 enable-method = "qcom,kpss-acc-v1";
61 device_type = "cpu";
62 reg = <2>;
63 next-level-cache = <&L2>;
64 qcom,acc = <&acc2>;
65 qcom,saw = <&saw2>;
66 cpu-idle-states = <&CPU_SPC>;
67 };
68
69 CPU3: cpu@3 {
70 compatible = "qcom,krait";
71 enable-method = "qcom,kpss-acc-v1";
72 device_type = "cpu";
73 reg = <3>;
74 next-level-cache = <&L2>;
75 qcom,acc = <&acc3>;
76 qcom,saw = <&saw3>;
77 cpu-idle-states = <&CPU_SPC>;
78 };
79
80 L2: l2-cache {
81 compatible = "cache";
82 cache-level = <2>;
83 };
84
85 idle-states {
86 CPU_SPC: spc {
87 compatible = "qcom,idle-state-spc",
88 "arm,idle-state";
89 entry-latency-us = <400>;
90 exit-latency-us = <900>;
91 min-residency-us = <3000>;
92 };
93 };
94 };
95
96 thermal-zones {
97 cpu-thermal0 {
98 polling-delay-passive = <250>;
99 polling-delay = <1000>;
100
101 thermal-sensors = <&gcc 7>;
102 coefficients = <1199 0>;
103
104 trips {
105 cpu_alert0: trip0 {
106 temperature = <75000>;
107 hysteresis = <2000>;
108 type = "passive";
109 };
110 cpu_crit0: trip1 {
111 temperature = <110000>;
112 hysteresis = <2000>;
113 type = "critical";
114 };
115 };
116 };
117
118 cpu-thermal1 {
119 polling-delay-passive = <250>;
120 polling-delay = <1000>;
121
122 thermal-sensors = <&gcc 8>;
123 coefficients = <1132 0>;
124
125 trips {
126 cpu_alert1: trip0 {
127 temperature = <75000>;
128 hysteresis = <2000>;
129 type = "passive";
130 };
131 cpu_crit1: trip1 {
132 temperature = <110000>;
133 hysteresis = <2000>;
134 type = "critical";
135 };
136 };
137 };
138
139 cpu-thermal2 {
140 polling-delay-passive = <250>;
141 polling-delay = <1000>;
142
143 thermal-sensors = <&gcc 9>;
144 coefficients = <1199 0>;
145
146 trips {
147 cpu_alert2: trip0 {
148 temperature = <75000>;
149 hysteresis = <2000>;
150 type = "passive";
151 };
152 cpu_crit2: trip1 {
153 temperature = <110000>;
154 hysteresis = <2000>;
155 type = "critical";
156 };
157 };
158 };
159
160 cpu-thermal3 {
161 polling-delay-passive = <250>;
162 polling-delay = <1000>;
163
164 thermal-sensors = <&gcc 10>;
165 coefficients = <1132 0>;
166
167 trips {
168 cpu_alert3: trip0 {
169 temperature = <75000>;
170 hysteresis = <2000>;
171 type = "passive";
172 };
173 cpu_crit3: trip1 {
174 temperature = <110000>;
175 hysteresis = <2000>;
176 type = "critical";
177 };
178 };
179 };
180 };
181
182 cpu-pmu {
183 compatible = "qcom,krait-pmu";
184 interrupts = <1 10 0x304>;
185 };
186
187 clocks {
188 cxo_board: cxo_board {
189 compatible = "fixed-clock";
190 #clock-cells = <0>;
191 clock-frequency = <19200000>;
192 };
193
194 pxo_board {
195 compatible = "fixed-clock";
196 #clock-cells = <0>;
197 clock-frequency = <27000000>;
198 };
199
200 sleep_clk {
201 compatible = "fixed-clock";
202 #clock-cells = <0>;
203 clock-frequency = <32768>;
204 };
205 };
206
207 sfpb_mutex: hwmutex {
208 compatible = "qcom,sfpb-mutex";
209 syscon = <&sfpb_wrapper_mutex 0x604 0x4>;
210 #hwlock-cells = <1>;
211 };
212
213 smem {
214 compatible = "qcom,smem";
215 memory-region = <&smem_region>;
216
217 hwlocks = <&sfpb_mutex 3>;
218 };
219
220 smd {
221 compatible = "qcom,smd";
222
223 modem@0 {
224 interrupts = <0 37 IRQ_TYPE_EDGE_RISING>;
225
226 qcom,ipc = <&l2cc 8 3>;
227 qcom,smd-edge = <0>;
228
229 status = "disabled";
230 };
231
232 q6@1 {
233 interrupts = <0 90 IRQ_TYPE_EDGE_RISING>;
234
235 qcom,ipc = <&l2cc 8 15>;
236 qcom,smd-edge = <1>;
237
238 status = "disabled";
239 };
240
241 dsps@3 {
242 interrupts = <0 138 IRQ_TYPE_EDGE_RISING>;
243
244 qcom,ipc = <&sps_sic_non_secure 0x4080 0>;
245 qcom,smd-edge = <3>;
246
247 status = "disabled";
248 };
249
250 riva@6 {
251 interrupts = <0 198 IRQ_TYPE_EDGE_RISING>;
252
253 qcom,ipc = <&l2cc 8 25>;
254 qcom,smd-edge = <6>;
255
256 status = "disabled";
257 };
258 };
259
260 smsm {
261 compatible = "qcom,smsm";
262
263 #address-cells = <1>;
264 #size-cells = <0>;
265
266 qcom,ipc-1 = <&l2cc 8 4>;
267 qcom,ipc-2 = <&l2cc 8 14>;
268 qcom,ipc-3 = <&l2cc 8 23>;
269 qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>;
270
271 apps_smsm: apps@0 {
272 reg = <0>;
273 #qcom,smem-state-cells = <1>;
274 };
275
276 modem_smsm: modem@1 {
277 reg = <1>;
278 interrupts = <0 38 IRQ_TYPE_EDGE_RISING>;
279
280 interrupt-controller;
281 #interrupt-cells = <2>;
282 };
283
284 q6_smsm: q6@2 {
285 reg = <2>;
286 interrupts = <0 89 IRQ_TYPE_EDGE_RISING>;
287
288 interrupt-controller;
289 #interrupt-cells = <2>;
290 };
291
292 wcnss_smsm: wcnss@3 {
293 reg = <3>;
294 interrupts = <0 204 IRQ_TYPE_EDGE_RISING>;
295
296 interrupt-controller;
297 #interrupt-cells = <2>;
298 };
299
300 dsps_smsm: dsps@4 {
301 reg = <4>;
302 interrupts = <0 137 IRQ_TYPE_EDGE_RISING>;
303
304 interrupt-controller;
305 #interrupt-cells = <2>;
306 };
307 };
308
309 firmware {
310 scm {
311 compatible = "qcom,scm-apq8064";
312
313 clocks = <&rpmcc RPM_DAYTONA_FABRIC_CLK>;
314 clock-names = "core";
315 };
316 };
317
318 soc: soc {
319 #address-cells = <1>;
320 #size-cells = <1>;
321 ranges;
322 compatible = "simple-bus";
323
324 tlmm_pinmux: pinctrl@800000 {
325 compatible = "qcom,apq8064-pinctrl";
326 reg = <0x800000 0x4000>;
327
328 gpio-controller;
329 #gpio-cells = <2>;
330 interrupt-controller;
331 #interrupt-cells = <2>;
332 interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
333
334 pinctrl-names = "default";
335 pinctrl-0 = <&ps_hold>;
336 };
337
338 sfpb_wrapper_mutex: syscon@1200000 {
339 compatible = "syscon";
340 reg = <0x01200000 0x8000>;
341 };
342
343 intc: interrupt-controller@2000000 {
344 compatible = "qcom,msm-qgic2";
345 interrupt-controller;
346 #interrupt-cells = <3>;
347 reg = <0x02000000 0x1000>,
348 <0x02002000 0x1000>;
349 };
350
351 timer@200a000 {
352 compatible = "qcom,kpss-timer",
353 "qcom,kpss-wdt-apq8064", "qcom,msm-timer";
354 interrupts = <1 1 0x301>,
355 <1 2 0x301>,
356 <1 3 0x301>;
357 reg = <0x0200a000 0x100>;
358 clock-frequency = <27000000>,
359 <32768>;
360 cpu-offset = <0x80000>;
361 };
362
363 acc0: clock-controller@2088000 {
364 compatible = "qcom,kpss-acc-v1";
365 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
366 };
367
368 acc1: clock-controller@2098000 {
369 compatible = "qcom,kpss-acc-v1";
370 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
371 };
372
373 acc2: clock-controller@20a8000 {
374 compatible = "qcom,kpss-acc-v1";
375 reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
376 };
377
378 acc3: clock-controller@20b8000 {
379 compatible = "qcom,kpss-acc-v1";
380 reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
381 };
382
383 saw0: power-controller@2089000 {
384 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
385 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
386 regulator;
387 };
388
389 saw1: power-controller@2099000 {
390 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
391 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
392 regulator;
393 };
394
395 saw2: power-controller@20a9000 {
396 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
397 reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
398 regulator;
399 };
400
401 saw3: power-controller@20b9000 {
402 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
403 reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
404 regulator;
405 };
406
407 sps_sic_non_secure: sps-sic-non-secure@12100000 {
408 compatible = "syscon";
409 reg = <0x12100000 0x10000>;
410 };
411
412 gsbi1: gsbi@12440000 {
413 status = "disabled";
414 compatible = "qcom,gsbi-v1.0.0";
415 cell-index = <1>;
416 reg = <0x12440000 0x100>;
417 clocks = <&gcc GSBI1_H_CLK>;
418 clock-names = "iface";
419 #address-cells = <1>;
420 #size-cells = <1>;
421 ranges;
422
423 syscon-tcsr = <&tcsr>;
424
425 gsbi1_serial: serial@12450000 {
426 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
427 reg = <0x12450000 0x100>,
428 <0x12400000 0x03>;
429 interrupts = <0 193 0x0>;
430 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
431 clock-names = "core", "iface";
432 status = "disabled";
433 };
434
435 gsbi1_i2c: i2c@12460000 {
436 compatible = "qcom,i2c-qup-v1.1.1";
437 pinctrl-0 = <&i2c1_pins>;
438 pinctrl-1 = <&i2c1_pins_sleep>;
439 pinctrl-names = "default", "sleep";
440 reg = <0x12460000 0x1000>;
441 interrupts = <0 194 IRQ_TYPE_NONE>;
442 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
443 clock-names = "core", "iface";
444 #address-cells = <1>;
445 #size-cells = <0>;
446 };
447
448 };
449
450 gsbi2: gsbi@12480000 {
451 status = "disabled";
452 compatible = "qcom,gsbi-v1.0.0";
453 cell-index = <2>;
454 reg = <0x12480000 0x100>;
455 clocks = <&gcc GSBI2_H_CLK>;
456 clock-names = "iface";
457 #address-cells = <1>;
458 #size-cells = <1>;
459 ranges;
460
461 syscon-tcsr = <&tcsr>;
462
463 gsbi2_i2c: i2c@124a0000 {
464 compatible = "qcom,i2c-qup-v1.1.1";
465 reg = <0x124a0000 0x1000>;
466 pinctrl-0 = <&i2c2_pins>;
467 pinctrl-1 = <&i2c2_pins_sleep>;
468 pinctrl-names = "default", "sleep";
469 interrupts = <0 196 IRQ_TYPE_NONE>;
470 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
471 clock-names = "core", "iface";
472 #address-cells = <1>;
473 #size-cells = <0>;
474 };
475 };
476
477 gsbi3: gsbi@16200000 {
478 status = "disabled";
479 compatible = "qcom,gsbi-v1.0.0";
480 cell-index = <3>;
481 reg = <0x16200000 0x100>;
482 clocks = <&gcc GSBI3_H_CLK>;
483 clock-names = "iface";
484 #address-cells = <1>;
485 #size-cells = <1>;
486 ranges;
487 gsbi3_i2c: i2c@16280000 {
488 compatible = "qcom,i2c-qup-v1.1.1";
489 pinctrl-0 = <&i2c3_pins>;
490 pinctrl-1 = <&i2c3_pins_sleep>;
491 pinctrl-names = "default", "sleep";
492 reg = <0x16280000 0x1000>;
493 interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
494 clocks = <&gcc GSBI3_QUP_CLK>,
495 <&gcc GSBI3_H_CLK>;
496 clock-names = "core", "iface";
497 #address-cells = <1>;
498 #size-cells = <0>;
499 };
500 };
501
502 gsbi4: gsbi@16300000 {
503 status = "disabled";
504 compatible = "qcom,gsbi-v1.0.0";
505 cell-index = <4>;
506 reg = <0x16300000 0x03>;
507 clocks = <&gcc GSBI4_H_CLK>;
508 clock-names = "iface";
509 #address-cells = <1>;
510 #size-cells = <1>;
511 ranges;
512
513 gsbi4_i2c: i2c@16380000 {
514 compatible = "qcom,i2c-qup-v1.1.1";
515 pinctrl-0 = <&i2c4_pins>;
516 pinctrl-1 = <&i2c4_pins_sleep>;
517 pinctrl-names = "default", "sleep";
518 reg = <0x16380000 0x1000>;
519 interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;
520 clocks = <&gcc GSBI4_QUP_CLK>,
521 <&gcc GSBI4_H_CLK>;
522 clock-names = "core", "iface";
523 };
524 };
525
526 gsbi5: gsbi@1a200000 {
527 status = "disabled";
528 compatible = "qcom,gsbi-v1.0.0";
529 cell-index = <5>;
530 reg = <0x1a200000 0x03>;
531 clocks = <&gcc GSBI5_H_CLK>;
532 clock-names = "iface";
533 #address-cells = <1>;
534 #size-cells = <1>;
535 ranges;
536
537 gsbi5_serial: serial@1a240000 {
538 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
539 reg = <0x1a240000 0x100>,
540 <0x1a200000 0x03>;
541 interrupts = <0 154 0x0>;
542 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
543 clock-names = "core", "iface";
544 status = "disabled";
545 };
546
547 gsbi5_spi: spi@1a280000 {
548 compatible = "qcom,spi-qup-v1.1.1";
549 reg = <0x1a280000 0x1000>;
550 interrupts = <0 155 0>;
551 pinctrl-0 = <&spi5_default>;
552 pinctrl-1 = <&spi5_sleep>;
553 pinctrl-names = "default", "sleep";
554 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
555 clock-names = "core", "iface";
556 status = "disabled";
557 #address-cells = <1>;
558 #size-cells = <0>;
559 };
560 };
561
562 gsbi6: gsbi@16500000 {
563 status = "disabled";
564 compatible = "qcom,gsbi-v1.0.0";
565 cell-index = <6>;
566 reg = <0x16500000 0x03>;
567 clocks = <&gcc GSBI6_H_CLK>;
568 clock-names = "iface";
569 #address-cells = <1>;
570 #size-cells = <1>;
571 ranges;
572
573 gsbi6_serial: serial@16540000 {
574 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
575 reg = <0x16540000 0x100>,
576 <0x16500000 0x03>;
577 interrupts = <0 156 0x0>;
578 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
579 clock-names = "core", "iface";
580 status = "disabled";
581 };
582
583 gsbi6_i2c: i2c@16580000 {
584 compatible = "qcom,i2c-qup-v1.1.1";
585 pinctrl-0 = <&i2c6_pins>;
586 pinctrl-1 = <&i2c6_pins_sleep>;
587 pinctrl-names = "default", "sleep";
588 reg = <0x16580000 0x1000>;
589 interrupts = <GIC_SPI 157 IRQ_TYPE_NONE>;
590 clocks = <&gcc GSBI6_QUP_CLK>,
591 <&gcc GSBI6_H_CLK>;
592 clock-names = "core", "iface";
593 };
594 };
595
596 gsbi7: gsbi@16600000 {
597 status = "disabled";
598 compatible = "qcom,gsbi-v1.0.0";
599 cell-index = <7>;
600 reg = <0x16600000 0x100>;
601 clocks = <&gcc GSBI7_H_CLK>;
602 clock-names = "iface";
603 #address-cells = <1>;
604 #size-cells = <1>;
605 ranges;
606 syscon-tcsr = <&tcsr>;
607
608 gsbi7_serial: serial@16640000 {
609 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
610 reg = <0x16640000 0x1000>,
611 <0x16600000 0x1000>;
612 interrupts = <0 158 0x0>;
613 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
614 clock-names = "core", "iface";
615 status = "disabled";
616 };
617
618 gsbi7_i2c: i2c@16680000 {
619 compatible = "qcom,i2c-qup-v1.1.1";
620 pinctrl-0 = <&i2c7_pins>;
621 pinctrl-1 = <&i2c7_pins_sleep>;
622 pinctrl-names = "default", "sleep";
623 reg = <0x16680000 0x1000>;
624 interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>;
625 clocks = <&gcc GSBI7_QUP_CLK>,
626 <&gcc GSBI7_H_CLK>;
627 clock-names = "core", "iface";
628 status = "disabled";
629 };
630 };
631
632 rng@1a500000 {
633 compatible = "qcom,prng";
634 reg = <0x1a500000 0x200>;
635 clocks = <&gcc PRNG_CLK>;
636 clock-names = "core";
637 };
638
639 ssbi@c00000 {
640 compatible = "qcom,ssbi";
641 reg = <0x00c00000 0x1000>;
642 qcom,controller-type = "pmic-arbiter";
643
644 pm8821: pmic@1 {
645 compatible = "qcom,pm8821";
646 interrupt-parent = <&tlmm_pinmux>;
647 interrupts = <76 IRQ_TYPE_LEVEL_LOW>;
648 #interrupt-cells = <2>;
649 interrupt-controller;
650 #address-cells = <1>;
651 #size-cells = <0>;
652
653 pm8821_mpps: mpps@50 {
654 compatible = "qcom,pm8821-mpp", "qcom,ssbi-mpp";
655 reg = <0x50>;
656 interrupts = <24 IRQ_TYPE_NONE>,
657 <25 IRQ_TYPE_NONE>,
658 <26 IRQ_TYPE_NONE>,
659 <27 IRQ_TYPE_NONE>;
660 gpio-controller;
661 #gpio-cells = <2>;
662 };
663 };
664 };
665
666 qcom,ssbi@500000 {
667 compatible = "qcom,ssbi";
668 reg = <0x00500000 0x1000>;
669 qcom,controller-type = "pmic-arbiter";
670
671 pmicintc: pmic@0 {
672 compatible = "qcom,pm8921";
673 interrupt-parent = <&tlmm_pinmux>;
674 interrupts = <74 8>;
675 #interrupt-cells = <2>;
676 interrupt-controller;
677 #address-cells = <1>;
678 #size-cells = <0>;
679
680 pm8921_gpio: gpio@150 {
681
682 compatible = "qcom,pm8921-gpio",
683 "qcom,ssbi-gpio";
684 reg = <0x150>;
685 interrupts = <192 IRQ_TYPE_NONE>,
686 <193 IRQ_TYPE_NONE>,
687 <194 IRQ_TYPE_NONE>,
688 <195 IRQ_TYPE_NONE>,
689 <196 IRQ_TYPE_NONE>,
690 <197 IRQ_TYPE_NONE>,
691 <198 IRQ_TYPE_NONE>,
692 <199 IRQ_TYPE_NONE>,
693 <200 IRQ_TYPE_NONE>,
694 <201 IRQ_TYPE_NONE>,
695 <202 IRQ_TYPE_NONE>,
696 <203 IRQ_TYPE_NONE>,
697 <204 IRQ_TYPE_NONE>,
698 <205 IRQ_TYPE_NONE>,
699 <206 IRQ_TYPE_NONE>,
700 <207 IRQ_TYPE_NONE>,
701 <208 IRQ_TYPE_NONE>,
702 <209 IRQ_TYPE_NONE>,
703 <210 IRQ_TYPE_NONE>,
704 <211 IRQ_TYPE_NONE>,
705 <212 IRQ_TYPE_NONE>,
706 <213 IRQ_TYPE_NONE>,
707 <214 IRQ_TYPE_NONE>,
708 <215 IRQ_TYPE_NONE>,
709 <216 IRQ_TYPE_NONE>,
710 <217 IRQ_TYPE_NONE>,
711 <218 IRQ_TYPE_NONE>,
712 <219 IRQ_TYPE_NONE>,
713 <220 IRQ_TYPE_NONE>,
714 <221 IRQ_TYPE_NONE>,
715 <222 IRQ_TYPE_NONE>,
716 <223 IRQ_TYPE_NONE>,
717 <224 IRQ_TYPE_NONE>,
718 <225 IRQ_TYPE_NONE>,
719 <226 IRQ_TYPE_NONE>,
720 <227 IRQ_TYPE_NONE>,
721 <228 IRQ_TYPE_NONE>,
722 <229 IRQ_TYPE_NONE>,
723 <230 IRQ_TYPE_NONE>,
724 <231 IRQ_TYPE_NONE>,
725 <232 IRQ_TYPE_NONE>,
726 <233 IRQ_TYPE_NONE>,
727 <234 IRQ_TYPE_NONE>,
728 <235 IRQ_TYPE_NONE>;
729 gpio-controller;
730 #gpio-cells = <2>;
731
732 };
733
734 pm8921_mpps: mpps@50 {
735 compatible = "qcom,pm8921-mpp",
736 "qcom,ssbi-mpp";
737 reg = <0x50>;
738 gpio-controller;
739 #gpio-cells = <2>;
740 interrupts =
741 <128 IRQ_TYPE_NONE>,
742 <129 IRQ_TYPE_NONE>,
743 <130 IRQ_TYPE_NONE>,
744 <131 IRQ_TYPE_NONE>,
745 <132 IRQ_TYPE_NONE>,
746 <133 IRQ_TYPE_NONE>,
747 <134 IRQ_TYPE_NONE>,
748 <135 IRQ_TYPE_NONE>,
749 <136 IRQ_TYPE_NONE>,
750 <137 IRQ_TYPE_NONE>,
751 <138 IRQ_TYPE_NONE>,
752 <139 IRQ_TYPE_NONE>;
753 };
754
755 rtc@11d {
756 compatible = "qcom,pm8921-rtc";
757 interrupt-parent = <&pmicintc>;
758 interrupts = <39 1>;
759 reg = <0x11d>;
760 allow-set-time;
761 };
762
763 pwrkey@1c {
764 compatible = "qcom,pm8921-pwrkey";
765 reg = <0x1c>;
766 interrupt-parent = <&pmicintc>;
767 interrupts = <50 1>, <51 1>;
768 debounce = <15625>;
769 pull-up;
770 };
771 };
772 };
773
774 qfprom: qfprom@700000 {
775 compatible = "qcom,qfprom";
776 reg = <0x00700000 0x1000>;
777 #address-cells = <1>;
778 #size-cells = <1>;
779 ranges;
780 tsens_calib: calib {
781 reg = <0x404 0x10>;
782 };
783 tsens_backup: backup_calib {
784 reg = <0x414 0x10>;
785 };
786 };
787
788 gcc: clock-controller@900000 {
789 compatible = "qcom,gcc-apq8064";
790 reg = <0x00900000 0x4000>;
791 nvmem-cells = <&tsens_calib>, <&tsens_backup>;
792 nvmem-cell-names = "calib", "calib_backup";
793 #clock-cells = <1>;
794 #reset-cells = <1>;
795 #thermal-sensor-cells = <1>;
796 };
797
798 lcc: clock-controller@28000000 {
799 compatible = "qcom,lcc-apq8064";
800 reg = <0x28000000 0x1000>;
801 #clock-cells = <1>;
802 #reset-cells = <1>;
803 };
804
805 mmcc: clock-controller@4000000 {
806 compatible = "qcom,mmcc-apq8064";
807 reg = <0x4000000 0x1000>;
808 #clock-cells = <1>;
809 #reset-cells = <1>;
810 };
811
812 l2cc: clock-controller@2011000 {
813 compatible = "syscon";
814 reg = <0x2011000 0x1000>;
815 };
816
817 rpm@108000 {
818 compatible = "qcom,rpm-apq8064";
819 reg = <0x108000 0x1000>;
820 qcom,ipc = <&l2cc 0x8 2>;
821
822 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
823 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
824 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
825 interrupt-names = "ack", "err", "wakeup";
826
827 rpmcc: clock-controller {
828 compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc";
829 #clock-cells = <1>;
830 };
831
832 regulators {
833 compatible = "qcom,rpm-pm8921-regulators";
834
835 pm8921_s1: s1 {};
836 pm8921_s2: s2 {};
837 pm8921_s3: s3 {};
838 pm8921_s4: s4 {};
839 pm8921_s7: s7 {};
840 pm8921_s8: s8 {};
841
842 pm8921_l1: l1 {};
843 pm8921_l2: l2 {};
844 pm8921_l3: l3 {};
845 pm8921_l4: l4 {};
846 pm8921_l5: l5 {};
847 pm8921_l6: l6 {};
848 pm8921_l7: l7 {};
849 pm8921_l8: l8 {};
850 pm8921_l9: l9 {};
851 pm8921_l10: l10 {};
852 pm8921_l11: l11 {};
853 pm8921_l12: l12 {};
854 pm8921_l14: l14 {};
855 pm8921_l15: l15 {};
856 pm8921_l16: l16 {};
857 pm8921_l17: l17 {};
858 pm8921_l18: l18 {};
859 pm8921_l21: l21 {};
860 pm8921_l22: l22 {};
861 pm8921_l23: l23 {};
862 pm8921_l24: l24 {};
863 pm8921_l25: l25 {};
864 pm8921_l26: l26 {};
865 pm8921_l27: l27 {};
866 pm8921_l28: l28 {};
867 pm8921_l29: l29 {};
868
869 pm8921_lvs1: lvs1 {};
870 pm8921_lvs2: lvs2 {};
871 pm8921_lvs3: lvs3 {};
872 pm8921_lvs4: lvs4 {};
873 pm8921_lvs5: lvs5 {};
874 pm8921_lvs6: lvs6 {};
875 pm8921_lvs7: lvs7 {};
876
877 pm8921_usb_switch: usb-switch {};
878
879 pm8921_hdmi_switch: hdmi-switch {
880 bias-pull-down;
881 };
882
883 pm8921_ncp: ncp {};
884 };
885 };
886
887 usb1_phy: phy@12500000 {
888 compatible = "qcom,usb-otg-ci";
889 reg = <0x12500000 0x400>;
890 interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
891 status = "disabled";
892
893 clocks = <&gcc USB_HS1_XCVR_CLK>,
894 <&gcc USB_HS1_H_CLK>;
895 clock-names = "core", "iface";
896
897 resets = <&gcc USB_HS1_RESET>;
898 reset-names = "link";
899 };
900
901 usb3_phy: phy@12520000 {
902 compatible = "qcom,usb-otg-ci";
903 reg = <0x12520000 0x400>;
904 interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
905 status = "disabled";
906 dr_mode = "host";
907
908 clocks = <&gcc USB_HS3_XCVR_CLK>,
909 <&gcc USB_HS3_H_CLK>;
910 clock-names = "core", "iface";
911
912 resets = <&gcc USB_HS3_RESET>;
913 reset-names = "link";
914 };
915
916 usb4_phy: phy@12530000 {
917 compatible = "qcom,usb-otg-ci";
918 reg = <0x12530000 0x400>;
919 interrupts = <GIC_SPI 215 IRQ_TYPE_NONE>;
920 status = "disabled";
921 dr_mode = "host";
922
923 clocks = <&gcc USB_HS4_XCVR_CLK>,
924 <&gcc USB_HS4_H_CLK>;
925 clock-names = "core", "iface";
926
927 resets = <&gcc USB_HS4_RESET>;
928 reset-names = "link";
929 };
930
931 gadget1: gadget@12500000 {
932 compatible = "qcom,ci-hdrc";
933 reg = <0x12500000 0x400>;
934 status = "disabled";
935 dr_mode = "peripheral";
936 interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
937 usb-phy = <&usb1_phy>;
938 };
939
940 usb1: usb@12500000 {
941 compatible = "qcom,ehci-host";
942 reg = <0x12500000 0x400>;
943 interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
944 status = "disabled";
945 usb-phy = <&usb1_phy>;
946 };
947
948 usb3: usb@12520000 {
949 compatible = "qcom,ehci-host";
950 reg = <0x12520000 0x400>;
951 interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
952 status = "disabled";
953 usb-phy = <&usb3_phy>;
954 };
955
956 usb4: usb@12530000 {
957 compatible = "qcom,ehci-host";
958 reg = <0x12530000 0x400>;
959 interrupts = <GIC_SPI 215 IRQ_TYPE_NONE>;
960 status = "disabled";
961 usb-phy = <&usb4_phy>;
962 };
963
964 sata_phy0: phy@1b400000 {
965 compatible = "qcom,apq8064-sata-phy";
966 status = "disabled";
967 reg = <0x1b400000 0x200>;
968 reg-names = "phy_mem";
969 clocks = <&gcc SATA_PHY_CFG_CLK>;
970 clock-names = "cfg";
971 #phy-cells = <0>;
972 };
973
974 sata0: sata@29000000 {
975 compatible = "qcom,apq8064-ahci", "generic-ahci";
976 status = "disabled";
977 reg = <0x29000000 0x180>;
978 interrupts = <GIC_SPI 209 IRQ_TYPE_NONE>;
979
980 clocks = <&gcc SFAB_SATA_S_H_CLK>,
981 <&gcc SATA_H_CLK>,
982 <&gcc SATA_A_CLK>,
983 <&gcc SATA_RXOOB_CLK>,
984 <&gcc SATA_PMALIVE_CLK>;
985 clock-names = "slave_iface",
986 "iface",
987 "bus",
988 "rxoob",
989 "core_pmalive";
990
991 assigned-clocks = <&gcc SATA_RXOOB_CLK>,
992 <&gcc SATA_PMALIVE_CLK>;
993 assigned-clock-rates = <100000000>, <100000000>;
994
995 phys = <&sata_phy0>;
996 phy-names = "sata-phy";
997 ports-implemented = <0x1>;
998 };
999
1000 /* Temporary fixed regulator */
1001 sdcc1bam:dma@12402000{
1002 compatible = "qcom,bam-v1.3.0";
1003 reg = <0x12402000 0x8000>;
1004 interrupts = <0 98 0>;
1005 clocks = <&gcc SDC1_H_CLK>;
1006 clock-names = "bam_clk";
1007 #dma-cells = <1>;
1008 qcom,ee = <0>;
1009 };
1010
1011 sdcc3bam:dma@12182000{
1012 compatible = "qcom,bam-v1.3.0";
1013 reg = <0x12182000 0x8000>;
1014 interrupts = <0 96 0>;
1015 clocks = <&gcc SDC3_H_CLK>;
1016 clock-names = "bam_clk";
1017 #dma-cells = <1>;
1018 qcom,ee = <0>;
1019 };
1020
1021 sdcc4bam:dma@121c2000{
1022 compatible = "qcom,bam-v1.3.0";
1023 reg = <0x121c2000 0x8000>;
1024 interrupts = <0 95 0>;
1025 clocks = <&gcc SDC4_H_CLK>;
1026 clock-names = "bam_clk";
1027 #dma-cells = <1>;
1028 qcom,ee = <0>;
1029 };
1030
1031 amba {
1032 compatible = "simple-bus";
1033 #address-cells = <1>;
1034 #size-cells = <1>;
1035 ranges;
1036 sdcc1: sdcc@12400000 {
1037 status = "disabled";
1038 compatible = "arm,pl18x", "arm,primecell";
1039 pinctrl-names = "default";
1040 pinctrl-0 = <&sdcc1_pins>;
1041 arm,primecell-periphid = <0x00051180>;
1042 reg = <0x12400000 0x2000>;
1043 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1044 interrupt-names = "cmd_irq";
1045 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
1046 clock-names = "mclk", "apb_pclk";
1047 bus-width = <8>;
1048 max-frequency = <96000000>;
1049 non-removable;
1050 cap-sd-highspeed;
1051 cap-mmc-highspeed;
1052 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
1053 dma-names = "tx", "rx";
1054 };
1055
1056 sdcc3: sdcc@12180000 {
1057 compatible = "arm,pl18x", "arm,primecell";
1058 arm,primecell-periphid = <0x00051180>;
1059 status = "disabled";
1060 reg = <0x12180000 0x2000>;
1061 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1062 interrupt-names = "cmd_irq";
1063 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
1064 clock-names = "mclk", "apb_pclk";
1065 bus-width = <4>;
1066 cap-sd-highspeed;
1067 cap-mmc-highspeed;
1068 max-frequency = <192000000>;
1069 no-1-8-v;
1070 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
1071 dma-names = "tx", "rx";
1072 };
1073
1074 sdcc4: sdcc@121c0000 {
1075 compatible = "arm,pl18x", "arm,primecell";
1076 arm,primecell-periphid = <0x00051180>;
1077 status = "disabled";
1078 reg = <0x121c0000 0x2000>;
1079 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1080 interrupt-names = "cmd_irq";
1081 clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
1082 clock-names = "mclk", "apb_pclk";
1083 bus-width = <4>;
1084 cap-sd-highspeed;
1085 cap-mmc-highspeed;
1086 max-frequency = <48000000>;
1087 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
1088 dma-names = "tx", "rx";
1089 pinctrl-names = "default";
1090 pinctrl-0 = <&sdc4_gpios>;
1091 };
1092 };
1093
1094 tcsr: syscon@1a400000 {
1095 compatible = "qcom,tcsr-apq8064", "syscon";
1096 reg = <0x1a400000 0x100>;
1097 };
1098
1099 gpu: adreno-3xx@4300000 {
1100 compatible = "qcom,adreno-3xx";
1101 reg = <0x04300000 0x20000>;
1102 reg-names = "kgsl_3d0_reg_memory";
1103 interrupts = <GIC_SPI 80 0>;
1104 interrupt-names = "kgsl_3d0_irq";
1105 clock-names =
1106 "core_clk",
1107 "iface_clk",
1108 "mem_clk",
1109 "mem_iface_clk";
1110 clocks =
1111 <&mmcc GFX3D_CLK>,
1112 <&mmcc GFX3D_AHB_CLK>,
1113 <&mmcc GFX3D_AXI_CLK>,
1114 <&mmcc MMSS_IMEM_AHB_CLK>;
1115 qcom,chipid = <0x03020002>;
1116
1117 iommus = <&gfx3d 0
1118 &gfx3d 1
1119 &gfx3d 2
1120 &gfx3d 3
1121 &gfx3d 4
1122 &gfx3d 5
1123 &gfx3d 6
1124 &gfx3d 7
1125 &gfx3d 8
1126 &gfx3d 9
1127 &gfx3d 10
1128 &gfx3d 11
1129 &gfx3d 12
1130 &gfx3d 13
1131 &gfx3d 14
1132 &gfx3d 15
1133 &gfx3d 16
1134 &gfx3d 17
1135 &gfx3d 18
1136 &gfx3d 19
1137 &gfx3d 20
1138 &gfx3d 21
1139 &gfx3d 22
1140 &gfx3d 23
1141 &gfx3d 24
1142 &gfx3d 25
1143 &gfx3d 26
1144 &gfx3d 27
1145 &gfx3d 28
1146 &gfx3d 29
1147 &gfx3d 30
1148 &gfx3d 31
1149 &gfx3d1 0
1150 &gfx3d1 1
1151 &gfx3d1 2
1152 &gfx3d1 3
1153 &gfx3d1 4
1154 &gfx3d1 5
1155 &gfx3d1 6
1156 &gfx3d1 7
1157 &gfx3d1 8
1158 &gfx3d1 9
1159 &gfx3d1 10
1160 &gfx3d1 11
1161 &gfx3d1 12
1162 &gfx3d1 13
1163 &gfx3d1 14
1164 &gfx3d1 15
1165 &gfx3d1 16
1166 &gfx3d1 17
1167 &gfx3d1 18
1168 &gfx3d1 19
1169 &gfx3d1 20
1170 &gfx3d1 21
1171 &gfx3d1 22
1172 &gfx3d1 23
1173 &gfx3d1 24
1174 &gfx3d1 25
1175 &gfx3d1 26
1176 &gfx3d1 27
1177 &gfx3d1 28
1178 &gfx3d1 29
1179 &gfx3d1 30
1180 &gfx3d1 31>;
1181
1182 qcom,gpu-pwrlevels {
1183 compatible = "qcom,gpu-pwrlevels";
1184 qcom,gpu-pwrlevel@0 {
1185 qcom,gpu-freq = <450000000>;
1186 };
1187 qcom,gpu-pwrlevel@1 {
1188 qcom,gpu-freq = <27000000>;
1189 };
1190 };
1191 };
1192
1193 mmss_sfpb: syscon@5700000 {
1194 compatible = "syscon";
1195 reg = <0x5700000 0x70>;
1196 };
1197
1198 dsi0: mdss_dsi@4700000 {
1199 compatible = "qcom,mdss-dsi-ctrl";
1200 label = "MDSS DSI CTRL->0";
1201 #address-cells = <1>;
1202 #size-cells = <0>;
1203 interrupts = <GIC_SPI 82 0>;
1204 reg = <0x04700000 0x200>;
1205 reg-names = "dsi_ctrl";
1206
1207 clocks = <&mmcc DSI_M_AHB_CLK>,
1208 <&mmcc DSI_S_AHB_CLK>,
1209 <&mmcc AMP_AHB_CLK>,
1210 <&mmcc DSI_CLK>,
1211 <&mmcc DSI1_BYTE_CLK>,
1212 <&mmcc DSI_PIXEL_CLK>,
1213 <&mmcc DSI1_ESC_CLK>;
1214 clock-names = "iface_clk", "bus_clk", "core_mmss_clk",
1215 "src_clk", "byte_clk", "pixel_clk",
1216 "core_clk";
1217
1218 assigned-clocks = <&mmcc DSI1_BYTE_SRC>,
1219 <&mmcc DSI1_ESC_SRC>,
1220 <&mmcc DSI_SRC>,
1221 <&mmcc DSI_PIXEL_SRC>;
1222 assigned-clock-parents = <&dsi0_phy 0>,
1223 <&dsi0_phy 0>,
1224 <&dsi0_phy 1>,
1225 <&dsi0_phy 1>;
1226 syscon-sfpb = <&mmss_sfpb>;
1227 phys = <&dsi0_phy>;
1228 ports {
1229 #address-cells = <1>;
1230 #size-cells = <0>;
1231
1232 port@0 {
1233 reg = <0>;
1234 dsi0_in: endpoint {
1235 };
1236 };
1237
1238 port@1 {
1239 reg = <1>;
1240 dsi0_out: endpoint {
1241 };
1242 };
1243 };
1244 };
1245
1246
1247 dsi0_phy: dsi-phy@4700200 {
1248 compatible = "qcom,dsi-phy-28nm-8960";
1249 #clock-cells = <1>;
1250
1251 reg = <0x04700200 0x100>,
1252 <0x04700300 0x200>,
1253 <0x04700500 0x5c>;
1254 reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator";
1255 clock-names = "iface_clk";
1256 clocks = <&mmcc DSI_M_AHB_CLK>;
1257 };
1258
1259
1260 mdp_port0: iommu@7500000 {
1261 compatible = "qcom,apq8064-iommu";
1262 #iommu-cells = <1>;
1263 clock-names =
1264 "smmu_pclk",
1265 "iommu_clk";
1266 clocks =
1267 <&mmcc SMMU_AHB_CLK>,
1268 <&mmcc MDP_AXI_CLK>;
1269 reg = <0x07500000 0x100000>;
1270 interrupts =
1271 <GIC_SPI 63 0>,
1272 <GIC_SPI 64 0>;
1273 qcom,ncb = <2>;
1274 };
1275
1276 mdp_port1: iommu@7600000 {
1277 compatible = "qcom,apq8064-iommu";
1278 #iommu-cells = <1>;
1279 clock-names =
1280 "smmu_pclk",
1281 "iommu_clk";
1282 clocks =
1283 <&mmcc SMMU_AHB_CLK>,
1284 <&mmcc MDP_AXI_CLK>;
1285 reg = <0x07600000 0x100000>;
1286 interrupts =
1287 <GIC_SPI 61 0>,
1288 <GIC_SPI 62 0>;
1289 qcom,ncb = <2>;
1290 };
1291
1292 gfx3d: iommu@7c00000 {
1293 compatible = "qcom,apq8064-iommu";
1294 #iommu-cells = <1>;
1295 clock-names =
1296 "smmu_pclk",
1297 "iommu_clk";
1298 clocks =
1299 <&mmcc SMMU_AHB_CLK>,
1300 <&mmcc GFX3D_AXI_CLK>;
1301 reg = <0x07c00000 0x100000>;
1302 interrupts =
1303 <GIC_SPI 69 0>,
1304 <GIC_SPI 70 0>;
1305 qcom,ncb = <3>;
1306 };
1307
1308 gfx3d1: iommu@7d00000 {
1309 compatible = "qcom,apq8064-iommu";
1310 #iommu-cells = <1>;
1311 clock-names =
1312 "smmu_pclk",
1313 "iommu_clk";
1314 clocks =
1315 <&mmcc SMMU_AHB_CLK>,
1316 <&mmcc GFX3D_AXI_CLK>;
1317 reg = <0x07d00000 0x100000>;
1318 interrupts =
1319 <GIC_SPI 210 0>,
1320 <GIC_SPI 211 0>;
1321 qcom,ncb = <3>;
1322 };
1323
1324 pcie: pci@1b500000 {
1325 compatible = "qcom,pcie-apq8064", "snps,dw-pcie";
1326 reg = <0x1b500000 0x1000
1327 0x1b502000 0x80
1328 0x1b600000 0x100
1329 0x0ff00000 0x100000>;
1330 reg-names = "dbi", "elbi", "parf", "config";
1331 device_type = "pci";
1332 linux,pci-domain = <0>;
1333 bus-range = <0x00 0xff>;
1334 num-lanes = <1>;
1335 #address-cells = <3>;
1336 #size-cells = <2>;
1337 ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* I/O */
1338 0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */
1339 interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
1340 interrupt-names = "msi";
1341 #interrupt-cells = <1>;
1342 interrupt-map-mask = <0 0 0 0x7>;
1343 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1344 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1345 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1346 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1347 clocks = <&gcc PCIE_A_CLK>,
1348 <&gcc PCIE_H_CLK>,
1349 <&gcc PCIE_PHY_REF_CLK>;
1350 clock-names = "core", "iface", "phy";
1351 resets = <&gcc PCIE_ACLK_RESET>,
1352 <&gcc PCIE_HCLK_RESET>,
1353 <&gcc PCIE_POR_RESET>,
1354 <&gcc PCIE_PCI_RESET>,
1355 <&gcc PCIE_PHY_RESET>;
1356 reset-names = "axi", "ahb", "por", "pci", "phy";
1357 status = "disabled";
1358 };
1359
1360 hdmi: hdmi-tx@4a00000 {
1361 compatible = "qcom,hdmi-tx-8960";
1362 pinctrl-names = "default";
1363 pinctrl-0 = <&hdmi_pinctrl>;
1364 reg = <0x04a00000 0x2f0>;
1365 reg-names = "core_physical";
1366 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1367 clocks = <&mmcc HDMI_APP_CLK>,
1368 <&mmcc HDMI_M_AHB_CLK>,
1369 <&mmcc HDMI_S_AHB_CLK>;
1370 clock-names = "core_clk",
1371 "master_iface_clk",
1372 "slave_iface_clk";
1373
1374 phys = <&hdmi_phy>;
1375 phy-names = "hdmi-phy";
1376
1377 ports {
1378 #address-cells = <1>;
1379 #size-cells = <0>;
1380
1381 port@0 {
1382 reg = <0>;
1383 hdmi_in: endpoint {
1384 };
1385 };
1386
1387 port@1 {
1388 reg = <1>;
1389 hdmi_out: endpoint {
1390 };
1391 };
1392 };
1393 };
1394
1395 hdmi_phy: hdmi-phy@4a00400 {
1396 compatible = "qcom,hdmi-phy-8960";
1397 reg = <0x4a00400 0x60>,
1398 <0x4a00500 0x100>;
1399 reg-names = "hdmi_phy",
1400 "hdmi_pll";
1401
1402 clocks = <&mmcc HDMI_S_AHB_CLK>;
1403 clock-names = "slave_iface_clk";
1404 };
1405
1406 mdp: mdp@5100000 {
1407 compatible = "qcom,mdp4";
1408 reg = <0x05100000 0xf0000>;
1409 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1410 clocks = <&mmcc MDP_CLK>,
1411 <&mmcc MDP_AHB_CLK>,
1412 <&mmcc MDP_AXI_CLK>,
1413 <&mmcc MDP_LUT_CLK>,
1414 <&mmcc HDMI_TV_CLK>,
1415 <&mmcc MDP_TV_CLK>;
1416 clock-names = "core_clk",
1417 "iface_clk",
1418 "bus_clk",
1419 "lut_clk",
1420 "hdmi_clk",
1421 "tv_clk";
1422
1423 iommus = <&mdp_port0 0
1424 &mdp_port0 2
1425 &mdp_port1 0
1426 &mdp_port1 2>;
1427
1428 ports {
1429 #address-cells = <1>;
1430 #size-cells = <0>;
1431
1432 port@0 {
1433 reg = <0>;
1434 mdp_lvds_out: endpoint {
1435 };
1436 };
1437
1438 port@1 {
1439 reg = <1>;
1440 mdp_dsi1_out: endpoint {
1441 };
1442 };
1443
1444 port@2 {
1445 reg = <2>;
1446 mdp_dsi2_out: endpoint {
1447 };
1448 };
1449
1450 port@3 {
1451 reg = <3>;
1452 mdp_dtv_out: endpoint {
1453 };
1454 };
1455 };
1456 };
1457
1458 riva: riva-pil@3204000 {
1459 compatible = "qcom,riva-pil";
1460
1461 reg = <0x03200800 0x1000>, <0x03202000 0x2000>, <0x03204000 0x100>;
1462 reg-names = "ccu", "dxe", "pmu";
1463
1464 interrupts-extended = <&intc GIC_SPI 199 IRQ_TYPE_EDGE_RISING>,
1465 <&wcnss_smsm 6 IRQ_TYPE_EDGE_RISING>;
1466 interrupt-names = "wdog", "fatal";
1467
1468 memory-region = <&wcnss_mem>;
1469
1470 vddcx-supply = <&pm8921_s3>;
1471 vddmx-supply = <&pm8921_l24>;
1472 vddpx-supply = <&pm8921_s4>;
1473
1474 status = "disabled";
1475
1476 iris {
1477 compatible = "qcom,wcn3660";
1478
1479 clocks = <&cxo_board>;
1480 clock-names = "xo";
1481
1482 vddxo-supply = <&pm8921_l4>;
1483 vddrfa-supply = <&pm8921_s2>;
1484 vddpa-supply = <&pm8921_l10>;
1485 vdddig-supply = <&pm8921_lvs2>;
1486 };
1487
1488 smd-edge {
1489 interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>;
1490
1491 qcom,ipc = <&l2cc 8 25>;
1492 qcom,smd-edge = <6>;
1493
1494 label = "riva";
1495
1496 wcnss {
1497 compatible = "qcom,wcnss";
1498 qcom,smd-channels = "WCNSS_CTRL";
1499
1500 qcom,mmio = <&riva>;
1501
1502 bt {
1503 compatible = "qcom,wcnss-bt";
1504 };
1505
1506 wifi {
1507 compatible = "qcom,wcnss-wlan";
1508
1509 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
1510 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
1511 interrupt-names = "tx", "rx";
1512
1513 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
1514 qcom,smem-state-names = "tx-enable", "tx-rings-empty";
1515 };
1516 };
1517 };
1518 };
1519
1520 etb@1a01000 {
1521 compatible = "coresight-etb10", "arm,primecell";
1522 reg = <0x1a01000 0x1000>;
1523
1524 clocks = <&rpmcc RPM_QDSS_CLK>;
1525 clock-names = "apb_pclk";
1526
1527 port {
1528 etb_in: endpoint {
1529 slave-mode;
1530 remote-endpoint = <&replicator_out0>;
1531 };
1532 };
1533 };
1534
1535 tpiu@1a03000 {
1536 compatible = "arm,coresight-tpiu", "arm,primecell";
1537 reg = <0x1a03000 0x1000>;
1538
1539 clocks = <&rpmcc RPM_QDSS_CLK>;
1540 clock-names = "apb_pclk";
1541
1542 port {
1543 tpiu_in: endpoint {
1544 slave-mode;
1545 remote-endpoint = <&replicator_out1>;
1546 };
1547 };
1548 };
1549
1550 replicator {
1551 compatible = "arm,coresight-replicator";
1552
1553 clocks = <&rpmcc RPM_QDSS_CLK>;
1554 clock-names = "apb_pclk";
1555
1556 ports {
1557 #address-cells = <1>;
1558 #size-cells = <0>;
1559
1560 port@0 {
1561 reg = <0>;
1562 replicator_out0: endpoint {
1563 remote-endpoint = <&etb_in>;
1564 };
1565 };
1566 port@1 {
1567 reg = <1>;
1568 replicator_out1: endpoint {
1569 remote-endpoint = <&tpiu_in>;
1570 };
1571 };
1572 port@2 {
1573 reg = <0>;
1574 replicator_in: endpoint {
1575 slave-mode;
1576 remote-endpoint = <&funnel_out>;
1577 };
1578 };
1579 };
1580 };
1581
1582 funnel@1a04000 {
1583 compatible = "arm,coresight-funnel", "arm,primecell";
1584 reg = <0x1a04000 0x1000>;
1585
1586 clocks = <&rpmcc RPM_QDSS_CLK>;
1587 clock-names = "apb_pclk";
1588
1589 ports {
1590 #address-cells = <1>;
1591 #size-cells = <0>;
1592
1593 /*
1594 * Not described input ports:
1595 * 2 - connected to STM component
1596 * 3 - not-connected
1597 * 6 - not-connected
1598 * 7 - not-connected
1599 */
1600 port@0 {
1601 reg = <0>;
1602 funnel_in0: endpoint {
1603 slave-mode;
1604 remote-endpoint = <&etm0_out>;
1605 };
1606 };
1607 port@1 {
1608 reg = <1>;
1609 funnel_in1: endpoint {
1610 slave-mode;
1611 remote-endpoint = <&etm1_out>;
1612 };
1613 };
1614 port@4 {
1615 reg = <4>;
1616 funnel_in4: endpoint {
1617 slave-mode;
1618 remote-endpoint = <&etm2_out>;
1619 };
1620 };
1621 port@5 {
1622 reg = <5>;
1623 funnel_in5: endpoint {
1624 slave-mode;
1625 remote-endpoint = <&etm3_out>;
1626 };
1627 };
1628 port@8 {
1629 reg = <0>;
1630 funnel_out: endpoint {
1631 remote-endpoint = <&replicator_in>;
1632 };
1633 };
1634 };
1635 };
1636
1637 etm@1a1c000 {
1638 compatible = "arm,coresight-etm3x", "arm,primecell";
1639 reg = <0x1a1c000 0x1000>;
1640
1641 clocks = <&rpmcc RPM_QDSS_CLK>;
1642 clock-names = "apb_pclk";
1643
1644 cpu = <&CPU0>;
1645
1646 port {
1647 etm0_out: endpoint {
1648 remote-endpoint = <&funnel_in0>;
1649 };
1650 };
1651 };
1652
1653 etm@1a1d000 {
1654 compatible = "arm,coresight-etm3x", "arm,primecell";
1655 reg = <0x1a1d000 0x1000>;
1656
1657 clocks = <&rpmcc RPM_QDSS_CLK>;
1658 clock-names = "apb_pclk";
1659
1660 cpu = <&CPU1>;
1661
1662 port {
1663 etm1_out: endpoint {
1664 remote-endpoint = <&funnel_in1>;
1665 };
1666 };
1667 };
1668
1669 etm@1a1e000 {
1670 compatible = "arm,coresight-etm3x", "arm,primecell";
1671 reg = <0x1a1e000 0x1000>;
1672
1673 clocks = <&rpmcc RPM_QDSS_CLK>;
1674 clock-names = "apb_pclk";
1675
1676 cpu = <&CPU2>;
1677
1678 port {
1679 etm2_out: endpoint {
1680 remote-endpoint = <&funnel_in4>;
1681 };
1682 };
1683 };
1684
1685 etm@1a1f000 {
1686 compatible = "arm,coresight-etm3x", "arm,primecell";
1687 reg = <0x1a1f000 0x1000>;
1688
1689 clocks = <&rpmcc RPM_QDSS_CLK>;
1690 clock-names = "apb_pclk";
1691
1692 cpu = <&CPU3>;
1693
1694 port {
1695 etm3_out: endpoint {
1696 remote-endpoint = <&funnel_in5>;
1697 };
1698 };
1699 };
1700 };
1701 };
1702 #include "qcom-apq8064-pins.dtsi"
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