arch/arm/boot/dts/qcom-apq8064.dtsi

   1 /dts-v1/;
   2
   3 #include "skeleton.dtsi"
   4 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
   5 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
   6 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
   7 #include <dt-bindings/clock/qcom,rpmcc.h>
   8 #include <dt-bindings/soc/qcom,gsbi.h>
   9 #include <dt-bindings/interrupt-controller/irq.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 / {
  12         model = "Qualcomm APQ8064";
  13         compatible = "qcom,apq8064";
  14         interrupt-parent = <&intc>;
  15
  16         reserved-memory {
  17                 #address-cells = <1>;
  18                 #size-cells = <1>;
  19                 ranges;
  20
  21                 smem_region: smem@80000000 {
  22                         reg = <0x80000000 0x200000>;
  23                         no-map;
  24                 };
  25
  26                 wcnss_mem: wcnss@8f000000 {
  27                         reg = <0x8f000000 0x700000>;
  28                         no-map;
  29                 };
  30         };
  31
  32         cpus {
  33                 #address-cells = <1>;
  34                 #size-cells = <0>;
  35
  36                 CPU0: cpu@0 {
  37                         compatible = "qcom,krait";
  38                         enable-method = "qcom,kpss-acc-v1";
  39                         device_type = "cpu";
  40                         reg = <0>;
  41                         next-level-cache = <&L2>;
  42                         qcom,acc = <&acc0>;
  43                         qcom,saw = <&saw0>;
  44                         cpu-idle-states = <&CPU_SPC>;
  45                 };
  46
  47                 CPU1: cpu@1 {
  48                         compatible = "qcom,krait";
  49                         enable-method = "qcom,kpss-acc-v1";
  50                         device_type = "cpu";
  51                         reg = <1>;
  52                         next-level-cache = <&L2>;
  53                         qcom,acc = <&acc1>;
  54                         qcom,saw = <&saw1>;
  55                         cpu-idle-states = <&CPU_SPC>;
  56                 };
  57
  58                 CPU2: cpu@2 {
  59                         compatible = "qcom,krait";
  60                         enable-method = "qcom,kpss-acc-v1";
  61                         device_type = "cpu";
  62                         reg = <2>;
  63                         next-level-cache = <&L2>;
  64                         qcom,acc = <&acc2>;
  65                         qcom,saw = <&saw2>;
  66                         cpu-idle-states = <&CPU_SPC>;
  67                 };
  68
  69                 CPU3: cpu@3 {
  70                         compatible = "qcom,krait";
  71                         enable-method = "qcom,kpss-acc-v1";
  72                         device_type = "cpu";
  73                         reg = <3>;
  74                         next-level-cache = <&L2>;
  75                         qcom,acc = <&acc3>;
  76                         qcom,saw = <&saw3>;
  77                         cpu-idle-states = <&CPU_SPC>;
  78                 };
  79
  80                 L2: l2-cache {
  81                         compatible = "cache";
  82                         cache-level = <2>;
  83                 };
  84
  85                 idle-states {
  86                         CPU_SPC: spc {
  87                                 compatible = "qcom,idle-state-spc",
  88                                                 "arm,idle-state";
  89                                 entry-latency-us = <400>;
  90                                 exit-latency-us = <900>;
  91                                 min-residency-us = <3000>;
  92                         };
  93                 };
  94         };
  95
  96         thermal-zones {
  97                 cpu-thermal0 {
  98                         polling-delay-passive = <250>;
  99                         polling-delay = <1000>;
 100
 101                         thermal-sensors = <&gcc 7>;
 102                         coefficients = <1199 0>;
 103
 104                         trips {
 105                                 cpu_alert0: trip0 {
 106                                         temperature = <75000>;
 107                                         hysteresis = <2000>;
 108                                         type = "passive";
 109                                 };
 110                                 cpu_crit0: trip1 {
 111                                         temperature = <110000>;
 112                                         hysteresis = <2000>;
 113                                         type = "critical";
 114                                 };
 115                         };
 116                 };
 117
 118                 cpu-thermal1 {
 119                         polling-delay-passive = <250>;
 120                         polling-delay = <1000>;
 121
 122                         thermal-sensors = <&gcc 8>;
 123                         coefficients = <1132 0>;
 124
 125                         trips {
 126                                 cpu_alert1: trip0 {
 127                                         temperature = <75000>;
 128                                         hysteresis = <2000>;
 129                                         type = "passive";
 130                                 };
 131                                 cpu_crit1: trip1 {
 132                                         temperature = <110000>;
 133                                         hysteresis = <2000>;
 134                                         type = "critical";
 135                                 };
 136                         };
 137                 };
 138
 139                 cpu-thermal2 {
 140                         polling-delay-passive = <250>;
 141                         polling-delay = <1000>;
 142
 143                         thermal-sensors = <&gcc 9>;
 144                         coefficients = <1199 0>;
 145
 146                         trips {
 147                                 cpu_alert2: trip0 {
 148                                         temperature = <75000>;
 149                                         hysteresis = <2000>;
 150                                         type = "passive";
 151                                 };
 152                                 cpu_crit2: trip1 {
 153                                         temperature = <110000>;
 154                                         hysteresis = <2000>;
 155                                         type = "critical";
 156                                 };
 157                         };
 158                 };
 159
 160                 cpu-thermal3 {
 161                         polling-delay-passive = <250>;
 162                         polling-delay = <1000>;
 163
 164                         thermal-sensors = <&gcc 10>;
 165                         coefficients = <1132 0>;
 166
 167                         trips {
 168                                 cpu_alert3: trip0 {
 169                                         temperature = <75000>;
 170                                         hysteresis = <2000>;
 171                                         type = "passive";
 172                                 };
 173                                 cpu_crit3: trip1 {
 174                                         temperature = <110000>;
 175                                         hysteresis = <2000>;
 176                                         type = "critical";
 177                                 };
 178                         };
 179                 };
 180         };
 181
 182         cpu-pmu {
 183                 compatible = "qcom,krait-pmu";
 184                 interrupts = <1 10 0x304>;
 185         };
 186
 187         clocks {
 188                 cxo_board: cxo_board {
 189                         compatible = "fixed-clock";
 190                         #clock-cells = <0>;
 191                         clock-frequency = <19200000>;
 192                 };
 193
 194                 pxo_board {
 195                         compatible = "fixed-clock";
 196                         #clock-cells = <0>;
 197                         clock-frequency = <27000000>;
 198                 };
 199
 200                 sleep_clk: sleep_clk {
 201                         compatible = "fixed-clock";
 202                         #clock-cells = <0>;
 203                         clock-frequency = <32768>;
 204                 };
 205         };
 206
 207         sfpb_mutex: hwmutex {
 208                 compatible = "qcom,sfpb-mutex";
 209                 syscon = <&sfpb_wrapper_mutex 0x604 0x4>;
 210                 #hwlock-cells = <1>;
 211         };
 212
 213         smem {
 214                 compatible = "qcom,smem";
 215                 memory-region = <&smem_region>;
 216
 217                 hwlocks = <&sfpb_mutex 3>;
 218         };
 219
 220         smd {
 221                 compatible = "qcom,smd";
 222
 223                 modem@0 {
 224                         interrupts = <0 37 IRQ_TYPE_EDGE_RISING>;
 225
 226                         qcom,ipc = <&l2cc 8 3>;
 227                         qcom,smd-edge = <0>;
 228
 229                         status = "disabled";
 230                 };
 231
 232                 q6@1 {
 233                         interrupts = <0 90 IRQ_TYPE_EDGE_RISING>;
 234
 235                         qcom,ipc = <&l2cc 8 15>;
 236                         qcom,smd-edge = <1>;
 237
 238                         status = "disabled";
 239                 };
 240
 241                 dsps@3 {
 242                         interrupts = <0 138 IRQ_TYPE_EDGE_RISING>;
 243
 244                         qcom,ipc = <&sps_sic_non_secure 0x4080 0>;
 245                         qcom,smd-edge = <3>;
 246
 247                         status = "disabled";
 248                 };
 249
 250                 riva@6 {
 251                         interrupts = <0 198 IRQ_TYPE_EDGE_RISING>;
 252
 253                         qcom,ipc = <&l2cc 8 25>;
 254                         qcom,smd-edge = <6>;
 255
 256                         status = "disabled";
 257                 };
 258         };
 259
 260         smsm {
 261                 compatible = "qcom,smsm";
 262
 263                 #address-cells = <1>;
 264                 #size-cells = <0>;
 265
 266                 qcom,ipc-1 = <&l2cc 8 4>;
 267                 qcom,ipc-2 = <&l2cc 8 14>;
 268                 qcom,ipc-3 = <&l2cc 8 23>;
 269                 qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>;
 270
 271                 apps_smsm: apps@0 {
 272                         reg = <0>;
 273                         #qcom,smem-state-cells = <1>;
 274                 };
 275
 276                 modem_smsm: modem@1 {
 277                         reg = <1>;
 278                         interrupts = <0 38 IRQ_TYPE_EDGE_RISING>;
 279
 280                         interrupt-controller;
 281                         #interrupt-cells = <2>;
 282                 };
 283
 284                 q6_smsm: q6@2 {
 285                         reg = <2>;
 286                         interrupts = <0 89 IRQ_TYPE_EDGE_RISING>;
 287
 288                         interrupt-controller;
 289                         #interrupt-cells = <2>;
 290                 };
 291
 292                 wcnss_smsm: wcnss@3 {
 293                         reg = <3>;
 294                         interrupts = <0 204 IRQ_TYPE_EDGE_RISING>;
 295
 296                         interrupt-controller;
 297                         #interrupt-cells = <2>;
 298                 };
 299
 300                 dsps_smsm: dsps@4 {
 301                         reg = <4>;
 302                         interrupts = <0 137 IRQ_TYPE_EDGE_RISING>;
 303
 304                         interrupt-controller;
 305                         #interrupt-cells = <2>;
 306                 };
 307         };
 308
 309         firmware {
 310                 scm {
 311                         compatible = "qcom,scm-apq8064";
 312
 313                         clocks = <&rpmcc RPM_DAYTONA_FABRIC_CLK>;
 314                         clock-names = "core";
 315                 };
 316         };
 317
 318         soc: soc {
 319                 #address-cells = <1>;
 320                 #size-cells = <1>;
 321                 ranges;
 322                 compatible = "simple-bus";
 323
 324                 tlmm_pinmux: pinctrl@800000 {
 325                         compatible = "qcom,apq8064-pinctrl";
 326                         reg = <0x800000 0x4000>;
 327
 328                         gpio-controller;
 329                         #gpio-cells = <2>;
 330                         interrupt-controller;
 331                         #interrupt-cells = <2>;
 332                         interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
 333
 334                         pinctrl-names = "default";
 335                         pinctrl-0 = <&ps_hold>;
 336                 };
 337
 338                 sfpb_wrapper_mutex: syscon@1200000 {
 339                         compatible = "syscon";
 340                         reg = <0x01200000 0x8000>;
 341                 };
 342
 343                 intc: interrupt-controller@2000000 {
 344                         compatible = "qcom,msm-qgic2";
 345                         interrupt-controller;
 346                         #interrupt-cells = <3>;
 347                         reg = <0x02000000 0x1000>,
 348                               <0x02002000 0x1000>;
 349                 };
 350
 351                 timer@200a000 {
 352                         compatible = "qcom,kpss-timer",
 353                                      "qcom,kpss-wdt-apq8064", "qcom,msm-timer";
 354                         interrupts = <1 1 0x301>,
 355                                      <1 2 0x301>,
 356                                      <1 3 0x301>;
 357                         reg = <0x0200a000 0x100>;
 358                         clock-frequency = <27000000>,
 359                                           <32768>;
 360                         cpu-offset = <0x80000>;
 361                 };
 362
 363                 acc0: clock-controller@2088000 {
 364                         compatible = "qcom,kpss-acc-v1";
 365                         reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
 366                 };
 367
 368                 acc1: clock-controller@2098000 {
 369                         compatible = "qcom,kpss-acc-v1";
 370                         reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
 371                 };
 372
 373                 acc2: clock-controller@20a8000 {
 374                         compatible = "qcom,kpss-acc-v1";
 375                         reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
 376                 };
 377
 378                 acc3: clock-controller@20b8000 {
 379                         compatible = "qcom,kpss-acc-v1";
 380                         reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
 381                 };
 382
 383                 saw0: power-controller@2089000 {
 384                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 385                         reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
 386                         regulator;
 387                 };
 388
 389                 saw1: power-controller@2099000 {
 390                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 391                         reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
 392                         regulator;
 393                 };
 394
 395                 saw2: power-controller@20a9000 {
 396                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 397                         reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
 398                         regulator;
 399                 };
 400
 401                 saw3: power-controller@20b9000 {
 402                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 403                         reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
 404                         regulator;
 405                 };
 406
 407                 sps_sic_non_secure: sps-sic-non-secure@12100000 {
 408                         compatible      = "syscon";
 409                         reg             = <0x12100000 0x10000>;
 410                 };
 411
 412                 gsbi1: gsbi@12440000 {
 413                         status = "disabled";
 414                         compatible = "qcom,gsbi-v1.0.0";
 415                         cell-index = <1>;
 416                         reg = <0x12440000 0x100>;
 417                         clocks = <&gcc GSBI1_H_CLK>;
 418                         clock-names = "iface";
 419                         #address-cells = <1>;
 420                         #size-cells = <1>;
 421                         ranges;
 422
 423                         syscon-tcsr = <&tcsr>;
 424
 425                         gsbi1_serial: serial@12450000 {
 426                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 427                                 reg = <0x12450000 0x100>,
 428                                       <0x12400000 0x03>;
 429                                 interrupts = <0 193 0x0>;
 430                                 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
 431                                 clock-names = "core", "iface";
 432                                 status = "disabled";
 433                         };
 434
 435                         gsbi1_i2c: i2c@12460000 {
 436                                 compatible = "qcom,i2c-qup-v1.1.1";
 437                                 pinctrl-0 = <&i2c1_pins>;
 438                                 pinctrl-1 = <&i2c1_pins_sleep>;
 439                                 pinctrl-names = "default", "sleep";
 440                                 reg = <0x12460000 0x1000>;
 441                                 interrupts = <0 194 IRQ_TYPE_NONE>;
 442                                 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
 443                                 clock-names = "core", "iface";
 444                                 #address-cells = <1>;
 445                                 #size-cells = <0>;
 446                         };
 447
 448                 };
 449
 450                 gsbi2: gsbi@12480000 {
 451                         status = "disabled";
 452                         compatible = "qcom,gsbi-v1.0.0";
 453                         cell-index = <2>;
 454                         reg = <0x12480000 0x100>;
 455                         clocks = <&gcc GSBI2_H_CLK>;
 456                         clock-names = "iface";
 457                         #address-cells = <1>;
 458                         #size-cells = <1>;
 459                         ranges;
 460
 461                         syscon-tcsr = <&tcsr>;
 462
 463                         gsbi2_i2c: i2c@124a0000 {
 464                                 compatible = "qcom,i2c-qup-v1.1.1";
 465                                 reg = <0x124a0000 0x1000>;
 466                                 pinctrl-0 = <&i2c2_pins>;
 467                                 pinctrl-1 = <&i2c2_pins_sleep>;
 468                                 pinctrl-names = "default", "sleep";
 469                                 interrupts = <0 196 IRQ_TYPE_NONE>;
 470                                 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
 471                                 clock-names = "core", "iface";
 472                                 #address-cells = <1>;
 473                                 #size-cells = <0>;
 474                         };
 475                 };
 476
 477                 gsbi3: gsbi@16200000 {
 478                         status = "disabled";
 479                         compatible = "qcom,gsbi-v1.0.0";
 480                         cell-index = <3>;
 481                         reg = <0x16200000 0x100>;
 482                         clocks = <&gcc GSBI3_H_CLK>;
 483                         clock-names = "iface";
 484                         #address-cells = <1>;
 485                         #size-cells = <1>;
 486                         ranges;
 487                         gsbi3_i2c: i2c@16280000 {
 488                                 compatible = "qcom,i2c-qup-v1.1.1";
 489                                 pinctrl-0 = <&i2c3_pins>;
 490                                 pinctrl-1 = <&i2c3_pins_sleep>;
 491                                 pinctrl-names = "default", "sleep";
 492                                 reg = <0x16280000 0x1000>;
 493                                 interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
 494                                 clocks = <&gcc GSBI3_QUP_CLK>,
 495                                          <&gcc GSBI3_H_CLK>;
 496                                 clock-names = "core", "iface";
 497                                 #address-cells = <1>;
 498                                 #size-cells = <0>;
 499                         };
 500                 };
 501
 502                 gsbi4: gsbi@16300000 {
 503                         status = "disabled";
 504                         compatible = "qcom,gsbi-v1.0.0";
 505                         cell-index = <4>;
 506                         reg = <0x16300000 0x03>;
 507                         clocks = <&gcc GSBI4_H_CLK>;
 508                         clock-names = "iface";
 509                         #address-cells = <1>;
 510                         #size-cells = <1>;
 511                         ranges;
 512
 513                         gsbi4_i2c: i2c@16380000 {
 514                                 compatible = "qcom,i2c-qup-v1.1.1";
 515                                 pinctrl-0 = <&i2c4_pins>;
 516                                 pinctrl-1 = <&i2c4_pins_sleep>;
 517                                 pinctrl-names = "default", "sleep";
 518                                 reg = <0x16380000 0x1000>;
 519                                 interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;
 520                                 clocks = <&gcc GSBI4_QUP_CLK>,
 521                                          <&gcc GSBI4_H_CLK>;
 522                                 clock-names = "core", "iface";
 523                         };
 524                 };
 525
 526                 gsbi5: gsbi@1a200000 {
 527                         status = "disabled";
 528                         compatible = "qcom,gsbi-v1.0.0";
 529                         cell-index = <5>;
 530                         reg = <0x1a200000 0x03>;
 531                         clocks = <&gcc GSBI5_H_CLK>;
 532                         clock-names = "iface";
 533                         #address-cells = <1>;
 534                         #size-cells = <1>;
 535                         ranges;
 536
 537                         gsbi5_serial: serial@1a240000 {
 538                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 539                                 reg = <0x1a240000 0x100>,
 540                                       <0x1a200000 0x03>;
 541                                 interrupts = <0 154 0x0>;
 542                                 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
 543                                 clock-names = "core", "iface";
 544                                 status = "disabled";
 545                         };
 546
 547                         gsbi5_spi: spi@1a280000 {
 548                                 compatible = "qcom,spi-qup-v1.1.1";
 549                                 reg = <0x1a280000 0x1000>;
 550                                 interrupts = <0 155 0>;
 551                                 pinctrl-0 = <&spi5_default>;
 552                                 pinctrl-1 = <&spi5_sleep>;
 553                                 pinctrl-names = "default", "sleep";
 554                                 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
 555                                 clock-names = "core", "iface";
 556                                 status = "disabled";
 557                                 #address-cells = <1>;
 558                                 #size-cells = <0>;
 559                         };
 560                 };
 561
 562                 gsbi6: gsbi@16500000 {
 563                         status = "disabled";
 564                         compatible = "qcom,gsbi-v1.0.0";
 565                         cell-index = <6>;
 566                         reg = <0x16500000 0x03>;
 567                         clocks = <&gcc GSBI6_H_CLK>;
 568                         clock-names = "iface";
 569                         #address-cells = <1>;
 570                         #size-cells = <1>;
 571                         ranges;
 572
 573                         gsbi6_serial: serial@16540000 {
 574                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 575                                 reg = <0x16540000 0x100>,
 576                                       <0x16500000 0x03>;
 577                                 interrupts = <0 156 0x0>;
 578                                 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
 579                                 clock-names = "core", "iface";
 580                                 status = "disabled";
 581                         };
 582
 583                         gsbi6_i2c: i2c@16580000 {
 584                                 compatible = "qcom,i2c-qup-v1.1.1";
 585                                 pinctrl-0 = <&i2c6_pins>;
 586                                 pinctrl-1 = <&i2c6_pins_sleep>;
 587                                 pinctrl-names = "default", "sleep";
 588                                 reg = <0x16580000 0x1000>;
 589                                 interrupts = <GIC_SPI 157 IRQ_TYPE_NONE>;
 590                                 clocks = <&gcc GSBI6_QUP_CLK>,
 591                                          <&gcc GSBI6_H_CLK>;
 592                                 clock-names = "core", "iface";
 593                         };
 594                 };
 595
 596                 gsbi7: gsbi@16600000 {
 597                         status = "disabled";
 598                         compatible = "qcom,gsbi-v1.0.0";
 599                         cell-index = <7>;
 600                         reg = <0x16600000 0x100>;
 601                         clocks = <&gcc GSBI7_H_CLK>;
 602                         clock-names = "iface";
 603                         #address-cells = <1>;
 604                         #size-cells = <1>;
 605                         ranges;
 606                         syscon-tcsr = <&tcsr>;
 607
 608                         gsbi7_serial: serial@16640000 {
 609                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 610                                 reg = <0x16640000 0x1000>,
 611                                       <0x16600000 0x1000>;
 612                                 interrupts = <0 158 0x0>;
 613                                 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
 614                                 clock-names = "core", "iface";
 615                                 status = "disabled";
 616                         };
 617
 618                         gsbi7_i2c: i2c@16680000 {
 619                                 compatible = "qcom,i2c-qup-v1.1.1";
 620                                 pinctrl-0 = <&i2c7_pins>;
 621                                 pinctrl-1 = <&i2c7_pins_sleep>;
 622                                 pinctrl-names = "default", "sleep";
 623                                 reg = <0x16680000 0x1000>;
 624                                 interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>;
 625                                 clocks = <&gcc GSBI7_QUP_CLK>,
 626                                          <&gcc GSBI7_H_CLK>;
 627                                 clock-names = "core", "iface";
 628                                 status = "disabled";
 629                         };
 630                 };
 631
 632                 rng@1a500000 {
 633                         compatible = "qcom,prng";
 634                         reg = <0x1a500000 0x200>;
 635                         clocks = <&gcc PRNG_CLK>;
 636                         clock-names = "core";
 637                 };
 638
 639                 ssbi@c00000 {
 640                         compatible = "qcom,ssbi";
 641                         reg = <0x00c00000 0x1000>;
 642                         qcom,controller-type = "pmic-arbiter";
 643
 644                         pm8821: pmic@1 {
 645                                 compatible = "qcom,pm8821";
 646                                 interrupt-parent = <&tlmm_pinmux>;
 647                                 interrupts = <76 IRQ_TYPE_LEVEL_LOW>;
 648                                 #interrupt-cells = <2>;
 649                                 interrupt-controller;
 650                                 #address-cells = <1>;
 651                                 #size-cells = <0>;
 652
 653                                 pm8821_mpps: mpps@50 {
 654                                         compatible = "qcom,pm8821-mpp", "qcom,ssbi-mpp";
 655                                         reg = <0x50>;
 656                                         interrupts = <24 IRQ_TYPE_NONE>,
 657                                                      <25 IRQ_TYPE_NONE>,
 658                                                      <26 IRQ_TYPE_NONE>,
 659                                                      <27 IRQ_TYPE_NONE>;
 660                                         gpio-controller;
 661                                         #gpio-cells = <2>;
 662                                 };
 663                         };
 664                 };
 665
 666                 qcom,ssbi@500000 {
 667                         compatible = "qcom,ssbi";
 668                         reg = <0x00500000 0x1000>;
 669                         qcom,controller-type = "pmic-arbiter";
 670
 671                         pmicintc: pmic@0 {
 672                                 compatible = "qcom,pm8921";
 673                                 interrupt-parent = <&tlmm_pinmux>;
 674                                 interrupts = <74 8>;
 675                                 #interrupt-cells = <2>;
 676                                 interrupt-controller;
 677                                 #address-cells = <1>;
 678                                 #size-cells = <0>;
 679
 680                                 pm8921_gpio: gpio@150 {
 681
 682                                         compatible = "qcom,pm8921-gpio",
 683                                                      "qcom,ssbi-gpio";
 684                                         reg = <0x150>;
 685                                         interrupts = <192 IRQ_TYPE_NONE>,
 686                                                      <193 IRQ_TYPE_NONE>,
 687                                                      <194 IRQ_TYPE_NONE>,
 688                                                      <195 IRQ_TYPE_NONE>,
 689                                                      <196 IRQ_TYPE_NONE>,
 690                                                      <197 IRQ_TYPE_NONE>,
 691                                                      <198 IRQ_TYPE_NONE>,
 692                                                      <199 IRQ_TYPE_NONE>,
 693                                                      <200 IRQ_TYPE_NONE>,
 694                                                      <201 IRQ_TYPE_NONE>,
 695                                                      <202 IRQ_TYPE_NONE>,
 696                                                      <203 IRQ_TYPE_NONE>,
 697                                                      <204 IRQ_TYPE_NONE>,
 698                                                      <205 IRQ_TYPE_NONE>,
 699                                                      <206 IRQ_TYPE_NONE>,
 700                                                      <207 IRQ_TYPE_NONE>,
 701                                                      <208 IRQ_TYPE_NONE>,
 702                                                      <209 IRQ_TYPE_NONE>,
 703                                                      <210 IRQ_TYPE_NONE>,
 704                                                      <211 IRQ_TYPE_NONE>,
 705                                                      <212 IRQ_TYPE_NONE>,
 706                                                      <213 IRQ_TYPE_NONE>,
 707                                                      <214 IRQ_TYPE_NONE>,
 708                                                      <215 IRQ_TYPE_NONE>,
 709                                                      <216 IRQ_TYPE_NONE>,
 710                                                      <217 IRQ_TYPE_NONE>,
 711                                                      <218 IRQ_TYPE_NONE>,
 712                                                      <219 IRQ_TYPE_NONE>,
 713                                                      <220 IRQ_TYPE_NONE>,
 714                                                      <221 IRQ_TYPE_NONE>,
 715                                                      <222 IRQ_TYPE_NONE>,
 716                                                      <223 IRQ_TYPE_NONE>,
 717                                                      <224 IRQ_TYPE_NONE>,
 718                                                      <225 IRQ_TYPE_NONE>,
 719                                                      <226 IRQ_TYPE_NONE>,
 720                                                      <227 IRQ_TYPE_NONE>,
 721                                                      <228 IRQ_TYPE_NONE>,
 722                                                      <229 IRQ_TYPE_NONE>,
 723                                                      <230 IRQ_TYPE_NONE>,
 724                                                      <231 IRQ_TYPE_NONE>,
 725                                                      <232 IRQ_TYPE_NONE>,
 726                                                      <233 IRQ_TYPE_NONE>,
 727                                                      <234 IRQ_TYPE_NONE>,
 728                                                      <235 IRQ_TYPE_NONE>;
 729                                         gpio-controller;
 730                                         #gpio-cells = <2>;
 731
 732                                 };
 733
 734                                 pm8921_mpps: mpps@50 {
 735                                         compatible = "qcom,pm8921-mpp",
 736                                                      "qcom,ssbi-mpp";
 737                                         reg = <0x50>;
 738                                         gpio-controller;
 739                                         #gpio-cells = <2>;
 740                                         interrupts =
 741                                         <128 IRQ_TYPE_NONE>,
 742                                         <129 IRQ_TYPE_NONE>,
 743                                         <130 IRQ_TYPE_NONE>,
 744                                         <131 IRQ_TYPE_NONE>,
 745                                         <132 IRQ_TYPE_NONE>,
 746                                         <133 IRQ_TYPE_NONE>,
 747                                         <134 IRQ_TYPE_NONE>,
 748                                         <135 IRQ_TYPE_NONE>,
 749                                         <136 IRQ_TYPE_NONE>,
 750                                         <137 IRQ_TYPE_NONE>,
 751                                         <138 IRQ_TYPE_NONE>,
 752                                         <139 IRQ_TYPE_NONE>;
 753                                 };
 754
 755                                 rtc@11d {
 756                                         compatible = "qcom,pm8921-rtc";
 757                                         interrupt-parent = <&pmicintc>;
 758                                         interrupts = <39 1>;
 759                                         reg = <0x11d>;
 760                                         allow-set-time;
 761                                 };
 762
 763                                 pwrkey@1c {
 764                                         compatible = "qcom,pm8921-pwrkey";
 765                                         reg = <0x1c>;
 766                                         interrupt-parent = <&pmicintc>;
 767                                         interrupts = <50 1>, <51 1>;
 768                                         debounce = <15625>;
 769                                         pull-up;
 770                                 };
 771                         };
 772                 };
 773
 774                 qfprom: qfprom@700000 {
 775                         compatible      = "qcom,qfprom";
 776                         reg             = <0x00700000 0x1000>;
 777                         #address-cells  = <1>;
 778                         #size-cells     = <1>;
 779                         ranges;
 780                         tsens_calib: calib {
 781                                 reg = <0x404 0x10>;
 782                         };
 783                         tsens_backup: backup_calib {
 784                                 reg = <0x414 0x10>;
 785                         };
 786                 };
 787
 788                 gcc: clock-controller@900000 {
 789                         compatible = "qcom,gcc-apq8064";
 790                         reg = <0x00900000 0x4000>;
 791                         nvmem-cells = <&tsens_calib>, <&tsens_backup>;
 792                         nvmem-cell-names = "calib", "calib_backup";
 793                         #clock-cells = <1>;
 794                         #reset-cells = <1>;
 795                         #thermal-sensor-cells = <1>;
 796                 };
 797
 798                 lcc: clock-controller@28000000 {
 799                         compatible = "qcom,lcc-apq8064";
 800                         reg = <0x28000000 0x1000>;
 801                         #clock-cells = <1>;
 802                         #reset-cells = <1>;
 803                 };
 804
 805                 mmcc: clock-controller@4000000 {
 806                         compatible = "qcom,mmcc-apq8064";
 807                         reg = <0x4000000 0x1000>;
 808                         #clock-cells = <1>;
 809                         #reset-cells = <1>;
 810                 };
 811
 812                 l2cc: clock-controller@2011000 {
 813                         compatible      = "syscon";
 814                         reg             = <0x2011000 0x1000>;
 815                 };
 816
 817                 rpm@108000 {
 818                         compatible      = "qcom,rpm-apq8064";
 819                         reg             = <0x108000 0x1000>;
 820                         qcom,ipc        = <&l2cc 0x8 2>;
 821
 822                         interrupts      = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
 823                                           <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
 824                                           <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
 825                         interrupt-names = "ack", "err", "wakeup";
 826
 827                         rpmcc: clock-controller {
 828                                 compatible      = "qcom,rpmcc-apq8064", "qcom,rpmcc";
 829                                 #clock-cells = <1>;
 830                         };
 831
 832                         regulators {
 833                                 compatible = "qcom,rpm-pm8921-regulators";
 834
 835                                 pm8921_s1: s1 {};
 836                                 pm8921_s2: s2 {};
 837                                 pm8921_s3: s3 {};
 838                                 pm8921_s4: s4 {};
 839                                 pm8921_s7: s7 {};
 840                                 pm8921_s8: s8 {};
 841
 842                                 pm8921_l1: l1 {};
 843                                 pm8921_l2: l2 {};
 844                                 pm8921_l3: l3 {};
 845                                 pm8921_l4: l4 {};
 846                                 pm8921_l5: l5 {};
 847                                 pm8921_l6: l6 {};
 848                                 pm8921_l7: l7 {};
 849                                 pm8921_l8: l8 {};
 850                                 pm8921_l9: l9 {};
 851                                 pm8921_l10: l10 {};
 852                                 pm8921_l11: l11 {};
 853                                 pm8921_l12: l12 {};
 854                                 pm8921_l14: l14 {};
 855                                 pm8921_l15: l15 {};
 856                                 pm8921_l16: l16 {};
 857                                 pm8921_l17: l17 {};
 858                                 pm8921_l18: l18 {};
 859                                 pm8921_l21: l21 {};
 860                                 pm8921_l22: l22 {};
 861                                 pm8921_l23: l23 {};
 862                                 pm8921_l24: l24 {};
 863                                 pm8921_l25: l25 {};
 864                                 pm8921_l26: l26 {};
 865                                 pm8921_l27: l27 {};
 866                                 pm8921_l28: l28 {};
 867                                 pm8921_l29: l29 {};
 868
 869                                 pm8921_lvs1: lvs1 {};
 870                                 pm8921_lvs2: lvs2 {};
 871                                 pm8921_lvs3: lvs3 {};
 872                                 pm8921_lvs4: lvs4 {};
 873                                 pm8921_lvs5: lvs5 {};
 874                                 pm8921_lvs6: lvs6 {};
 875                                 pm8921_lvs7: lvs7 {};
 876
 877                                 pm8921_usb_switch: usb-switch {};
 878
 879                                 pm8921_hdmi_switch: hdmi-switch {
 880                                         bias-pull-down;
 881                                 };
 882
 883                                 pm8921_ncp: ncp {};
 884                         };
 885                 };
 886
 887                 usb1: usb@12500000 {
 888                         compatible = "qcom,ci-hdrc";
 889                         reg = <0x12500000 0x200>,
 890                               <0x12500200 0x200>;
 891                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 892                         clocks = <&gcc USB_HS1_XCVR_CLK>, <&gcc USB_HS1_H_CLK>;
 893                         clock-names = "core", "iface";
 894                         assigned-clocks = <&gcc USB_HS1_XCVR_CLK>;
 895                         assigned-clock-rates = <60000000>;
 896                         resets = <&gcc USB_HS1_RESET>;
 897                         reset-names = "core";
 898                         phy_type = "ulpi";
 899                         ahb-burst-config = <0>;
 900                         phys = <&usb_hs1_phy>;
 901                         phy-names = "usb-phy";
 902                         status = "disabled";
 903                         #reset-cells = <1>;
 904
 905                         ulpi {
 906                                 usb_hs1_phy: phy {
 907                                         compatible = "qcom,usb-hs-phy-apq8064",
 908                                                      "qcom,usb-hs-phy";
 909                                         #phy-cells = <0>;
 910                                         clocks = <&sleep_clk>, <&cxo_board>;
 911                                         clock-names = "sleep", "ref";
 912                                         resets = <&usb1 0>;
 913                                         reset-names = "por";
 914                                 };
 915                         };
 916                 };
 917
 918                 usb3: usb@12520000 {
 919                         compatible = "qcom,ci-hdrc";
 920                         reg = <0x12520000 0x200>,
 921                               <0x12520200 0x200>;
 922                         interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
 923                         clocks = <&gcc USB_HS3_XCVR_CLK>, <&gcc USB_HS3_H_CLK>;
 924                         clock-names = "core", "iface";
 925                         assigned-clocks = <&gcc USB_HS3_XCVR_CLK>;
 926                         assigned-clock-rates = <60000000>;
 927                         resets = <&gcc USB_HS3_RESET>;
 928                         reset-names = "core";
 929                         phy_type = "ulpi";
 930                         ahb-burst-config = <0>;
 931                         phys = <&usb_hs3_phy>;
 932                         phy-names = "usb-phy";
 933                         status = "disabled";
 934                         #reset-cells = <1>;
 935
 936                         ulpi {
 937                                 usb_hs3_phy: phy {
 938                                         compatible = "qcom,usb-hs-phy-apq8064",
 939                                                      "qcom,usb-hs-phy";
 940                                         #phy-cells = <0>;
 941                                         clocks = <&sleep_clk>, <&cxo_board>;
 942                                         clock-names = "sleep", "ref";
 943                                         resets = <&usb3 0>;
 944                                         reset-names = "por";
 945                                 };
 946                         };
 947                 };
 948
 949                 usb4: usb@12530000 {
 950                         compatible = "qcom,ci-hdrc";
 951                         reg = <0x12530000 0x200>,
 952                               <0x12530200 0x200>;
 953                         interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
 954                         clocks = <&gcc USB_HS4_XCVR_CLK>, <&gcc USB_HS4_H_CLK>;
 955                         clock-names = "core", "iface";
 956                         assigned-clocks = <&gcc USB_HS4_XCVR_CLK>;
 957                         assigned-clock-rates = <60000000>;
 958                         resets = <&gcc USB_HS4_RESET>;
 959                         reset-names = "core";
 960                         phy_type = "ulpi";
 961                         ahb-burst-config = <0>;
 962                         phys = <&usb_hs4_phy>;
 963                         phy-names = "usb-phy";
 964                         status = "disabled";
 965                         #reset-cells = <1>;
 966
 967                         ulpi {
 968                                 usb_hs4_phy: phy {
 969                                         compatible = "qcom,usb-hs-phy-apq8064",
 970                                                      "qcom,usb-hs-phy";
 971                                         #phy-cells = <0>;
 972                                         clocks = <&sleep_clk>, <&cxo_board>;
 973                                         clock-names = "sleep", "ref";
 974                                         resets = <&usb4 0>;
 975                                         reset-names = "por";
 976                                 };
 977                         };
 978                 };
 979
 980                 sata_phy0: phy@1b400000 {
 981                         compatible      = "qcom,apq8064-sata-phy";
 982                         status          = "disabled";
 983                         reg             = <0x1b400000 0x200>;
 984                         reg-names       = "phy_mem";
 985                         clocks          = <&gcc SATA_PHY_CFG_CLK>;
 986                         clock-names     = "cfg";
 987                         #phy-cells      = <0>;
 988                 };
 989
 990                 sata0: sata@29000000 {
 991                         compatible              = "qcom,apq8064-ahci", "generic-ahci";
 992                         status                  = "disabled";
 993                         reg                     = <0x29000000 0x180>;
 994                         interrupts              = <GIC_SPI 209 IRQ_TYPE_NONE>;
 995
 996                         clocks                  = <&gcc SFAB_SATA_S_H_CLK>,
 997                                                 <&gcc SATA_H_CLK>,
 998                                                 <&gcc SATA_A_CLK>,
 999                                                 <&gcc SATA_RXOOB_CLK>,
1000                                                 <&gcc SATA_PMALIVE_CLK>;
1001                         clock-names             = "slave_iface",
1002                                                 "iface",
1003                                                 "bus",
1004                                                 "rxoob",
1005                                                 "core_pmalive";
1006
1007                         assigned-clocks         = <&gcc SATA_RXOOB_CLK>,
1008                                                 <&gcc SATA_PMALIVE_CLK>;
1009                         assigned-clock-rates    = <100000000>, <100000000>;
1010
1011                         phys                    = <&sata_phy0>;
1012                         phy-names               = "sata-phy";
1013                         ports-implemented       = <0x1>;
1014                 };
1015
1016                 /* Temporary fixed regulator */
1017                 sdcc1bam:dma@12402000{
1018                         compatible = "qcom,bam-v1.3.0";
1019                         reg = <0x12402000 0x8000>;
1020                         interrupts = <0 98 0>;
1021                         clocks = <&gcc SDC1_H_CLK>;
1022                         clock-names = "bam_clk";
1023                         #dma-cells = <1>;
1024                         qcom,ee = <0>;
1025                 };
1026
1027                 sdcc3bam:dma@12182000{
1028                         compatible = "qcom,bam-v1.3.0";
1029                         reg = <0x12182000 0x8000>;
1030                         interrupts = <0 96 0>;
1031                         clocks = <&gcc SDC3_H_CLK>;
1032                         clock-names = "bam_clk";
1033                         #dma-cells = <1>;
1034                         qcom,ee = <0>;
1035                 };
1036
1037                 sdcc4bam:dma@121c2000{
1038                         compatible = "qcom,bam-v1.3.0";
1039                         reg = <0x121c2000 0x8000>;
1040                         interrupts = <0 95 0>;
1041                         clocks = <&gcc SDC4_H_CLK>;
1042                         clock-names = "bam_clk";
1043                         #dma-cells = <1>;
1044                         qcom,ee = <0>;
1045                 };
1046
1047                 amba {
1048                         compatible = "simple-bus";
1049                         #address-cells = <1>;
1050                         #size-cells = <1>;
1051                         ranges;
1052                         sdcc1: sdcc@12400000 {
1053                                 status          = "disabled";
1054                                 compatible      = "arm,pl18x", "arm,primecell";
1055                                 pinctrl-names   = "default";
1056                                 pinctrl-0       = <&sdcc1_pins>;
1057                                 arm,primecell-periphid = <0x00051180>;
1058                                 reg             = <0x12400000 0x2000>;
1059                                 interrupts      = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1060                                 interrupt-names = "cmd_irq";
1061                                 clocks          = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
1062                                 clock-names     = "mclk", "apb_pclk";
1063                                 bus-width       = <8>;
1064                                 max-frequency   = <96000000>;
1065                                 non-removable;
1066                                 cap-sd-highspeed;
1067                                 cap-mmc-highspeed;
1068                                 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
1069                                 dma-names = "tx", "rx";
1070                         };
1071
1072                         sdcc3: sdcc@12180000 {
1073                                 compatible      = "arm,pl18x", "arm,primecell";
1074                                 arm,primecell-periphid = <0x00051180>;
1075                                 status          = "disabled";
1076                                 reg             = <0x12180000 0x2000>;
1077                                 interrupts      = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1078                                 interrupt-names = "cmd_irq";
1079                                 clocks          = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
1080                                 clock-names     = "mclk", "apb_pclk";
1081                                 bus-width       = <4>;
1082                                 cap-sd-highspeed;
1083                                 cap-mmc-highspeed;
1084                                 max-frequency   = <192000000>;
1085                                 no-1-8-v;
1086                                 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
1087                                 dma-names = "tx", "rx";
1088                         };
1089
1090                         sdcc4: sdcc@121c0000 {
1091                                 compatible      = "arm,pl18x", "arm,primecell";
1092                                 arm,primecell-periphid = <0x00051180>;
1093                                 status          = "disabled";
1094                                 reg             = <0x121c0000 0x2000>;
1095                                 interrupts      = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1096                                 interrupt-names = "cmd_irq";
1097                                 clocks          = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
1098                                 clock-names     = "mclk", "apb_pclk";
1099                                 bus-width       = <4>;
1100                                 cap-sd-highspeed;
1101                                 cap-mmc-highspeed;
1102                                 max-frequency   = <48000000>;
1103                                 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
1104                                 dma-names = "tx", "rx";
1105                                 pinctrl-names = "default";
1106                                 pinctrl-0 = <&sdc4_gpios>;
1107                         };
1108                 };
1109
1110                 tcsr: syscon@1a400000 {
1111                         compatible = "qcom,tcsr-apq8064", "syscon";
1112                         reg = <0x1a400000 0x100>;
1113                 };
1114
1115                 gpu: adreno-3xx@4300000 {
1116                         compatible = "qcom,adreno-3xx";
1117                         reg = <0x04300000 0x20000>;
1118                         reg-names = "kgsl_3d0_reg_memory";
1119                         interrupts = <GIC_SPI 80 0>;
1120                         interrupt-names = "kgsl_3d0_irq";
1121                         clock-names =
1122                             "core_clk",
1123                             "iface_clk",
1124                             "mem_clk",
1125                             "mem_iface_clk";
1126                         clocks =
1127                             <&mmcc GFX3D_CLK>,
1128                             <&mmcc GFX3D_AHB_CLK>,
1129                             <&mmcc GFX3D_AXI_CLK>,
1130                             <&mmcc MMSS_IMEM_AHB_CLK>;
1131                         qcom,chipid = <0x03020002>;
1132
1133                         iommus = <&gfx3d 0
1134                                   &gfx3d 1
1135                                   &gfx3d 2
1136                                   &gfx3d 3
1137                                   &gfx3d 4
1138                                   &gfx3d 5
1139                                   &gfx3d 6
1140                                   &gfx3d 7
1141                                   &gfx3d 8
1142                                   &gfx3d 9
1143                                   &gfx3d 10
1144                                   &gfx3d 11
1145                                   &gfx3d 12
1146                                   &gfx3d 13
1147                                   &gfx3d 14
1148                                   &gfx3d 15
1149                                   &gfx3d 16
1150                                   &gfx3d 17
1151                                   &gfx3d 18
1152                                   &gfx3d 19
1153                                   &gfx3d 20
1154                                   &gfx3d 21
1155                                   &gfx3d 22
1156                                   &gfx3d 23
1157                                   &gfx3d 24
1158                                   &gfx3d 25
1159                                   &gfx3d 26
1160                                   &gfx3d 27
1161                                   &gfx3d 28
1162                                   &gfx3d 29
1163                                   &gfx3d 30
1164                                   &gfx3d 31
1165                                   &gfx3d1 0
1166                                   &gfx3d1 1
1167                                   &gfx3d1 2
1168                                   &gfx3d1 3
1169                                   &gfx3d1 4
1170                                   &gfx3d1 5
1171                                   &gfx3d1 6
1172                                   &gfx3d1 7
1173                                   &gfx3d1 8
1174                                   &gfx3d1 9
1175                                   &gfx3d1 10
1176                                   &gfx3d1 11
1177                                   &gfx3d1 12
1178                                   &gfx3d1 13
1179                                   &gfx3d1 14
1180                                   &gfx3d1 15
1181                                   &gfx3d1 16
1182                                   &gfx3d1 17
1183                                   &gfx3d1 18
1184                                   &gfx3d1 19
1185                                   &gfx3d1 20
1186                                   &gfx3d1 21
1187                                   &gfx3d1 22
1188                                   &gfx3d1 23
1189                                   &gfx3d1 24
1190                                   &gfx3d1 25
1191                                   &gfx3d1 26
1192                                   &gfx3d1 27
1193                                   &gfx3d1 28
1194                                   &gfx3d1 29
1195                                   &gfx3d1 30
1196                                   &gfx3d1 31>;
1197
1198                         qcom,gpu-pwrlevels {
1199                                 compatible = "qcom,gpu-pwrlevels";
1200                                 qcom,gpu-pwrlevel@0 {
1201                                         qcom,gpu-freq = <450000000>;
1202                                 };
1203                                 qcom,gpu-pwrlevel@1 {
1204                                         qcom,gpu-freq = <27000000>;
1205                                 };
1206                         };
1207                 };
1208
1209                 mmss_sfpb: syscon@5700000 {
1210                         compatible = "syscon";
1211                         reg = <0x5700000 0x70>;
1212                 };
1213
1214                 dsi0: mdss_dsi@4700000 {
1215                         compatible = "qcom,mdss-dsi-ctrl";
1216                         label = "MDSS DSI CTRL->0";
1217                         #address-cells = <1>;
1218                         #size-cells = <0>;
1219                         interrupts = <GIC_SPI 82 0>;
1220                         reg = <0x04700000 0x200>;
1221                         reg-names = "dsi_ctrl";
1222
1223                         clocks = <&mmcc DSI_M_AHB_CLK>,
1224                                 <&mmcc DSI_S_AHB_CLK>,
1225                                 <&mmcc AMP_AHB_CLK>,
1226                                 <&mmcc DSI_CLK>,
1227                                 <&mmcc DSI1_BYTE_CLK>,
1228                                 <&mmcc DSI_PIXEL_CLK>,
1229                                 <&mmcc DSI1_ESC_CLK>;
1230                         clock-names = "iface_clk", "bus_clk", "core_mmss_clk",
1231                                         "src_clk", "byte_clk", "pixel_clk",
1232                                         "core_clk";
1233
1234                         assigned-clocks = <&mmcc DSI1_BYTE_SRC>,
1235                                         <&mmcc DSI1_ESC_SRC>,
1236                                         <&mmcc DSI_SRC>,
1237                                         <&mmcc DSI_PIXEL_SRC>;
1238                         assigned-clock-parents = <&dsi0_phy 0>,
1239                                                 <&dsi0_phy 0>,
1240                                                 <&dsi0_phy 1>,
1241                                                 <&dsi0_phy 1>;
1242                         syscon-sfpb = <&mmss_sfpb>;
1243                         phys = <&dsi0_phy>;
1244                         ports {
1245                                 #address-cells = <1>;
1246                                 #size-cells = <0>;
1247
1248                                 port@0 {
1249                                         reg = <0>;
1250                                         dsi0_in: endpoint {
1251                                         };
1252                                 };
1253
1254                                 port@1 {
1255                                         reg = <1>;
1256                                         dsi0_out: endpoint {
1257                                         };
1258                                 };
1259                         };
1260                 };
1261
1262
1263                 dsi0_phy: dsi-phy@4700200 {
1264                         compatible = "qcom,dsi-phy-28nm-8960";
1265                         #clock-cells = <1>;
1266
1267                         reg = <0x04700200 0x100>,
1268                                 <0x04700300 0x200>,
1269                                 <0x04700500 0x5c>;
1270                         reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator";
1271                         clock-names = "iface_clk";
1272                         clocks = <&mmcc DSI_M_AHB_CLK>;
1273                 };
1274
1275
1276                 mdp_port0: iommu@7500000 {
1277                         compatible = "qcom,apq8064-iommu";
1278                         #iommu-cells = <1>;
1279                         clock-names =
1280                             "smmu_pclk",
1281                             "iommu_clk";
1282                         clocks =
1283                             <&mmcc SMMU_AHB_CLK>,
1284                             <&mmcc MDP_AXI_CLK>;
1285                         reg = <0x07500000 0x100000>;
1286                         interrupts =
1287                             <GIC_SPI 63 0>,
1288                             <GIC_SPI 64 0>;
1289                         qcom,ncb = <2>;
1290                 };
1291
1292                 mdp_port1: iommu@7600000 {
1293                         compatible = "qcom,apq8064-iommu";
1294                         #iommu-cells = <1>;
1295                         clock-names =
1296                             "smmu_pclk",
1297                             "iommu_clk";
1298                         clocks =
1299                             <&mmcc SMMU_AHB_CLK>,
1300                             <&mmcc MDP_AXI_CLK>;
1301                         reg = <0x07600000 0x100000>;
1302                         interrupts =
1303                             <GIC_SPI 61 0>,
1304                             <GIC_SPI 62 0>;
1305                         qcom,ncb = <2>;
1306                 };
1307
1308                 gfx3d: iommu@7c00000 {
1309                         compatible = "qcom,apq8064-iommu";
1310                         #iommu-cells = <1>;
1311                         clock-names =
1312                             "smmu_pclk",
1313                             "iommu_clk";
1314                         clocks =
1315                             <&mmcc SMMU_AHB_CLK>,
1316                             <&mmcc GFX3D_AXI_CLK>;
1317                         reg = <0x07c00000 0x100000>;
1318                         interrupts =
1319                             <GIC_SPI 69 0>,
1320                             <GIC_SPI 70 0>;
1321                         qcom,ncb = <3>;
1322                 };
1323
1324                 gfx3d1: iommu@7d00000 {
1325                         compatible = "qcom,apq8064-iommu";
1326                         #iommu-cells = <1>;
1327                         clock-names =
1328                             "smmu_pclk",
1329                             "iommu_clk";
1330                         clocks =
1331                             <&mmcc SMMU_AHB_CLK>,
1332                             <&mmcc GFX3D_AXI_CLK>;
1333                         reg = <0x07d00000 0x100000>;
1334                         interrupts =
1335                             <GIC_SPI 210 0>,
1336                             <GIC_SPI 211 0>;
1337                         qcom,ncb = <3>;
1338                 };
1339
1340                 pcie: pci@1b500000 {
1341                         compatible = "qcom,pcie-apq8064", "snps,dw-pcie";
1342                         reg = <0x1b500000 0x1000
1343                                0x1b502000 0x80
1344                                0x1b600000 0x100
1345                                0x0ff00000 0x100000>;
1346                         reg-names = "dbi", "elbi", "parf", "config";
1347                         device_type = "pci";
1348                         linux,pci-domain = <0>;
1349                         bus-range = <0x00 0xff>;
1350                         num-lanes = <1>;
1351                         #address-cells = <3>;
1352                         #size-cells = <2>;
1353                         ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000   /* I/O */
1354                                   0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */
1355                         interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
1356                         interrupt-names = "msi";
1357                         #interrupt-cells = <1>;
1358                         interrupt-map-mask = <0 0 0 0x7>;
1359                         interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1360                                         <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1361                                         <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1362                                         <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1363                         clocks = <&gcc PCIE_A_CLK>,
1364                                  <&gcc PCIE_H_CLK>,
1365                                  <&gcc PCIE_PHY_REF_CLK>;
1366                         clock-names = "core", "iface", "phy";
1367                         resets = <&gcc PCIE_ACLK_RESET>,
1368                                  <&gcc PCIE_HCLK_RESET>,
1369                                  <&gcc PCIE_POR_RESET>,
1370                                  <&gcc PCIE_PCI_RESET>,
1371                                  <&gcc PCIE_PHY_RESET>;
1372                         reset-names = "axi", "ahb", "por", "pci", "phy";
1373                         status = "disabled";
1374                 };
1375
1376                 hdmi: hdmi-tx@4a00000 {
1377                         compatible = "qcom,hdmi-tx-8960";
1378                         pinctrl-names = "default";
1379                         pinctrl-0 = <&hdmi_pinctrl>;
1380                         reg = <0x04a00000 0x2f0>;
1381                         reg-names = "core_physical";
1382                         interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1383                         clocks = <&mmcc HDMI_APP_CLK>,
1384                                  <&mmcc HDMI_M_AHB_CLK>,
1385                                  <&mmcc HDMI_S_AHB_CLK>;
1386                         clock-names = "core_clk",
1387                                       "master_iface_clk",
1388                                       "slave_iface_clk";
1389
1390                         phys = <&hdmi_phy>;
1391                         phy-names = "hdmi-phy";
1392
1393                         ports {
1394                                 #address-cells = <1>;
1395                                 #size-cells = <0>;
1396
1397                                 port@0 {
1398                                         reg = <0>;
1399                                         hdmi_in: endpoint {
1400                                         };
1401                                 };
1402
1403                                 port@1 {
1404                                         reg = <1>;
1405                                         hdmi_out: endpoint {
1406                                         };
1407                                 };
1408                         };
1409                 };
1410
1411                 hdmi_phy: hdmi-phy@4a00400 {
1412                         compatible = "qcom,hdmi-phy-8960";
1413                         reg = <0x4a00400 0x60>,
1414                               <0x4a00500 0x100>;
1415                         reg-names = "hdmi_phy",
1416                                     "hdmi_pll";
1417
1418                         clocks = <&mmcc HDMI_S_AHB_CLK>;
1419                         clock-names = "slave_iface_clk";
1420                 };
1421
1422                 mdp: mdp@5100000 {
1423                         compatible = "qcom,mdp4";
1424                         reg = <0x05100000 0xf0000>;
1425                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1426                         clocks = <&mmcc MDP_CLK>,
1427                                  <&mmcc MDP_AHB_CLK>,
1428                                  <&mmcc MDP_AXI_CLK>,
1429                                  <&mmcc MDP_LUT_CLK>,
1430                                  <&mmcc HDMI_TV_CLK>,
1431                                  <&mmcc MDP_TV_CLK>;
1432                         clock-names = "core_clk",
1433                                       "iface_clk",
1434                                       "bus_clk",
1435                                       "lut_clk",
1436                                       "hdmi_clk",
1437                                       "tv_clk";
1438
1439                         iommus = <&mdp_port0 0
1440                                   &mdp_port0 2
1441                                   &mdp_port1 0
1442                                   &mdp_port1 2>;
1443
1444                         ports {
1445                                 #address-cells = <1>;
1446                                 #size-cells = <0>;
1447
1448                                 port@0 {
1449                                         reg = <0>;
1450                                         mdp_lvds_out: endpoint {
1451                                         };
1452                                 };
1453
1454                                 port@1 {
1455                                         reg = <1>;
1456                                         mdp_dsi1_out: endpoint {
1457                                         };
1458                                 };
1459
1460                                 port@2 {
1461                                         reg = <2>;
1462                                         mdp_dsi2_out: endpoint {
1463                                         };
1464                                 };
1465
1466                                 port@3 {
1467                                         reg = <3>;
1468                                         mdp_dtv_out: endpoint {
1469                                         };
1470                                 };
1471                         };
1472                 };
1473
1474                 riva: riva-pil@3204000 {
1475                         compatible = "qcom,riva-pil";
1476
1477                         reg = <0x03200800 0x1000>, <0x03202000 0x2000>, <0x03204000 0x100>;
1478                         reg-names = "ccu", "dxe", "pmu";
1479
1480                         interrupts-extended = <&intc GIC_SPI 199 IRQ_TYPE_EDGE_RISING>,
1481                                               <&wcnss_smsm 6 IRQ_TYPE_EDGE_RISING>;
1482                         interrupt-names = "wdog", "fatal";
1483
1484                         memory-region = <&wcnss_mem>;
1485
1486                         vddcx-supply = <&pm8921_s3>;
1487                         vddmx-supply = <&pm8921_l24>;
1488                         vddpx-supply = <&pm8921_s4>;
1489
1490                         status = "disabled";
1491
1492                         iris {
1493                                 compatible = "qcom,wcn3660";
1494
1495                                 clocks = <&cxo_board>;
1496                                 clock-names = "xo";
1497
1498                                 vddxo-supply = <&pm8921_l4>;
1499                                 vddrfa-supply = <&pm8921_s2>;
1500                                 vddpa-supply = <&pm8921_l10>;
1501                                 vdddig-supply = <&pm8921_lvs2>;
1502                         };
1503
1504                         smd-edge {
1505                                 interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>;
1506
1507                                 qcom,ipc = <&l2cc 8 25>;
1508                                 qcom,smd-edge = <6>;
1509
1510                                 label = "riva";
1511
1512                                 wcnss {
1513                                         compatible = "qcom,wcnss";
1514                                         qcom,smd-channels = "WCNSS_CTRL";
1515
1516                                         qcom,mmio = <&riva>;
1517
1518                                         bt {
1519                                                 compatible = "qcom,wcnss-bt";
1520                                         };
1521
1522                                         wifi {
1523                                                 compatible = "qcom,wcnss-wlan";
1524
1525                                                 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
1526                                                              <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
1527                                                 interrupt-names = "tx", "rx";
1528
1529                                                 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
1530                                                 qcom,smem-state-names = "tx-enable", "tx-rings-empty";
1531                                         };
1532                                 };
1533                         };
1534                 };
1535
1536                 etb@1a01000 {
1537                         compatible = "coresight-etb10", "arm,primecell";
1538                         reg = <0x1a01000 0x1000>;
1539
1540                         clocks = <&rpmcc RPM_QDSS_CLK>;
1541                         clock-names = "apb_pclk";
1542
1543                         port {
1544                                 etb_in: endpoint {
1545                                         slave-mode;
1546                                         remote-endpoint = <&replicator_out0>;
1547                                 };
1548                         };
1549                 };
1550
1551                 tpiu@1a03000 {
1552                         compatible = "arm,coresight-tpiu", "arm,primecell";
1553                         reg = <0x1a03000 0x1000>;
1554
1555                         clocks = <&rpmcc RPM_QDSS_CLK>;
1556                         clock-names = "apb_pclk";
1557
1558                         port {
1559                                 tpiu_in: endpoint {
1560                                         slave-mode;
1561                                         remote-endpoint = <&replicator_out1>;
1562                                 };
1563                         };
1564                 };
1565
1566                 replicator {
1567                         compatible = "arm,coresight-replicator";
1568
1569                         clocks = <&rpmcc RPM_QDSS_CLK>;
1570                         clock-names = "apb_pclk";
1571
1572                         ports {
1573                                 #address-cells = <1>;
1574                                 #size-cells = <0>;
1575
1576                                 port@0 {
1577                                         reg = <0>;
1578                                         replicator_out0: endpoint {
1579                                                 remote-endpoint = <&etb_in>;
1580                                         };
1581                                 };
1582                                 port@1 {
1583                                         reg = <1>;
1584                                         replicator_out1: endpoint {
1585                                                 remote-endpoint = <&tpiu_in>;
1586                                         };
1587                                 };
1588                                 port@2 {
1589                                         reg = <0>;
1590                                         replicator_in: endpoint {
1591                                                 slave-mode;
1592                                                 remote-endpoint = <&funnel_out>;
1593                                         };
1594                                 };
1595                         };
1596                 };
1597
1598                 funnel@1a04000 {
1599                         compatible = "arm,coresight-funnel", "arm,primecell";
1600                         reg = <0x1a04000 0x1000>;
1601
1602                         clocks = <&rpmcc RPM_QDSS_CLK>;
1603                         clock-names = "apb_pclk";
1604
1605                         ports {
1606                                 #address-cells = <1>;
1607                                 #size-cells = <0>;
1608
1609                                 /*
1610                                  * Not described input ports:
1611                                  * 2 - connected to STM component
1612                                  * 3 - not-connected
1613                                  * 6 - not-connected
1614                                  * 7 - not-connected
1615                                  */
1616                                 port@0 {
1617                                         reg = <0>;
1618                                         funnel_in0: endpoint {
1619                                                 slave-mode;
1620                                                 remote-endpoint = <&etm0_out>;
1621                                         };
1622                                 };
1623                                 port@1 {
1624                                         reg = <1>;
1625                                         funnel_in1: endpoint {
1626                                                 slave-mode;
1627                                                 remote-endpoint = <&etm1_out>;
1628                                         };
1629                                 };
1630                                 port@4 {
1631                                         reg = <4>;
1632                                         funnel_in4: endpoint {
1633                                                 slave-mode;
1634                                                 remote-endpoint = <&etm2_out>;
1635                                         };
1636                                 };
1637                                 port@5 {
1638                                         reg = <5>;
1639                                         funnel_in5: endpoint {
1640                                                 slave-mode;
1641                                                 remote-endpoint = <&etm3_out>;
1642                                         };
1643                                 };
1644                                 port@8 {
1645                                         reg = <0>;
1646                                         funnel_out: endpoint {
1647                                                 remote-endpoint = <&replicator_in>;
1648                                         };
1649                                 };
1650                         };
1651                 };
1652
1653                 etm@1a1c000 {
1654                         compatible = "arm,coresight-etm3x", "arm,primecell";
1655                         reg = <0x1a1c000 0x1000>;
1656
1657                         clocks = <&rpmcc RPM_QDSS_CLK>;
1658                         clock-names = "apb_pclk";
1659
1660                         cpu = <&CPU0>;
1661
1662                         port {
1663                                 etm0_out: endpoint {
1664                                         remote-endpoint = <&funnel_in0>;
1665                                 };
1666                         };
1667                 };
1668
1669                 etm@1a1d000 {
1670                         compatible = "arm,coresight-etm3x", "arm,primecell";
1671                         reg = <0x1a1d000 0x1000>;
1672
1673                         clocks = <&rpmcc RPM_QDSS_CLK>;
1674                         clock-names = "apb_pclk";
1675
1676                         cpu = <&CPU1>;
1677
1678                         port {
1679                                 etm1_out: endpoint {
1680                                         remote-endpoint = <&funnel_in1>;
1681                                 };
1682                         };
1683                 };
1684
1685                 etm@1a1e000 {
1686                         compatible = "arm,coresight-etm3x", "arm,primecell";
1687                         reg = <0x1a1e000 0x1000>;
1688
1689                         clocks = <&rpmcc RPM_QDSS_CLK>;
1690                         clock-names = "apb_pclk";
1691
1692                         cpu = <&CPU2>;
1693
1694                         port {
1695                                 etm2_out: endpoint {
1696                                         remote-endpoint = <&funnel_in4>;
1697                                 };
1698                         };
1699                 };
1700
1701                 etm@1a1f000 {
1702                         compatible = "arm,coresight-etm3x", "arm,primecell";
1703                         reg = <0x1a1f000 0x1000>;
1704
1705                         clocks = <&rpmcc RPM_QDSS_CLK>;
1706                         clock-names = "apb_pclk";
1707
1708                         cpu = <&CPU3>;
1709
1710                         port {
1711                                 etm3_out: endpoint {
1712                                         remote-endpoint = <&funnel_in5>;
1713                                 };
1714                         };
1715                 };
1716         };
1717 };
1718 #include "qcom-apq8064-pins.dtsi"