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Merge tag 'iio-fixes-for-4.17a' of git://git.kernel.org/pub/scm/linux/kernel/git...
[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / qcom-apq8064.dtsi
1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
3
4 #include "skeleton.dtsi"
5 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
6 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/soc/qcom,gsbi.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 / {
13 model = "Qualcomm APQ8064";
14 compatible = "qcom,apq8064";
15 interrupt-parent = <&intc>;
16
17 reserved-memory {
18 #address-cells = <1>;
19 #size-cells = <1>;
20 ranges;
21
22 smem_region: smem@80000000 {
23 reg = <0x80000000 0x200000>;
24 no-map;
25 };
26
27 wcnss_mem: wcnss@8f000000 {
28 reg = <0x8f000000 0x700000>;
29 no-map;
30 };
31 };
32
33 cpus {
34 #address-cells = <1>;
35 #size-cells = <0>;
36
37 CPU0: cpu@0 {
38 compatible = "qcom,krait";
39 enable-method = "qcom,kpss-acc-v1";
40 device_type = "cpu";
41 reg = <0>;
42 next-level-cache = <&L2>;
43 qcom,acc = <&acc0>;
44 qcom,saw = <&saw0>;
45 cpu-idle-states = <&CPU_SPC>;
46 };
47
48 CPU1: cpu@1 {
49 compatible = "qcom,krait";
50 enable-method = "qcom,kpss-acc-v1";
51 device_type = "cpu";
52 reg = <1>;
53 next-level-cache = <&L2>;
54 qcom,acc = <&acc1>;
55 qcom,saw = <&saw1>;
56 cpu-idle-states = <&CPU_SPC>;
57 };
58
59 CPU2: cpu@2 {
60 compatible = "qcom,krait";
61 enable-method = "qcom,kpss-acc-v1";
62 device_type = "cpu";
63 reg = <2>;
64 next-level-cache = <&L2>;
65 qcom,acc = <&acc2>;
66 qcom,saw = <&saw2>;
67 cpu-idle-states = <&CPU_SPC>;
68 };
69
70 CPU3: cpu@3 {
71 compatible = "qcom,krait";
72 enable-method = "qcom,kpss-acc-v1";
73 device_type = "cpu";
74 reg = <3>;
75 next-level-cache = <&L2>;
76 qcom,acc = <&acc3>;
77 qcom,saw = <&saw3>;
78 cpu-idle-states = <&CPU_SPC>;
79 };
80
81 L2: l2-cache {
82 compatible = "cache";
83 cache-level = <2>;
84 };
85
86 idle-states {
87 CPU_SPC: spc {
88 compatible = "qcom,idle-state-spc",
89 "arm,idle-state";
90 entry-latency-us = <400>;
91 exit-latency-us = <900>;
92 min-residency-us = <3000>;
93 };
94 };
95 };
96
97 thermal-zones {
98 cpu-thermal0 {
99 polling-delay-passive = <250>;
100 polling-delay = <1000>;
101
102 thermal-sensors = <&gcc 7>;
103 coefficients = <1199 0>;
104
105 trips {
106 cpu_alert0: trip0 {
107 temperature = <75000>;
108 hysteresis = <2000>;
109 type = "passive";
110 };
111 cpu_crit0: trip1 {
112 temperature = <110000>;
113 hysteresis = <2000>;
114 type = "critical";
115 };
116 };
117 };
118
119 cpu-thermal1 {
120 polling-delay-passive = <250>;
121 polling-delay = <1000>;
122
123 thermal-sensors = <&gcc 8>;
124 coefficients = <1132 0>;
125
126 trips {
127 cpu_alert1: trip0 {
128 temperature = <75000>;
129 hysteresis = <2000>;
130 type = "passive";
131 };
132 cpu_crit1: trip1 {
133 temperature = <110000>;
134 hysteresis = <2000>;
135 type = "critical";
136 };
137 };
138 };
139
140 cpu-thermal2 {
141 polling-delay-passive = <250>;
142 polling-delay = <1000>;
143
144 thermal-sensors = <&gcc 9>;
145 coefficients = <1199 0>;
146
147 trips {
148 cpu_alert2: trip0 {
149 temperature = <75000>;
150 hysteresis = <2000>;
151 type = "passive";
152 };
153 cpu_crit2: trip1 {
154 temperature = <110000>;
155 hysteresis = <2000>;
156 type = "critical";
157 };
158 };
159 };
160
161 cpu-thermal3 {
162 polling-delay-passive = <250>;
163 polling-delay = <1000>;
164
165 thermal-sensors = <&gcc 10>;
166 coefficients = <1132 0>;
167
168 trips {
169 cpu_alert3: trip0 {
170 temperature = <75000>;
171 hysteresis = <2000>;
172 type = "passive";
173 };
174 cpu_crit3: trip1 {
175 temperature = <110000>;
176 hysteresis = <2000>;
177 type = "critical";
178 };
179 };
180 };
181 };
182
183 cpu-pmu {
184 compatible = "qcom,krait-pmu";
185 interrupts = <1 10 0x304>;
186 };
187
188 clocks {
189 cxo_board: cxo_board {
190 compatible = "fixed-clock";
191 #clock-cells = <0>;
192 clock-frequency = <19200000>;
193 };
194
195 pxo_board {
196 compatible = "fixed-clock";
197 #clock-cells = <0>;
198 clock-frequency = <27000000>;
199 };
200
201 sleep_clk: sleep_clk {
202 compatible = "fixed-clock";
203 #clock-cells = <0>;
204 clock-frequency = <32768>;
205 };
206 };
207
208 sfpb_mutex: hwmutex {
209 compatible = "qcom,sfpb-mutex";
210 syscon = <&sfpb_wrapper_mutex 0x604 0x4>;
211 #hwlock-cells = <1>;
212 };
213
214 smem {
215 compatible = "qcom,smem";
216 memory-region = <&smem_region>;
217
218 hwlocks = <&sfpb_mutex 3>;
219 };
220
221 smd {
222 compatible = "qcom,smd";
223
224 modem@0 {
225 interrupts = <0 37 IRQ_TYPE_EDGE_RISING>;
226
227 qcom,ipc = <&l2cc 8 3>;
228 qcom,smd-edge = <0>;
229
230 status = "disabled";
231 };
232
233 q6@1 {
234 interrupts = <0 90 IRQ_TYPE_EDGE_RISING>;
235
236 qcom,ipc = <&l2cc 8 15>;
237 qcom,smd-edge = <1>;
238
239 status = "disabled";
240 };
241
242 dsps@3 {
243 interrupts = <0 138 IRQ_TYPE_EDGE_RISING>;
244
245 qcom,ipc = <&sps_sic_non_secure 0x4080 0>;
246 qcom,smd-edge = <3>;
247
248 status = "disabled";
249 };
250
251 riva@6 {
252 interrupts = <0 198 IRQ_TYPE_EDGE_RISING>;
253
254 qcom,ipc = <&l2cc 8 25>;
255 qcom,smd-edge = <6>;
256
257 status = "disabled";
258 };
259 };
260
261 smsm {
262 compatible = "qcom,smsm";
263
264 #address-cells = <1>;
265 #size-cells = <0>;
266
267 qcom,ipc-1 = <&l2cc 8 4>;
268 qcom,ipc-2 = <&l2cc 8 14>;
269 qcom,ipc-3 = <&l2cc 8 23>;
270 qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>;
271
272 apps_smsm: apps@0 {
273 reg = <0>;
274 #qcom,smem-state-cells = <1>;
275 };
276
277 modem_smsm: modem@1 {
278 reg = <1>;
279 interrupts = <0 38 IRQ_TYPE_EDGE_RISING>;
280
281 interrupt-controller;
282 #interrupt-cells = <2>;
283 };
284
285 q6_smsm: q6@2 {
286 reg = <2>;
287 interrupts = <0 89 IRQ_TYPE_EDGE_RISING>;
288
289 interrupt-controller;
290 #interrupt-cells = <2>;
291 };
292
293 wcnss_smsm: wcnss@3 {
294 reg = <3>;
295 interrupts = <0 204 IRQ_TYPE_EDGE_RISING>;
296
297 interrupt-controller;
298 #interrupt-cells = <2>;
299 };
300
301 dsps_smsm: dsps@4 {
302 reg = <4>;
303 interrupts = <0 137 IRQ_TYPE_EDGE_RISING>;
304
305 interrupt-controller;
306 #interrupt-cells = <2>;
307 };
308 };
309
310 firmware {
311 scm {
312 compatible = "qcom,scm-apq8064";
313
314 clocks = <&rpmcc RPM_DAYTONA_FABRIC_CLK>;
315 clock-names = "core";
316 };
317 };
318
319
320 /*
321 * These channels from the ADC are simply hardware monitors.
322 * That is why the ADC is referred to as "HKADC" - HouseKeeping
323 * ADC.
324 */
325 iio-hwmon {
326 compatible = "iio-hwmon";
327 io-channels = <&xoadc 0x00 0x01>, /* Battery */
328 <&xoadc 0x00 0x02>, /* DC in (charger) */
329 <&xoadc 0x00 0x04>, /* VPH the main system voltage */
330 <&xoadc 0x00 0x0b>, /* Die temperature */
331 <&xoadc 0x00 0x0c>, /* Reference voltage 1.25V */
332 <&xoadc 0x00 0x0d>, /* Reference voltage 0.625V */
333 <&xoadc 0x00 0x0e>; /* Charger temperature */
334 };
335
336 soc: soc {
337 #address-cells = <1>;
338 #size-cells = <1>;
339 ranges;
340 compatible = "simple-bus";
341
342 tlmm_pinmux: pinctrl@800000 {
343 compatible = "qcom,apq8064-pinctrl";
344 reg = <0x800000 0x4000>;
345
346 gpio-controller;
347 #gpio-cells = <2>;
348 interrupt-controller;
349 #interrupt-cells = <2>;
350 interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
351
352 pinctrl-names = "default";
353 pinctrl-0 = <&ps_hold>;
354 };
355
356 sfpb_wrapper_mutex: syscon@1200000 {
357 compatible = "syscon";
358 reg = <0x01200000 0x8000>;
359 };
360
361 intc: interrupt-controller@2000000 {
362 compatible = "qcom,msm-qgic2";
363 interrupt-controller;
364 #interrupt-cells = <3>;
365 reg = <0x02000000 0x1000>,
366 <0x02002000 0x1000>;
367 };
368
369 timer@200a000 {
370 compatible = "qcom,kpss-timer",
371 "qcom,kpss-wdt-apq8064", "qcom,msm-timer";
372 interrupts = <1 1 0x301>,
373 <1 2 0x301>,
374 <1 3 0x301>;
375 reg = <0x0200a000 0x100>;
376 clock-frequency = <27000000>,
377 <32768>;
378 cpu-offset = <0x80000>;
379 };
380
381 acc0: clock-controller@2088000 {
382 compatible = "qcom,kpss-acc-v1";
383 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
384 };
385
386 acc1: clock-controller@2098000 {
387 compatible = "qcom,kpss-acc-v1";
388 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
389 };
390
391 acc2: clock-controller@20a8000 {
392 compatible = "qcom,kpss-acc-v1";
393 reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
394 };
395
396 acc3: clock-controller@20b8000 {
397 compatible = "qcom,kpss-acc-v1";
398 reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
399 };
400
401 saw0: power-controller@2089000 {
402 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
403 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
404 regulator;
405 };
406
407 saw1: power-controller@2099000 {
408 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
409 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
410 regulator;
411 };
412
413 saw2: power-controller@20a9000 {
414 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
415 reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
416 regulator;
417 };
418
419 saw3: power-controller@20b9000 {
420 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
421 reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
422 regulator;
423 };
424
425 sps_sic_non_secure: sps-sic-non-secure@12100000 {
426 compatible = "syscon";
427 reg = <0x12100000 0x10000>;
428 };
429
430 gsbi1: gsbi@12440000 {
431 status = "disabled";
432 compatible = "qcom,gsbi-v1.0.0";
433 cell-index = <1>;
434 reg = <0x12440000 0x100>;
435 clocks = <&gcc GSBI1_H_CLK>;
436 clock-names = "iface";
437 #address-cells = <1>;
438 #size-cells = <1>;
439 ranges;
440
441 syscon-tcsr = <&tcsr>;
442
443 gsbi1_serial: serial@12450000 {
444 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
445 reg = <0x12450000 0x100>,
446 <0x12400000 0x03>;
447 interrupts = <0 193 0x0>;
448 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
449 clock-names = "core", "iface";
450 status = "disabled";
451 };
452
453 gsbi1_i2c: i2c@12460000 {
454 compatible = "qcom,i2c-qup-v1.1.1";
455 pinctrl-0 = <&i2c1_pins>;
456 pinctrl-1 = <&i2c1_pins_sleep>;
457 pinctrl-names = "default", "sleep";
458 reg = <0x12460000 0x1000>;
459 interrupts = <0 194 IRQ_TYPE_NONE>;
460 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
461 clock-names = "core", "iface";
462 #address-cells = <1>;
463 #size-cells = <0>;
464 };
465
466 };
467
468 gsbi2: gsbi@12480000 {
469 status = "disabled";
470 compatible = "qcom,gsbi-v1.0.0";
471 cell-index = <2>;
472 reg = <0x12480000 0x100>;
473 clocks = <&gcc GSBI2_H_CLK>;
474 clock-names = "iface";
475 #address-cells = <1>;
476 #size-cells = <1>;
477 ranges;
478
479 syscon-tcsr = <&tcsr>;
480
481 gsbi2_i2c: i2c@124a0000 {
482 compatible = "qcom,i2c-qup-v1.1.1";
483 reg = <0x124a0000 0x1000>;
484 pinctrl-0 = <&i2c2_pins>;
485 pinctrl-1 = <&i2c2_pins_sleep>;
486 pinctrl-names = "default", "sleep";
487 interrupts = <0 196 IRQ_TYPE_NONE>;
488 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
489 clock-names = "core", "iface";
490 #address-cells = <1>;
491 #size-cells = <0>;
492 };
493 };
494
495 gsbi3: gsbi@16200000 {
496 status = "disabled";
497 compatible = "qcom,gsbi-v1.0.0";
498 cell-index = <3>;
499 reg = <0x16200000 0x100>;
500 clocks = <&gcc GSBI3_H_CLK>;
501 clock-names = "iface";
502 #address-cells = <1>;
503 #size-cells = <1>;
504 ranges;
505 gsbi3_i2c: i2c@16280000 {
506 compatible = "qcom,i2c-qup-v1.1.1";
507 pinctrl-0 = <&i2c3_pins>;
508 pinctrl-1 = <&i2c3_pins_sleep>;
509 pinctrl-names = "default", "sleep";
510 reg = <0x16280000 0x1000>;
511 interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
512 clocks = <&gcc GSBI3_QUP_CLK>,
513 <&gcc GSBI3_H_CLK>;
514 clock-names = "core", "iface";
515 #address-cells = <1>;
516 #size-cells = <0>;
517 };
518 };
519
520 gsbi4: gsbi@16300000 {
521 status = "disabled";
522 compatible = "qcom,gsbi-v1.0.0";
523 cell-index = <4>;
524 reg = <0x16300000 0x03>;
525 clocks = <&gcc GSBI4_H_CLK>;
526 clock-names = "iface";
527 #address-cells = <1>;
528 #size-cells = <1>;
529 ranges;
530
531 gsbi4_i2c: i2c@16380000 {
532 compatible = "qcom,i2c-qup-v1.1.1";
533 pinctrl-0 = <&i2c4_pins>;
534 pinctrl-1 = <&i2c4_pins_sleep>;
535 pinctrl-names = "default", "sleep";
536 reg = <0x16380000 0x1000>;
537 interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;
538 clocks = <&gcc GSBI4_QUP_CLK>,
539 <&gcc GSBI4_H_CLK>;
540 clock-names = "core", "iface";
541 };
542 };
543
544 gsbi5: gsbi@1a200000 {
545 status = "disabled";
546 compatible = "qcom,gsbi-v1.0.0";
547 cell-index = <5>;
548 reg = <0x1a200000 0x03>;
549 clocks = <&gcc GSBI5_H_CLK>;
550 clock-names = "iface";
551 #address-cells = <1>;
552 #size-cells = <1>;
553 ranges;
554
555 gsbi5_serial: serial@1a240000 {
556 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
557 reg = <0x1a240000 0x100>,
558 <0x1a200000 0x03>;
559 interrupts = <0 154 0x0>;
560 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
561 clock-names = "core", "iface";
562 status = "disabled";
563 };
564
565 gsbi5_spi: spi@1a280000 {
566 compatible = "qcom,spi-qup-v1.1.1";
567 reg = <0x1a280000 0x1000>;
568 interrupts = <0 155 0>;
569 pinctrl-0 = <&spi5_default>;
570 pinctrl-1 = <&spi5_sleep>;
571 pinctrl-names = "default", "sleep";
572 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
573 clock-names = "core", "iface";
574 status = "disabled";
575 #address-cells = <1>;
576 #size-cells = <0>;
577 };
578 };
579
580 gsbi6: gsbi@16500000 {
581 status = "disabled";
582 compatible = "qcom,gsbi-v1.0.0";
583 cell-index = <6>;
584 reg = <0x16500000 0x03>;
585 clocks = <&gcc GSBI6_H_CLK>;
586 clock-names = "iface";
587 #address-cells = <1>;
588 #size-cells = <1>;
589 ranges;
590
591 gsbi6_serial: serial@16540000 {
592 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
593 reg = <0x16540000 0x100>,
594 <0x16500000 0x03>;
595 interrupts = <0 156 0x0>;
596 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
597 clock-names = "core", "iface";
598 status = "disabled";
599 };
600
601 gsbi6_i2c: i2c@16580000 {
602 compatible = "qcom,i2c-qup-v1.1.1";
603 pinctrl-0 = <&i2c6_pins>;
604 pinctrl-1 = <&i2c6_pins_sleep>;
605 pinctrl-names = "default", "sleep";
606 reg = <0x16580000 0x1000>;
607 interrupts = <GIC_SPI 157 IRQ_TYPE_NONE>;
608 clocks = <&gcc GSBI6_QUP_CLK>,
609 <&gcc GSBI6_H_CLK>;
610 clock-names = "core", "iface";
611 status = "disabled";
612 };
613 };
614
615 gsbi7: gsbi@16600000 {
616 status = "disabled";
617 compatible = "qcom,gsbi-v1.0.0";
618 cell-index = <7>;
619 reg = <0x16600000 0x100>;
620 clocks = <&gcc GSBI7_H_CLK>;
621 clock-names = "iface";
622 #address-cells = <1>;
623 #size-cells = <1>;
624 ranges;
625 syscon-tcsr = <&tcsr>;
626
627 gsbi7_serial: serial@16640000 {
628 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
629 reg = <0x16640000 0x1000>,
630 <0x16600000 0x1000>;
631 interrupts = <0 158 0x0>;
632 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
633 clock-names = "core", "iface";
634 status = "disabled";
635 };
636
637 gsbi7_i2c: i2c@16680000 {
638 compatible = "qcom,i2c-qup-v1.1.1";
639 pinctrl-0 = <&i2c7_pins>;
640 pinctrl-1 = <&i2c7_pins_sleep>;
641 pinctrl-names = "default", "sleep";
642 reg = <0x16680000 0x1000>;
643 interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>;
644 clocks = <&gcc GSBI7_QUP_CLK>,
645 <&gcc GSBI7_H_CLK>;
646 clock-names = "core", "iface";
647 status = "disabled";
648 };
649 };
650
651 rng@1a500000 {
652 compatible = "qcom,prng";
653 reg = <0x1a500000 0x200>;
654 clocks = <&gcc PRNG_CLK>;
655 clock-names = "core";
656 };
657
658 ssbi@c00000 {
659 compatible = "qcom,ssbi";
660 reg = <0x00c00000 0x1000>;
661 qcom,controller-type = "pmic-arbiter";
662
663 pm8821: pmic@1 {
664 compatible = "qcom,pm8821";
665 interrupt-parent = <&tlmm_pinmux>;
666 interrupts = <76 IRQ_TYPE_LEVEL_LOW>;
667 #interrupt-cells = <2>;
668 interrupt-controller;
669 #address-cells = <1>;
670 #size-cells = <0>;
671
672 pm8821_mpps: mpps@50 {
673 compatible = "qcom,pm8821-mpp", "qcom,ssbi-mpp";
674 reg = <0x50>;
675 interrupts = <24 IRQ_TYPE_NONE>,
676 <25 IRQ_TYPE_NONE>,
677 <26 IRQ_TYPE_NONE>,
678 <27 IRQ_TYPE_NONE>;
679 gpio-controller;
680 #gpio-cells = <2>;
681 };
682 };
683 };
684
685 qcom,ssbi@500000 {
686 compatible = "qcom,ssbi";
687 reg = <0x00500000 0x1000>;
688 qcom,controller-type = "pmic-arbiter";
689
690 pmicintc: pmic@0 {
691 compatible = "qcom,pm8921";
692 interrupt-parent = <&tlmm_pinmux>;
693 interrupts = <74 8>;
694 #interrupt-cells = <2>;
695 interrupt-controller;
696 #address-cells = <1>;
697 #size-cells = <0>;
698
699 pm8921_gpio: gpio@150 {
700
701 compatible = "qcom,pm8921-gpio",
702 "qcom,ssbi-gpio";
703 reg = <0x150>;
704 interrupts = <192 IRQ_TYPE_NONE>,
705 <193 IRQ_TYPE_NONE>,
706 <194 IRQ_TYPE_NONE>,
707 <195 IRQ_TYPE_NONE>,
708 <196 IRQ_TYPE_NONE>,
709 <197 IRQ_TYPE_NONE>,
710 <198 IRQ_TYPE_NONE>,
711 <199 IRQ_TYPE_NONE>,
712 <200 IRQ_TYPE_NONE>,
713 <201 IRQ_TYPE_NONE>,
714 <202 IRQ_TYPE_NONE>,
715 <203 IRQ_TYPE_NONE>,
716 <204 IRQ_TYPE_NONE>,
717 <205 IRQ_TYPE_NONE>,
718 <206 IRQ_TYPE_NONE>,
719 <207 IRQ_TYPE_NONE>,
720 <208 IRQ_TYPE_NONE>,
721 <209 IRQ_TYPE_NONE>,
722 <210 IRQ_TYPE_NONE>,
723 <211 IRQ_TYPE_NONE>,
724 <212 IRQ_TYPE_NONE>,
725 <213 IRQ_TYPE_NONE>,
726 <214 IRQ_TYPE_NONE>,
727 <215 IRQ_TYPE_NONE>,
728 <216 IRQ_TYPE_NONE>,
729 <217 IRQ_TYPE_NONE>,
730 <218 IRQ_TYPE_NONE>,
731 <219 IRQ_TYPE_NONE>,
732 <220 IRQ_TYPE_NONE>,
733 <221 IRQ_TYPE_NONE>,
734 <222 IRQ_TYPE_NONE>,
735 <223 IRQ_TYPE_NONE>,
736 <224 IRQ_TYPE_NONE>,
737 <225 IRQ_TYPE_NONE>,
738 <226 IRQ_TYPE_NONE>,
739 <227 IRQ_TYPE_NONE>,
740 <228 IRQ_TYPE_NONE>,
741 <229 IRQ_TYPE_NONE>,
742 <230 IRQ_TYPE_NONE>,
743 <231 IRQ_TYPE_NONE>,
744 <232 IRQ_TYPE_NONE>,
745 <233 IRQ_TYPE_NONE>,
746 <234 IRQ_TYPE_NONE>,
747 <235 IRQ_TYPE_NONE>;
748 gpio-controller;
749 #gpio-cells = <2>;
750
751 };
752
753 pm8921_mpps: mpps@50 {
754 compatible = "qcom,pm8921-mpp",
755 "qcom,ssbi-mpp";
756 reg = <0x50>;
757 gpio-controller;
758 #gpio-cells = <2>;
759 interrupts =
760 <128 IRQ_TYPE_NONE>,
761 <129 IRQ_TYPE_NONE>,
762 <130 IRQ_TYPE_NONE>,
763 <131 IRQ_TYPE_NONE>,
764 <132 IRQ_TYPE_NONE>,
765 <133 IRQ_TYPE_NONE>,
766 <134 IRQ_TYPE_NONE>,
767 <135 IRQ_TYPE_NONE>,
768 <136 IRQ_TYPE_NONE>,
769 <137 IRQ_TYPE_NONE>,
770 <138 IRQ_TYPE_NONE>,
771 <139 IRQ_TYPE_NONE>;
772 };
773
774 rtc@11d {
775 compatible = "qcom,pm8921-rtc";
776 interrupt-parent = <&pmicintc>;
777 interrupts = <39 1>;
778 reg = <0x11d>;
779 allow-set-time;
780 };
781
782 pwrkey@1c {
783 compatible = "qcom,pm8921-pwrkey";
784 reg = <0x1c>;
785 interrupt-parent = <&pmicintc>;
786 interrupts = <50 1>, <51 1>;
787 debounce = <15625>;
788 pull-up;
789 };
790
791 xoadc: xoadc@197 {
792 compatible = "qcom,pm8921-adc";
793 reg = <197>;
794 interrupts-extended = <&pmicintc 78 IRQ_TYPE_EDGE_RISING>;
795 #address-cells = <2>;
796 #size-cells = <0>;
797 #io-channel-cells = <2>;
798
799 vcoin: adc-channel@00 {
800 reg = <0x00 0x00>;
801 };
802 vbat: adc-channel@01 {
803 reg = <0x00 0x01>;
804 };
805 dcin: adc-channel@02 {
806 reg = <0x00 0x02>;
807 };
808 vph_pwr: adc-channel@04 {
809 reg = <0x00 0x04>;
810 };
811 batt_therm: adc-channel@08 {
812 reg = <0x00 0x08>;
813 };
814 batt_id: adc-channel@09 {
815 reg = <0x00 0x09>;
816 };
817 usb_vbus: adc-channel@0a {
818 reg = <0x00 0x0a>;
819 };
820 die_temp: adc-channel@0b {
821 reg = <0x00 0x0b>;
822 };
823 ref_625mv: adc-channel@0c {
824 reg = <0x00 0x0c>;
825 };
826 ref_1250mv: adc-channel@0d {
827 reg = <0x00 0x0d>;
828 };
829 chg_temp: adc-channel@0e {
830 reg = <0x00 0x0e>;
831 };
832 ref_muxoff: adc-channel@0f {
833 reg = <0x00 0x0f>;
834 };
835 };
836 };
837 };
838
839 qfprom: qfprom@700000 {
840 compatible = "qcom,qfprom";
841 reg = <0x00700000 0x1000>;
842 #address-cells = <1>;
843 #size-cells = <1>;
844 ranges;
845 tsens_calib: calib {
846 reg = <0x404 0x10>;
847 };
848 tsens_backup: backup_calib {
849 reg = <0x414 0x10>;
850 };
851 };
852
853 gcc: clock-controller@900000 {
854 compatible = "qcom,gcc-apq8064";
855 reg = <0x00900000 0x4000>;
856 nvmem-cells = <&tsens_calib>, <&tsens_backup>;
857 nvmem-cell-names = "calib", "calib_backup";
858 #clock-cells = <1>;
859 #reset-cells = <1>;
860 #thermal-sensor-cells = <1>;
861 };
862
863 lcc: clock-controller@28000000 {
864 compatible = "qcom,lcc-apq8064";
865 reg = <0x28000000 0x1000>;
866 #clock-cells = <1>;
867 #reset-cells = <1>;
868 };
869
870 mmcc: clock-controller@4000000 {
871 compatible = "qcom,mmcc-apq8064";
872 reg = <0x4000000 0x1000>;
873 #clock-cells = <1>;
874 #reset-cells = <1>;
875 };
876
877 l2cc: clock-controller@2011000 {
878 compatible = "syscon";
879 reg = <0x2011000 0x1000>;
880 };
881
882 rpm@108000 {
883 compatible = "qcom,rpm-apq8064";
884 reg = <0x108000 0x1000>;
885 qcom,ipc = <&l2cc 0x8 2>;
886
887 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
888 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
889 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
890 interrupt-names = "ack", "err", "wakeup";
891
892 rpmcc: clock-controller {
893 compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc";
894 #clock-cells = <1>;
895 };
896
897 regulators {
898 compatible = "qcom,rpm-pm8921-regulators";
899
900 pm8921_s1: s1 {};
901 pm8921_s2: s2 {};
902 pm8921_s3: s3 {};
903 pm8921_s4: s4 {};
904 pm8921_s7: s7 {};
905 pm8921_s8: s8 {};
906
907 pm8921_l1: l1 {};
908 pm8921_l2: l2 {};
909 pm8921_l3: l3 {};
910 pm8921_l4: l4 {};
911 pm8921_l5: l5 {};
912 pm8921_l6: l6 {};
913 pm8921_l7: l7 {};
914 pm8921_l8: l8 {};
915 pm8921_l9: l9 {};
916 pm8921_l10: l10 {};
917 pm8921_l11: l11 {};
918 pm8921_l12: l12 {};
919 pm8921_l14: l14 {};
920 pm8921_l15: l15 {};
921 pm8921_l16: l16 {};
922 pm8921_l17: l17 {};
923 pm8921_l18: l18 {};
924 pm8921_l21: l21 {};
925 pm8921_l22: l22 {};
926 pm8921_l23: l23 {};
927 pm8921_l24: l24 {};
928 pm8921_l25: l25 {};
929 pm8921_l26: l26 {};
930 pm8921_l27: l27 {};
931 pm8921_l28: l28 {};
932 pm8921_l29: l29 {};
933
934 pm8921_lvs1: lvs1 {};
935 pm8921_lvs2: lvs2 {};
936 pm8921_lvs3: lvs3 {};
937 pm8921_lvs4: lvs4 {};
938 pm8921_lvs5: lvs5 {};
939 pm8921_lvs6: lvs6 {};
940 pm8921_lvs7: lvs7 {};
941
942 pm8921_usb_switch: usb-switch {};
943
944 pm8921_hdmi_switch: hdmi-switch {
945 bias-pull-down;
946 };
947
948 pm8921_ncp: ncp {};
949 };
950 };
951
952 usb1: usb@12500000 {
953 compatible = "qcom,ci-hdrc";
954 reg = <0x12500000 0x200>,
955 <0x12500200 0x200>;
956 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
957 clocks = <&gcc USB_HS1_XCVR_CLK>, <&gcc USB_HS1_H_CLK>;
958 clock-names = "core", "iface";
959 assigned-clocks = <&gcc USB_HS1_XCVR_CLK>;
960 assigned-clock-rates = <60000000>;
961 resets = <&gcc USB_HS1_RESET>;
962 reset-names = "core";
963 phy_type = "ulpi";
964 ahb-burst-config = <0>;
965 phys = <&usb_hs1_phy>;
966 phy-names = "usb-phy";
967 status = "disabled";
968 #reset-cells = <1>;
969
970 ulpi {
971 usb_hs1_phy: phy {
972 compatible = "qcom,usb-hs-phy-apq8064",
973 "qcom,usb-hs-phy";
974 clocks = <&sleep_clk>, <&cxo_board>;
975 clock-names = "sleep", "ref";
976 resets = <&usb1 0>;
977 reset-names = "por";
978 #phy-cells = <0>;
979 };
980 };
981 };
982
983 usb3: usb@12520000 {
984 compatible = "qcom,ci-hdrc";
985 reg = <0x12520000 0x200>,
986 <0x12520200 0x200>;
987 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
988 clocks = <&gcc USB_HS3_XCVR_CLK>, <&gcc USB_HS3_H_CLK>;
989 clock-names = "core", "iface";
990 assigned-clocks = <&gcc USB_HS3_XCVR_CLK>;
991 assigned-clock-rates = <60000000>;
992 resets = <&gcc USB_HS3_RESET>;
993 reset-names = "core";
994 phy_type = "ulpi";
995 ahb-burst-config = <0>;
996 phys = <&usb_hs3_phy>;
997 phy-names = "usb-phy";
998 status = "disabled";
999 #reset-cells = <1>;
1000
1001 ulpi {
1002 usb_hs3_phy: phy {
1003 compatible = "qcom,usb-hs-phy-apq8064",
1004 "qcom,usb-hs-phy";
1005 #phy-cells = <0>;
1006 clocks = <&sleep_clk>, <&cxo_board>;
1007 clock-names = "sleep", "ref";
1008 resets = <&usb3 0>;
1009 reset-names = "por";
1010 };
1011 };
1012 };
1013
1014 usb4: usb@12530000 {
1015 compatible = "qcom,ci-hdrc";
1016 reg = <0x12530000 0x200>,
1017 <0x12530200 0x200>;
1018 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
1019 clocks = <&gcc USB_HS4_XCVR_CLK>, <&gcc USB_HS4_H_CLK>;
1020 clock-names = "core", "iface";
1021 assigned-clocks = <&gcc USB_HS4_XCVR_CLK>;
1022 assigned-clock-rates = <60000000>;
1023 resets = <&gcc USB_HS4_RESET>;
1024 reset-names = "core";
1025 phy_type = "ulpi";
1026 ahb-burst-config = <0>;
1027 phys = <&usb_hs4_phy>;
1028 phy-names = "usb-phy";
1029 status = "disabled";
1030 #reset-cells = <1>;
1031
1032 ulpi {
1033 usb_hs4_phy: phy {
1034 compatible = "qcom,usb-hs-phy-apq8064",
1035 "qcom,usb-hs-phy";
1036 #phy-cells = <0>;
1037 clocks = <&sleep_clk>, <&cxo_board>;
1038 clock-names = "sleep", "ref";
1039 resets = <&usb4 0>;
1040 reset-names = "por";
1041 };
1042 };
1043 };
1044
1045 sata_phy0: phy@1b400000 {
1046 compatible = "qcom,apq8064-sata-phy";
1047 status = "disabled";
1048 reg = <0x1b400000 0x200>;
1049 reg-names = "phy_mem";
1050 clocks = <&gcc SATA_PHY_CFG_CLK>;
1051 clock-names = "cfg";
1052 #phy-cells = <0>;
1053 };
1054
1055 sata0: sata@29000000 {
1056 compatible = "qcom,apq8064-ahci", "generic-ahci";
1057 status = "disabled";
1058 reg = <0x29000000 0x180>;
1059 interrupts = <GIC_SPI 209 IRQ_TYPE_NONE>;
1060
1061 clocks = <&gcc SFAB_SATA_S_H_CLK>,
1062 <&gcc SATA_H_CLK>,
1063 <&gcc SATA_A_CLK>,
1064 <&gcc SATA_RXOOB_CLK>,
1065 <&gcc SATA_PMALIVE_CLK>;
1066 clock-names = "slave_iface",
1067 "iface",
1068 "bus",
1069 "rxoob",
1070 "core_pmalive";
1071
1072 assigned-clocks = <&gcc SATA_RXOOB_CLK>,
1073 <&gcc SATA_PMALIVE_CLK>;
1074 assigned-clock-rates = <100000000>, <100000000>;
1075
1076 phys = <&sata_phy0>;
1077 phy-names = "sata-phy";
1078 ports-implemented = <0x1>;
1079 };
1080
1081 /* Temporary fixed regulator */
1082 sdcc1bam:dma@12402000{
1083 compatible = "qcom,bam-v1.3.0";
1084 reg = <0x12402000 0x8000>;
1085 interrupts = <0 98 0>;
1086 clocks = <&gcc SDC1_H_CLK>;
1087 clock-names = "bam_clk";
1088 #dma-cells = <1>;
1089 qcom,ee = <0>;
1090 };
1091
1092 sdcc3bam:dma@12182000{
1093 compatible = "qcom,bam-v1.3.0";
1094 reg = <0x12182000 0x8000>;
1095 interrupts = <0 96 0>;
1096 clocks = <&gcc SDC3_H_CLK>;
1097 clock-names = "bam_clk";
1098 #dma-cells = <1>;
1099 qcom,ee = <0>;
1100 };
1101
1102 sdcc4bam:dma@121c2000{
1103 compatible = "qcom,bam-v1.3.0";
1104 reg = <0x121c2000 0x8000>;
1105 interrupts = <0 95 0>;
1106 clocks = <&gcc SDC4_H_CLK>;
1107 clock-names = "bam_clk";
1108 #dma-cells = <1>;
1109 qcom,ee = <0>;
1110 };
1111
1112 amba {
1113 compatible = "simple-bus";
1114 #address-cells = <1>;
1115 #size-cells = <1>;
1116 ranges;
1117 sdcc1: sdcc@12400000 {
1118 status = "disabled";
1119 compatible = "arm,pl18x", "arm,primecell";
1120 pinctrl-names = "default";
1121 pinctrl-0 = <&sdcc1_pins>;
1122 arm,primecell-periphid = <0x00051180>;
1123 reg = <0x12400000 0x2000>;
1124 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1125 interrupt-names = "cmd_irq";
1126 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
1127 clock-names = "mclk", "apb_pclk";
1128 bus-width = <8>;
1129 max-frequency = <96000000>;
1130 non-removable;
1131 cap-sd-highspeed;
1132 cap-mmc-highspeed;
1133 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
1134 dma-names = "tx", "rx";
1135 };
1136
1137 sdcc3: sdcc@12180000 {
1138 compatible = "arm,pl18x", "arm,primecell";
1139 arm,primecell-periphid = <0x00051180>;
1140 status = "disabled";
1141 reg = <0x12180000 0x2000>;
1142 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1143 interrupt-names = "cmd_irq";
1144 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
1145 clock-names = "mclk", "apb_pclk";
1146 bus-width = <4>;
1147 cap-sd-highspeed;
1148 cap-mmc-highspeed;
1149 max-frequency = <192000000>;
1150 no-1-8-v;
1151 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
1152 dma-names = "tx", "rx";
1153 };
1154
1155 sdcc4: sdcc@121c0000 {
1156 compatible = "arm,pl18x", "arm,primecell";
1157 arm,primecell-periphid = <0x00051180>;
1158 status = "disabled";
1159 reg = <0x121c0000 0x2000>;
1160 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1161 interrupt-names = "cmd_irq";
1162 clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
1163 clock-names = "mclk", "apb_pclk";
1164 bus-width = <4>;
1165 cap-sd-highspeed;
1166 cap-mmc-highspeed;
1167 max-frequency = <48000000>;
1168 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
1169 dma-names = "tx", "rx";
1170 pinctrl-names = "default";
1171 pinctrl-0 = <&sdc4_gpios>;
1172 };
1173 };
1174
1175 tcsr: syscon@1a400000 {
1176 compatible = "qcom,tcsr-apq8064", "syscon";
1177 reg = <0x1a400000 0x100>;
1178 };
1179
1180 gpu: adreno-3xx@4300000 {
1181 compatible = "qcom,adreno-3xx";
1182 reg = <0x04300000 0x20000>;
1183 reg-names = "kgsl_3d0_reg_memory";
1184 interrupts = <GIC_SPI 80 0>;
1185 interrupt-names = "kgsl_3d0_irq";
1186 clock-names =
1187 "core_clk",
1188 "iface_clk",
1189 "mem_clk",
1190 "mem_iface_clk";
1191 clocks =
1192 <&mmcc GFX3D_CLK>,
1193 <&mmcc GFX3D_AHB_CLK>,
1194 <&mmcc GFX3D_AXI_CLK>,
1195 <&mmcc MMSS_IMEM_AHB_CLK>;
1196 qcom,chipid = <0x03020002>;
1197
1198 iommus = <&gfx3d 0
1199 &gfx3d 1
1200 &gfx3d 2
1201 &gfx3d 3
1202 &gfx3d 4
1203 &gfx3d 5
1204 &gfx3d 6
1205 &gfx3d 7
1206 &gfx3d 8
1207 &gfx3d 9
1208 &gfx3d 10
1209 &gfx3d 11
1210 &gfx3d 12
1211 &gfx3d 13
1212 &gfx3d 14
1213 &gfx3d 15
1214 &gfx3d 16
1215 &gfx3d 17
1216 &gfx3d 18
1217 &gfx3d 19
1218 &gfx3d 20
1219 &gfx3d 21
1220 &gfx3d 22
1221 &gfx3d 23
1222 &gfx3d 24
1223 &gfx3d 25
1224 &gfx3d 26
1225 &gfx3d 27
1226 &gfx3d 28
1227 &gfx3d 29
1228 &gfx3d 30
1229 &gfx3d 31
1230 &gfx3d1 0
1231 &gfx3d1 1
1232 &gfx3d1 2
1233 &gfx3d1 3
1234 &gfx3d1 4
1235 &gfx3d1 5
1236 &gfx3d1 6
1237 &gfx3d1 7
1238 &gfx3d1 8
1239 &gfx3d1 9
1240 &gfx3d1 10
1241 &gfx3d1 11
1242 &gfx3d1 12
1243 &gfx3d1 13
1244 &gfx3d1 14
1245 &gfx3d1 15
1246 &gfx3d1 16
1247 &gfx3d1 17
1248 &gfx3d1 18
1249 &gfx3d1 19
1250 &gfx3d1 20
1251 &gfx3d1 21
1252 &gfx3d1 22
1253 &gfx3d1 23
1254 &gfx3d1 24
1255 &gfx3d1 25
1256 &gfx3d1 26
1257 &gfx3d1 27
1258 &gfx3d1 28
1259 &gfx3d1 29
1260 &gfx3d1 30
1261 &gfx3d1 31>;
1262
1263 qcom,gpu-pwrlevels {
1264 compatible = "qcom,gpu-pwrlevels";
1265 qcom,gpu-pwrlevel@0 {
1266 qcom,gpu-freq = <450000000>;
1267 };
1268 qcom,gpu-pwrlevel@1 {
1269 qcom,gpu-freq = <27000000>;
1270 };
1271 };
1272 };
1273
1274 mmss_sfpb: syscon@5700000 {
1275 compatible = "syscon";
1276 reg = <0x5700000 0x70>;
1277 };
1278
1279 dsi0: mdss_dsi@4700000 {
1280 compatible = "qcom,mdss-dsi-ctrl";
1281 label = "MDSS DSI CTRL->0";
1282 #address-cells = <1>;
1283 #size-cells = <0>;
1284 interrupts = <GIC_SPI 82 0>;
1285 reg = <0x04700000 0x200>;
1286 reg-names = "dsi_ctrl";
1287
1288 clocks = <&mmcc DSI_M_AHB_CLK>,
1289 <&mmcc DSI_S_AHB_CLK>,
1290 <&mmcc AMP_AHB_CLK>,
1291 <&mmcc DSI_CLK>,
1292 <&mmcc DSI1_BYTE_CLK>,
1293 <&mmcc DSI_PIXEL_CLK>,
1294 <&mmcc DSI1_ESC_CLK>;
1295 clock-names = "iface_clk", "bus_clk", "core_mmss_clk",
1296 "src_clk", "byte_clk", "pixel_clk",
1297 "core_clk";
1298
1299 assigned-clocks = <&mmcc DSI1_BYTE_SRC>,
1300 <&mmcc DSI1_ESC_SRC>,
1301 <&mmcc DSI_SRC>,
1302 <&mmcc DSI_PIXEL_SRC>;
1303 assigned-clock-parents = <&dsi0_phy 0>,
1304 <&dsi0_phy 0>,
1305 <&dsi0_phy 1>,
1306 <&dsi0_phy 1>;
1307 syscon-sfpb = <&mmss_sfpb>;
1308 phys = <&dsi0_phy>;
1309 ports {
1310 #address-cells = <1>;
1311 #size-cells = <0>;
1312
1313 port@0 {
1314 reg = <0>;
1315 dsi0_in: endpoint {
1316 };
1317 };
1318
1319 port@1 {
1320 reg = <1>;
1321 dsi0_out: endpoint {
1322 };
1323 };
1324 };
1325 };
1326
1327
1328 dsi0_phy: dsi-phy@4700200 {
1329 compatible = "qcom,dsi-phy-28nm-8960";
1330 #clock-cells = <1>;
1331 #phy-cells = <0>;
1332
1333 reg = <0x04700200 0x100>,
1334 <0x04700300 0x200>,
1335 <0x04700500 0x5c>;
1336 reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator";
1337 clock-names = "iface_clk";
1338 clocks = <&mmcc DSI_M_AHB_CLK>;
1339 };
1340
1341
1342 mdp_port0: iommu@7500000 {
1343 compatible = "qcom,apq8064-iommu";
1344 #iommu-cells = <1>;
1345 clock-names =
1346 "smmu_pclk",
1347 "iommu_clk";
1348 clocks =
1349 <&mmcc SMMU_AHB_CLK>,
1350 <&mmcc MDP_AXI_CLK>;
1351 reg = <0x07500000 0x100000>;
1352 interrupts =
1353 <GIC_SPI 63 0>,
1354 <GIC_SPI 64 0>;
1355 qcom,ncb = <2>;
1356 };
1357
1358 mdp_port1: iommu@7600000 {
1359 compatible = "qcom,apq8064-iommu";
1360 #iommu-cells = <1>;
1361 clock-names =
1362 "smmu_pclk",
1363 "iommu_clk";
1364 clocks =
1365 <&mmcc SMMU_AHB_CLK>,
1366 <&mmcc MDP_AXI_CLK>;
1367 reg = <0x07600000 0x100000>;
1368 interrupts =
1369 <GIC_SPI 61 0>,
1370 <GIC_SPI 62 0>;
1371 qcom,ncb = <2>;
1372 };
1373
1374 gfx3d: iommu@7c00000 {
1375 compatible = "qcom,apq8064-iommu";
1376 #iommu-cells = <1>;
1377 clock-names =
1378 "smmu_pclk",
1379 "iommu_clk";
1380 clocks =
1381 <&mmcc SMMU_AHB_CLK>,
1382 <&mmcc GFX3D_AXI_CLK>;
1383 reg = <0x07c00000 0x100000>;
1384 interrupts =
1385 <GIC_SPI 69 0>,
1386 <GIC_SPI 70 0>;
1387 qcom,ncb = <3>;
1388 };
1389
1390 gfx3d1: iommu@7d00000 {
1391 compatible = "qcom,apq8064-iommu";
1392 #iommu-cells = <1>;
1393 clock-names =
1394 "smmu_pclk",
1395 "iommu_clk";
1396 clocks =
1397 <&mmcc SMMU_AHB_CLK>,
1398 <&mmcc GFX3D_AXI_CLK>;
1399 reg = <0x07d00000 0x100000>;
1400 interrupts =
1401 <GIC_SPI 210 0>,
1402 <GIC_SPI 211 0>;
1403 qcom,ncb = <3>;
1404 };
1405
1406 pcie: pci@1b500000 {
1407 compatible = "qcom,pcie-apq8064", "snps,dw-pcie";
1408 reg = <0x1b500000 0x1000
1409 0x1b502000 0x80
1410 0x1b600000 0x100
1411 0x0ff00000 0x100000>;
1412 reg-names = "dbi", "elbi", "parf", "config";
1413 device_type = "pci";
1414 linux,pci-domain = <0>;
1415 bus-range = <0x00 0xff>;
1416 num-lanes = <1>;
1417 #address-cells = <3>;
1418 #size-cells = <2>;
1419 ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* I/O */
1420 0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */
1421 interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
1422 interrupt-names = "msi";
1423 #interrupt-cells = <1>;
1424 interrupt-map-mask = <0 0 0 0x7>;
1425 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1426 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1427 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1428 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1429 clocks = <&gcc PCIE_A_CLK>,
1430 <&gcc PCIE_H_CLK>,
1431 <&gcc PCIE_PHY_REF_CLK>;
1432 clock-names = "core", "iface", "phy";
1433 resets = <&gcc PCIE_ACLK_RESET>,
1434 <&gcc PCIE_HCLK_RESET>,
1435 <&gcc PCIE_POR_RESET>,
1436 <&gcc PCIE_PCI_RESET>,
1437 <&gcc PCIE_PHY_RESET>;
1438 reset-names = "axi", "ahb", "por", "pci", "phy";
1439 status = "disabled";
1440 };
1441
1442 hdmi: hdmi-tx@4a00000 {
1443 compatible = "qcom,hdmi-tx-8960";
1444 pinctrl-names = "default";
1445 pinctrl-0 = <&hdmi_pinctrl>;
1446 reg = <0x04a00000 0x2f0>;
1447 reg-names = "core_physical";
1448 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1449 clocks = <&mmcc HDMI_APP_CLK>,
1450 <&mmcc HDMI_M_AHB_CLK>,
1451 <&mmcc HDMI_S_AHB_CLK>;
1452 clock-names = "core_clk",
1453 "master_iface_clk",
1454 "slave_iface_clk";
1455
1456 phys = <&hdmi_phy>;
1457 phy-names = "hdmi-phy";
1458
1459 ports {
1460 #address-cells = <1>;
1461 #size-cells = <0>;
1462
1463 port@0 {
1464 reg = <0>;
1465 hdmi_in: endpoint {
1466 };
1467 };
1468
1469 port@1 {
1470 reg = <1>;
1471 hdmi_out: endpoint {
1472 };
1473 };
1474 };
1475 };
1476
1477 hdmi_phy: hdmi-phy@4a00400 {
1478 compatible = "qcom,hdmi-phy-8960";
1479 reg = <0x4a00400 0x60>,
1480 <0x4a00500 0x100>;
1481 reg-names = "hdmi_phy",
1482 "hdmi_pll";
1483
1484 clocks = <&mmcc HDMI_S_AHB_CLK>;
1485 clock-names = "slave_iface_clk";
1486 #phy-cells = <0>;
1487 };
1488
1489 mdp: mdp@5100000 {
1490 compatible = "qcom,mdp4";
1491 reg = <0x05100000 0xf0000>;
1492 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1493 clocks = <&mmcc MDP_CLK>,
1494 <&mmcc MDP_AHB_CLK>,
1495 <&mmcc MDP_AXI_CLK>,
1496 <&mmcc MDP_LUT_CLK>,
1497 <&mmcc HDMI_TV_CLK>,
1498 <&mmcc MDP_TV_CLK>;
1499 clock-names = "core_clk",
1500 "iface_clk",
1501 "bus_clk",
1502 "lut_clk",
1503 "hdmi_clk",
1504 "tv_clk";
1505
1506 iommus = <&mdp_port0 0
1507 &mdp_port0 2
1508 &mdp_port1 0
1509 &mdp_port1 2>;
1510
1511 ports {
1512 #address-cells = <1>;
1513 #size-cells = <0>;
1514
1515 port@0 {
1516 reg = <0>;
1517 mdp_lvds_out: endpoint {
1518 };
1519 };
1520
1521 port@1 {
1522 reg = <1>;
1523 mdp_dsi1_out: endpoint {
1524 };
1525 };
1526
1527 port@2 {
1528 reg = <2>;
1529 mdp_dsi2_out: endpoint {
1530 };
1531 };
1532
1533 port@3 {
1534 reg = <3>;
1535 mdp_dtv_out: endpoint {
1536 };
1537 };
1538 };
1539 };
1540
1541 riva: riva-pil@3204000 {
1542 compatible = "qcom,riva-pil";
1543
1544 reg = <0x03200800 0x1000>, <0x03202000 0x2000>, <0x03204000 0x100>;
1545 reg-names = "ccu", "dxe", "pmu";
1546
1547 interrupts-extended = <&intc GIC_SPI 199 IRQ_TYPE_EDGE_RISING>,
1548 <&wcnss_smsm 6 IRQ_TYPE_EDGE_RISING>;
1549 interrupt-names = "wdog", "fatal";
1550
1551 memory-region = <&wcnss_mem>;
1552
1553 vddcx-supply = <&pm8921_s3>;
1554 vddmx-supply = <&pm8921_l24>;
1555 vddpx-supply = <&pm8921_s4>;
1556
1557 status = "disabled";
1558
1559 iris {
1560 compatible = "qcom,wcn3660";
1561
1562 clocks = <&cxo_board>;
1563 clock-names = "xo";
1564
1565 vddxo-supply = <&pm8921_l4>;
1566 vddrfa-supply = <&pm8921_s2>;
1567 vddpa-supply = <&pm8921_l10>;
1568 vdddig-supply = <&pm8921_lvs2>;
1569 };
1570
1571 smd-edge {
1572 interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>;
1573
1574 qcom,ipc = <&l2cc 8 25>;
1575 qcom,smd-edge = <6>;
1576
1577 label = "riva";
1578
1579 wcnss {
1580 compatible = "qcom,wcnss";
1581 qcom,smd-channels = "WCNSS_CTRL";
1582
1583 qcom,mmio = <&riva>;
1584
1585 bt {
1586 compatible = "qcom,wcnss-bt";
1587 };
1588
1589 wifi {
1590 compatible = "qcom,wcnss-wlan";
1591
1592 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
1593 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
1594 interrupt-names = "tx", "rx";
1595
1596 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
1597 qcom,smem-state-names = "tx-enable", "tx-rings-empty";
1598 };
1599 };
1600 };
1601 };
1602
1603 etb@1a01000 {
1604 compatible = "coresight-etb10", "arm,primecell";
1605 reg = <0x1a01000 0x1000>;
1606
1607 clocks = <&rpmcc RPM_QDSS_CLK>;
1608 clock-names = "apb_pclk";
1609
1610 port {
1611 etb_in: endpoint {
1612 slave-mode;
1613 remote-endpoint = <&replicator_out0>;
1614 };
1615 };
1616 };
1617
1618 tpiu@1a03000 {
1619 compatible = "arm,coresight-tpiu", "arm,primecell";
1620 reg = <0x1a03000 0x1000>;
1621
1622 clocks = <&rpmcc RPM_QDSS_CLK>;
1623 clock-names = "apb_pclk";
1624
1625 port {
1626 tpiu_in: endpoint {
1627 slave-mode;
1628 remote-endpoint = <&replicator_out1>;
1629 };
1630 };
1631 };
1632
1633 replicator {
1634 compatible = "arm,coresight-replicator";
1635
1636 clocks = <&rpmcc RPM_QDSS_CLK>;
1637 clock-names = "apb_pclk";
1638
1639 ports {
1640 #address-cells = <1>;
1641 #size-cells = <0>;
1642
1643 port@0 {
1644 reg = <0>;
1645 replicator_out0: endpoint {
1646 remote-endpoint = <&etb_in>;
1647 };
1648 };
1649 port@1 {
1650 reg = <1>;
1651 replicator_out1: endpoint {
1652 remote-endpoint = <&tpiu_in>;
1653 };
1654 };
1655 port@2 {
1656 reg = <0>;
1657 replicator_in: endpoint {
1658 slave-mode;
1659 remote-endpoint = <&funnel_out>;
1660 };
1661 };
1662 };
1663 };
1664
1665 funnel@1a04000 {
1666 compatible = "arm,coresight-funnel", "arm,primecell";
1667 reg = <0x1a04000 0x1000>;
1668
1669 clocks = <&rpmcc RPM_QDSS_CLK>;
1670 clock-names = "apb_pclk";
1671
1672 ports {
1673 #address-cells = <1>;
1674 #size-cells = <0>;
1675
1676 /*
1677 * Not described input ports:
1678 * 2 - connected to STM component
1679 * 3 - not-connected
1680 * 6 - not-connected
1681 * 7 - not-connected
1682 */
1683 port@0 {
1684 reg = <0>;
1685 funnel_in0: endpoint {
1686 slave-mode;
1687 remote-endpoint = <&etm0_out>;
1688 };
1689 };
1690 port@1 {
1691 reg = <1>;
1692 funnel_in1: endpoint {
1693 slave-mode;
1694 remote-endpoint = <&etm1_out>;
1695 };
1696 };
1697 port@4 {
1698 reg = <4>;
1699 funnel_in4: endpoint {
1700 slave-mode;
1701 remote-endpoint = <&etm2_out>;
1702 };
1703 };
1704 port@5 {
1705 reg = <5>;
1706 funnel_in5: endpoint {
1707 slave-mode;
1708 remote-endpoint = <&etm3_out>;
1709 };
1710 };
1711 port@8 {
1712 reg = <0>;
1713 funnel_out: endpoint {
1714 remote-endpoint = <&replicator_in>;
1715 };
1716 };
1717 };
1718 };
1719
1720 etm@1a1c000 {
1721 compatible = "arm,coresight-etm3x", "arm,primecell";
1722 reg = <0x1a1c000 0x1000>;
1723
1724 clocks = <&rpmcc RPM_QDSS_CLK>;
1725 clock-names = "apb_pclk";
1726
1727 cpu = <&CPU0>;
1728
1729 port {
1730 etm0_out: endpoint {
1731 remote-endpoint = <&funnel_in0>;
1732 };
1733 };
1734 };
1735
1736 etm@1a1d000 {
1737 compatible = "arm,coresight-etm3x", "arm,primecell";
1738 reg = <0x1a1d000 0x1000>;
1739
1740 clocks = <&rpmcc RPM_QDSS_CLK>;
1741 clock-names = "apb_pclk";
1742
1743 cpu = <&CPU1>;
1744
1745 port {
1746 etm1_out: endpoint {
1747 remote-endpoint = <&funnel_in1>;
1748 };
1749 };
1750 };
1751
1752 etm@1a1e000 {
1753 compatible = "arm,coresight-etm3x", "arm,primecell";
1754 reg = <0x1a1e000 0x1000>;
1755
1756 clocks = <&rpmcc RPM_QDSS_CLK>;
1757 clock-names = "apb_pclk";
1758
1759 cpu = <&CPU2>;
1760
1761 port {
1762 etm2_out: endpoint {
1763 remote-endpoint = <&funnel_in4>;
1764 };
1765 };
1766 };
1767
1768 etm@1a1f000 {
1769 compatible = "arm,coresight-etm3x", "arm,primecell";
1770 reg = <0x1a1f000 0x1000>;
1771
1772 clocks = <&rpmcc RPM_QDSS_CLK>;
1773 clock-names = "apb_pclk";
1774
1775 cpu = <&CPU3>;
1776
1777 port {
1778 etm3_out: endpoint {
1779 remote-endpoint = <&funnel_in5>;
1780 };
1781 };
1782 };
1783 };
1784 };
1785 #include "qcom-apq8064-pins.dtsi"
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