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Merge tag 'iommu-updates-v5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/joro...
[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / qcom-apq8064.dtsi
1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
3
4 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
5 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
6 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
7 #include <dt-bindings/clock/qcom,rpmcc.h>
8 #include <dt-bindings/soc/qcom,gsbi.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 / {
12 #address-cells = <1>;
13 #size-cells = <1>;
14 model = "Qualcomm APQ8064";
15 compatible = "qcom,apq8064";
16 interrupt-parent = <&intc>;
17
18 reserved-memory {
19 #address-cells = <1>;
20 #size-cells = <1>;
21 ranges;
22
23 smem_region: smem@80000000 {
24 reg = <0x80000000 0x200000>;
25 no-map;
26 };
27
28 wcnss_mem: wcnss@8f000000 {
29 reg = <0x8f000000 0x700000>;
30 no-map;
31 };
32 };
33
34 cpus {
35 #address-cells = <1>;
36 #size-cells = <0>;
37
38 CPU0: cpu@0 {
39 compatible = "qcom,krait";
40 enable-method = "qcom,kpss-acc-v1";
41 device_type = "cpu";
42 reg = <0>;
43 next-level-cache = <&L2>;
44 qcom,acc = <&acc0>;
45 qcom,saw = <&saw0>;
46 cpu-idle-states = <&CPU_SPC>;
47 };
48
49 CPU1: cpu@1 {
50 compatible = "qcom,krait";
51 enable-method = "qcom,kpss-acc-v1";
52 device_type = "cpu";
53 reg = <1>;
54 next-level-cache = <&L2>;
55 qcom,acc = <&acc1>;
56 qcom,saw = <&saw1>;
57 cpu-idle-states = <&CPU_SPC>;
58 };
59
60 CPU2: cpu@2 {
61 compatible = "qcom,krait";
62 enable-method = "qcom,kpss-acc-v1";
63 device_type = "cpu";
64 reg = <2>;
65 next-level-cache = <&L2>;
66 qcom,acc = <&acc2>;
67 qcom,saw = <&saw2>;
68 cpu-idle-states = <&CPU_SPC>;
69 };
70
71 CPU3: cpu@3 {
72 compatible = "qcom,krait";
73 enable-method = "qcom,kpss-acc-v1";
74 device_type = "cpu";
75 reg = <3>;
76 next-level-cache = <&L2>;
77 qcom,acc = <&acc3>;
78 qcom,saw = <&saw3>;
79 cpu-idle-states = <&CPU_SPC>;
80 };
81
82 L2: l2-cache {
83 compatible = "cache";
84 cache-level = <2>;
85 };
86
87 idle-states {
88 CPU_SPC: spc {
89 compatible = "qcom,idle-state-spc",
90 "arm,idle-state";
91 entry-latency-us = <400>;
92 exit-latency-us = <900>;
93 min-residency-us = <3000>;
94 };
95 };
96 };
97
98 memory {
99 device_type = "memory";
100 reg = <0x0 0x0>;
101 };
102
103 thermal-zones {
104 cpu-thermal0 {
105 polling-delay-passive = <250>;
106 polling-delay = <1000>;
107
108 thermal-sensors = <&gcc 7>;
109 coefficients = <1199 0>;
110
111 trips {
112 cpu_alert0: trip0 {
113 temperature = <75000>;
114 hysteresis = <2000>;
115 type = "passive";
116 };
117 cpu_crit0: trip1 {
118 temperature = <110000>;
119 hysteresis = <2000>;
120 type = "critical";
121 };
122 };
123 };
124
125 cpu-thermal1 {
126 polling-delay-passive = <250>;
127 polling-delay = <1000>;
128
129 thermal-sensors = <&gcc 8>;
130 coefficients = <1132 0>;
131
132 trips {
133 cpu_alert1: trip0 {
134 temperature = <75000>;
135 hysteresis = <2000>;
136 type = "passive";
137 };
138 cpu_crit1: trip1 {
139 temperature = <110000>;
140 hysteresis = <2000>;
141 type = "critical";
142 };
143 };
144 };
145
146 cpu-thermal2 {
147 polling-delay-passive = <250>;
148 polling-delay = <1000>;
149
150 thermal-sensors = <&gcc 9>;
151 coefficients = <1199 0>;
152
153 trips {
154 cpu_alert2: trip0 {
155 temperature = <75000>;
156 hysteresis = <2000>;
157 type = "passive";
158 };
159 cpu_crit2: trip1 {
160 temperature = <110000>;
161 hysteresis = <2000>;
162 type = "critical";
163 };
164 };
165 };
166
167 cpu-thermal3 {
168 polling-delay-passive = <250>;
169 polling-delay = <1000>;
170
171 thermal-sensors = <&gcc 10>;
172 coefficients = <1132 0>;
173
174 trips {
175 cpu_alert3: trip0 {
176 temperature = <75000>;
177 hysteresis = <2000>;
178 type = "passive";
179 };
180 cpu_crit3: trip1 {
181 temperature = <110000>;
182 hysteresis = <2000>;
183 type = "critical";
184 };
185 };
186 };
187 };
188
189 cpu-pmu {
190 compatible = "qcom,krait-pmu";
191 interrupts = <1 10 0x304>;
192 };
193
194 clocks {
195 cxo_board: cxo_board {
196 compatible = "fixed-clock";
197 #clock-cells = <0>;
198 clock-frequency = <19200000>;
199 };
200
201 pxo_board {
202 compatible = "fixed-clock";
203 #clock-cells = <0>;
204 clock-frequency = <27000000>;
205 };
206
207 sleep_clk: sleep_clk {
208 compatible = "fixed-clock";
209 #clock-cells = <0>;
210 clock-frequency = <32768>;
211 };
212 };
213
214 sfpb_mutex: hwmutex {
215 compatible = "qcom,sfpb-mutex";
216 syscon = <&sfpb_wrapper_mutex 0x604 0x4>;
217 #hwlock-cells = <1>;
218 };
219
220 smem {
221 compatible = "qcom,smem";
222 memory-region = <&smem_region>;
223
224 hwlocks = <&sfpb_mutex 3>;
225 };
226
227 smd {
228 compatible = "qcom,smd";
229
230 modem@0 {
231 interrupts = <0 37 IRQ_TYPE_EDGE_RISING>;
232
233 qcom,ipc = <&l2cc 8 3>;
234 qcom,smd-edge = <0>;
235
236 status = "disabled";
237 };
238
239 q6@1 {
240 interrupts = <0 90 IRQ_TYPE_EDGE_RISING>;
241
242 qcom,ipc = <&l2cc 8 15>;
243 qcom,smd-edge = <1>;
244
245 status = "disabled";
246 };
247
248 dsps@3 {
249 interrupts = <0 138 IRQ_TYPE_EDGE_RISING>;
250
251 qcom,ipc = <&sps_sic_non_secure 0x4080 0>;
252 qcom,smd-edge = <3>;
253
254 status = "disabled";
255 };
256
257 riva@6 {
258 interrupts = <0 198 IRQ_TYPE_EDGE_RISING>;
259
260 qcom,ipc = <&l2cc 8 25>;
261 qcom,smd-edge = <6>;
262
263 status = "disabled";
264 };
265 };
266
267 smsm {
268 compatible = "qcom,smsm";
269
270 #address-cells = <1>;
271 #size-cells = <0>;
272
273 qcom,ipc-1 = <&l2cc 8 4>;
274 qcom,ipc-2 = <&l2cc 8 14>;
275 qcom,ipc-3 = <&l2cc 8 23>;
276 qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>;
277
278 apps_smsm: apps@0 {
279 reg = <0>;
280 #qcom,smem-state-cells = <1>;
281 };
282
283 modem_smsm: modem@1 {
284 reg = <1>;
285 interrupts = <0 38 IRQ_TYPE_EDGE_RISING>;
286
287 interrupt-controller;
288 #interrupt-cells = <2>;
289 };
290
291 q6_smsm: q6@2 {
292 reg = <2>;
293 interrupts = <0 89 IRQ_TYPE_EDGE_RISING>;
294
295 interrupt-controller;
296 #interrupt-cells = <2>;
297 };
298
299 wcnss_smsm: wcnss@3 {
300 reg = <3>;
301 interrupts = <0 204 IRQ_TYPE_EDGE_RISING>;
302
303 interrupt-controller;
304 #interrupt-cells = <2>;
305 };
306
307 dsps_smsm: dsps@4 {
308 reg = <4>;
309 interrupts = <0 137 IRQ_TYPE_EDGE_RISING>;
310
311 interrupt-controller;
312 #interrupt-cells = <2>;
313 };
314 };
315
316 firmware {
317 scm {
318 compatible = "qcom,scm-apq8064";
319
320 clocks = <&rpmcc RPM_DAYTONA_FABRIC_CLK>;
321 clock-names = "core";
322 };
323 };
324
325
326 /*
327 * These channels from the ADC are simply hardware monitors.
328 * That is why the ADC is referred to as "HKADC" - HouseKeeping
329 * ADC.
330 */
331 iio-hwmon {
332 compatible = "iio-hwmon";
333 io-channels = <&xoadc 0x00 0x01>, /* Battery */
334 <&xoadc 0x00 0x02>, /* DC in (charger) */
335 <&xoadc 0x00 0x04>, /* VPH the main system voltage */
336 <&xoadc 0x00 0x0b>, /* Die temperature */
337 <&xoadc 0x00 0x0c>, /* Reference voltage 1.25V */
338 <&xoadc 0x00 0x0d>, /* Reference voltage 0.625V */
339 <&xoadc 0x00 0x0e>; /* Charger temperature */
340 };
341
342 soc: soc {
343 #address-cells = <1>;
344 #size-cells = <1>;
345 ranges;
346 compatible = "simple-bus";
347
348 tlmm_pinmux: pinctrl@800000 {
349 compatible = "qcom,apq8064-pinctrl";
350 reg = <0x800000 0x4000>;
351
352 gpio-controller;
353 #gpio-cells = <2>;
354 interrupt-controller;
355 #interrupt-cells = <2>;
356 interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
357
358 pinctrl-names = "default";
359 pinctrl-0 = <&ps_hold>;
360 };
361
362 sfpb_wrapper_mutex: syscon@1200000 {
363 compatible = "syscon";
364 reg = <0x01200000 0x8000>;
365 };
366
367 intc: interrupt-controller@2000000 {
368 compatible = "qcom,msm-qgic2";
369 interrupt-controller;
370 #interrupt-cells = <3>;
371 reg = <0x02000000 0x1000>,
372 <0x02002000 0x1000>;
373 };
374
375 timer@200a000 {
376 compatible = "qcom,kpss-timer",
377 "qcom,kpss-wdt-apq8064", "qcom,msm-timer";
378 interrupts = <1 1 0x301>,
379 <1 2 0x301>,
380 <1 3 0x301>;
381 reg = <0x0200a000 0x100>;
382 clock-frequency = <27000000>,
383 <32768>;
384 cpu-offset = <0x80000>;
385 };
386
387 acc0: clock-controller@2088000 {
388 compatible = "qcom,kpss-acc-v1";
389 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
390 };
391
392 acc1: clock-controller@2098000 {
393 compatible = "qcom,kpss-acc-v1";
394 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
395 };
396
397 acc2: clock-controller@20a8000 {
398 compatible = "qcom,kpss-acc-v1";
399 reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
400 };
401
402 acc3: clock-controller@20b8000 {
403 compatible = "qcom,kpss-acc-v1";
404 reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
405 };
406
407 saw0: power-controller@2089000 {
408 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
409 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
410 regulator;
411 };
412
413 saw1: power-controller@2099000 {
414 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
415 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
416 regulator;
417 };
418
419 saw2: power-controller@20a9000 {
420 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
421 reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
422 regulator;
423 };
424
425 saw3: power-controller@20b9000 {
426 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
427 reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
428 regulator;
429 };
430
431 sps_sic_non_secure: sps-sic-non-secure@12100000 {
432 compatible = "syscon";
433 reg = <0x12100000 0x10000>;
434 };
435
436 gsbi1: gsbi@12440000 {
437 status = "disabled";
438 compatible = "qcom,gsbi-v1.0.0";
439 cell-index = <1>;
440 reg = <0x12440000 0x100>;
441 clocks = <&gcc GSBI1_H_CLK>;
442 clock-names = "iface";
443 #address-cells = <1>;
444 #size-cells = <1>;
445 ranges;
446
447 syscon-tcsr = <&tcsr>;
448
449 gsbi1_serial: serial@12450000 {
450 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
451 reg = <0x12450000 0x100>,
452 <0x12400000 0x03>;
453 interrupts = <0 193 IRQ_TYPE_LEVEL_HIGH>;
454 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
455 clock-names = "core", "iface";
456 status = "disabled";
457 };
458
459 gsbi1_i2c: i2c@12460000 {
460 compatible = "qcom,i2c-qup-v1.1.1";
461 pinctrl-0 = <&i2c1_pins>;
462 pinctrl-1 = <&i2c1_pins_sleep>;
463 pinctrl-names = "default", "sleep";
464 reg = <0x12460000 0x1000>;
465 interrupts = <0 194 IRQ_TYPE_LEVEL_HIGH>;
466 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
467 clock-names = "core", "iface";
468 #address-cells = <1>;
469 #size-cells = <0>;
470 status = "disabled";
471 };
472
473 };
474
475 gsbi2: gsbi@12480000 {
476 status = "disabled";
477 compatible = "qcom,gsbi-v1.0.0";
478 cell-index = <2>;
479 reg = <0x12480000 0x100>;
480 clocks = <&gcc GSBI2_H_CLK>;
481 clock-names = "iface";
482 #address-cells = <1>;
483 #size-cells = <1>;
484 ranges;
485
486 syscon-tcsr = <&tcsr>;
487
488 gsbi2_i2c: i2c@124a0000 {
489 compatible = "qcom,i2c-qup-v1.1.1";
490 reg = <0x124a0000 0x1000>;
491 pinctrl-0 = <&i2c2_pins>;
492 pinctrl-1 = <&i2c2_pins_sleep>;
493 pinctrl-names = "default", "sleep";
494 interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>;
495 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
496 clock-names = "core", "iface";
497 #address-cells = <1>;
498 #size-cells = <0>;
499 status = "disabled";
500 };
501 };
502
503 gsbi3: gsbi@16200000 {
504 status = "disabled";
505 compatible = "qcom,gsbi-v1.0.0";
506 cell-index = <3>;
507 reg = <0x16200000 0x100>;
508 clocks = <&gcc GSBI3_H_CLK>;
509 clock-names = "iface";
510 #address-cells = <1>;
511 #size-cells = <1>;
512 ranges;
513 gsbi3_i2c: i2c@16280000 {
514 compatible = "qcom,i2c-qup-v1.1.1";
515 pinctrl-0 = <&i2c3_pins>;
516 pinctrl-1 = <&i2c3_pins_sleep>;
517 pinctrl-names = "default", "sleep";
518 reg = <0x16280000 0x1000>;
519 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
520 clocks = <&gcc GSBI3_QUP_CLK>,
521 <&gcc GSBI3_H_CLK>;
522 clock-names = "core", "iface";
523 #address-cells = <1>;
524 #size-cells = <0>;
525 status = "disabled";
526 };
527 };
528
529 gsbi4: gsbi@16300000 {
530 status = "disabled";
531 compatible = "qcom,gsbi-v1.0.0";
532 cell-index = <4>;
533 reg = <0x16300000 0x03>;
534 clocks = <&gcc GSBI4_H_CLK>;
535 clock-names = "iface";
536 #address-cells = <1>;
537 #size-cells = <1>;
538 ranges;
539
540 gsbi4_i2c: i2c@16380000 {
541 compatible = "qcom,i2c-qup-v1.1.1";
542 pinctrl-0 = <&i2c4_pins>;
543 pinctrl-1 = <&i2c4_pins_sleep>;
544 pinctrl-names = "default", "sleep";
545 reg = <0x16380000 0x1000>;
546 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
547 clocks = <&gcc GSBI4_QUP_CLK>,
548 <&gcc GSBI4_H_CLK>;
549 clock-names = "core", "iface";
550 status = "disabled";
551 };
552 };
553
554 gsbi5: gsbi@1a200000 {
555 status = "disabled";
556 compatible = "qcom,gsbi-v1.0.0";
557 cell-index = <5>;
558 reg = <0x1a200000 0x03>;
559 clocks = <&gcc GSBI5_H_CLK>;
560 clock-names = "iface";
561 #address-cells = <1>;
562 #size-cells = <1>;
563 ranges;
564
565 gsbi5_serial: serial@1a240000 {
566 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
567 reg = <0x1a240000 0x100>,
568 <0x1a200000 0x03>;
569 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
570 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
571 clock-names = "core", "iface";
572 status = "disabled";
573 };
574
575 gsbi5_spi: spi@1a280000 {
576 compatible = "qcom,spi-qup-v1.1.1";
577 reg = <0x1a280000 0x1000>;
578 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
579 pinctrl-0 = <&spi5_default>;
580 pinctrl-1 = <&spi5_sleep>;
581 pinctrl-names = "default", "sleep";
582 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
583 clock-names = "core", "iface";
584 status = "disabled";
585 #address-cells = <1>;
586 #size-cells = <0>;
587 };
588 };
589
590 gsbi6: gsbi@16500000 {
591 status = "disabled";
592 compatible = "qcom,gsbi-v1.0.0";
593 cell-index = <6>;
594 reg = <0x16500000 0x03>;
595 clocks = <&gcc GSBI6_H_CLK>;
596 clock-names = "iface";
597 #address-cells = <1>;
598 #size-cells = <1>;
599 ranges;
600
601 gsbi6_serial: serial@16540000 {
602 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
603 reg = <0x16540000 0x100>,
604 <0x16500000 0x03>;
605 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
606 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
607 clock-names = "core", "iface";
608 status = "disabled";
609 };
610
611 gsbi6_i2c: i2c@16580000 {
612 compatible = "qcom,i2c-qup-v1.1.1";
613 pinctrl-0 = <&i2c6_pins>;
614 pinctrl-1 = <&i2c6_pins_sleep>;
615 pinctrl-names = "default", "sleep";
616 reg = <0x16580000 0x1000>;
617 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
618 clocks = <&gcc GSBI6_QUP_CLK>,
619 <&gcc GSBI6_H_CLK>;
620 clock-names = "core", "iface";
621 status = "disabled";
622 };
623 };
624
625 gsbi7: gsbi@16600000 {
626 status = "disabled";
627 compatible = "qcom,gsbi-v1.0.0";
628 cell-index = <7>;
629 reg = <0x16600000 0x100>;
630 clocks = <&gcc GSBI7_H_CLK>;
631 clock-names = "iface";
632 #address-cells = <1>;
633 #size-cells = <1>;
634 ranges;
635 syscon-tcsr = <&tcsr>;
636
637 gsbi7_serial: serial@16640000 {
638 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
639 reg = <0x16640000 0x1000>,
640 <0x16600000 0x1000>;
641 interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
642 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
643 clock-names = "core", "iface";
644 status = "disabled";
645 };
646
647 gsbi7_i2c: i2c@16680000 {
648 compatible = "qcom,i2c-qup-v1.1.1";
649 pinctrl-0 = <&i2c7_pins>;
650 pinctrl-1 = <&i2c7_pins_sleep>;
651 pinctrl-names = "default", "sleep";
652 reg = <0x16680000 0x1000>;
653 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
654 clocks = <&gcc GSBI7_QUP_CLK>,
655 <&gcc GSBI7_H_CLK>;
656 clock-names = "core", "iface";
657 status = "disabled";
658 };
659 };
660
661 rng@1a500000 {
662 compatible = "qcom,prng";
663 reg = <0x1a500000 0x200>;
664 clocks = <&gcc PRNG_CLK>;
665 clock-names = "core";
666 };
667
668 ssbi@c00000 {
669 compatible = "qcom,ssbi";
670 reg = <0x00c00000 0x1000>;
671 qcom,controller-type = "pmic-arbiter";
672
673 pm8821: pmic@1 {
674 compatible = "qcom,pm8821";
675 interrupt-parent = <&tlmm_pinmux>;
676 interrupts = <76 IRQ_TYPE_LEVEL_LOW>;
677 #interrupt-cells = <2>;
678 interrupt-controller;
679 #address-cells = <1>;
680 #size-cells = <0>;
681
682 pm8821_mpps: mpps@50 {
683 compatible = "qcom,pm8821-mpp", "qcom,ssbi-mpp";
684 reg = <0x50>;
685 interrupts = <24 IRQ_TYPE_NONE>,
686 <25 IRQ_TYPE_NONE>,
687 <26 IRQ_TYPE_NONE>,
688 <27 IRQ_TYPE_NONE>;
689 gpio-controller;
690 #gpio-cells = <2>;
691 };
692 };
693 };
694
695 qcom,ssbi@500000 {
696 compatible = "qcom,ssbi";
697 reg = <0x00500000 0x1000>;
698 qcom,controller-type = "pmic-arbiter";
699
700 pmicintc: pmic@0 {
701 compatible = "qcom,pm8921";
702 interrupt-parent = <&tlmm_pinmux>;
703 interrupts = <74 8>;
704 #interrupt-cells = <2>;
705 interrupt-controller;
706 #address-cells = <1>;
707 #size-cells = <0>;
708
709 pm8921_gpio: gpio@150 {
710
711 compatible = "qcom,pm8921-gpio",
712 "qcom,ssbi-gpio";
713 reg = <0x150>;
714 interrupt-controller;
715 #interrupt-cells = <2>;
716 gpio-controller;
717 #gpio-cells = <2>;
718
719 };
720
721 pm8921_mpps: mpps@50 {
722 compatible = "qcom,pm8921-mpp",
723 "qcom,ssbi-mpp";
724 reg = <0x50>;
725 gpio-controller;
726 #gpio-cells = <2>;
727 interrupts =
728 <128 IRQ_TYPE_NONE>,
729 <129 IRQ_TYPE_NONE>,
730 <130 IRQ_TYPE_NONE>,
731 <131 IRQ_TYPE_NONE>,
732 <132 IRQ_TYPE_NONE>,
733 <133 IRQ_TYPE_NONE>,
734 <134 IRQ_TYPE_NONE>,
735 <135 IRQ_TYPE_NONE>,
736 <136 IRQ_TYPE_NONE>,
737 <137 IRQ_TYPE_NONE>,
738 <138 IRQ_TYPE_NONE>,
739 <139 IRQ_TYPE_NONE>;
740 };
741
742 rtc@11d {
743 compatible = "qcom,pm8921-rtc";
744 interrupt-parent = <&pmicintc>;
745 interrupts = <39 1>;
746 reg = <0x11d>;
747 allow-set-time;
748 };
749
750 pwrkey@1c {
751 compatible = "qcom,pm8921-pwrkey";
752 reg = <0x1c>;
753 interrupt-parent = <&pmicintc>;
754 interrupts = <50 1>, <51 1>;
755 debounce = <15625>;
756 pull-up;
757 };
758
759 xoadc: xoadc@197 {
760 compatible = "qcom,pm8921-adc";
761 reg = <197>;
762 interrupts-extended = <&pmicintc 78 IRQ_TYPE_EDGE_RISING>;
763 #address-cells = <2>;
764 #size-cells = <0>;
765 #io-channel-cells = <2>;
766
767 vcoin: adc-channel@00 {
768 reg = <0x00 0x00>;
769 };
770 vbat: adc-channel@01 {
771 reg = <0x00 0x01>;
772 };
773 dcin: adc-channel@02 {
774 reg = <0x00 0x02>;
775 };
776 vph_pwr: adc-channel@04 {
777 reg = <0x00 0x04>;
778 };
779 batt_therm: adc-channel@08 {
780 reg = <0x00 0x08>;
781 };
782 batt_id: adc-channel@09 {
783 reg = <0x00 0x09>;
784 };
785 usb_vbus: adc-channel@0a {
786 reg = <0x00 0x0a>;
787 };
788 die_temp: adc-channel@0b {
789 reg = <0x00 0x0b>;
790 };
791 ref_625mv: adc-channel@0c {
792 reg = <0x00 0x0c>;
793 };
794 ref_1250mv: adc-channel@0d {
795 reg = <0x00 0x0d>;
796 };
797 chg_temp: adc-channel@0e {
798 reg = <0x00 0x0e>;
799 };
800 ref_muxoff: adc-channel@0f {
801 reg = <0x00 0x0f>;
802 };
803 };
804 };
805 };
806
807 qfprom: qfprom@700000 {
808 compatible = "qcom,qfprom";
809 reg = <0x00700000 0x1000>;
810 #address-cells = <1>;
811 #size-cells = <1>;
812 ranges;
813 tsens_calib: calib {
814 reg = <0x404 0x10>;
815 };
816 tsens_backup: backup_calib {
817 reg = <0x414 0x10>;
818 };
819 };
820
821 gcc: clock-controller@900000 {
822 compatible = "qcom,gcc-apq8064";
823 reg = <0x00900000 0x4000>;
824 nvmem-cells = <&tsens_calib>, <&tsens_backup>;
825 nvmem-cell-names = "calib", "calib_backup";
826 #clock-cells = <1>;
827 #reset-cells = <1>;
828 #thermal-sensor-cells = <1>;
829 };
830
831 lcc: clock-controller@28000000 {
832 compatible = "qcom,lcc-apq8064";
833 reg = <0x28000000 0x1000>;
834 #clock-cells = <1>;
835 #reset-cells = <1>;
836 };
837
838 mmcc: clock-controller@4000000 {
839 compatible = "qcom,mmcc-apq8064";
840 reg = <0x4000000 0x1000>;
841 #clock-cells = <1>;
842 #reset-cells = <1>;
843 };
844
845 l2cc: clock-controller@2011000 {
846 compatible = "syscon";
847 reg = <0x2011000 0x1000>;
848 };
849
850 rpm@108000 {
851 compatible = "qcom,rpm-apq8064";
852 reg = <0x108000 0x1000>;
853 qcom,ipc = <&l2cc 0x8 2>;
854
855 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
856 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
857 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
858 interrupt-names = "ack", "err", "wakeup";
859
860 rpmcc: clock-controller {
861 compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc";
862 #clock-cells = <1>;
863 };
864
865 regulators {
866 compatible = "qcom,rpm-pm8921-regulators";
867
868 pm8921_s1: s1 {};
869 pm8921_s2: s2 {};
870 pm8921_s3: s3 {};
871 pm8921_s4: s4 {};
872 pm8921_s7: s7 {};
873 pm8921_s8: s8 {};
874
875 pm8921_l1: l1 {};
876 pm8921_l2: l2 {};
877 pm8921_l3: l3 {};
878 pm8921_l4: l4 {};
879 pm8921_l5: l5 {};
880 pm8921_l6: l6 {};
881 pm8921_l7: l7 {};
882 pm8921_l8: l8 {};
883 pm8921_l9: l9 {};
884 pm8921_l10: l10 {};
885 pm8921_l11: l11 {};
886 pm8921_l12: l12 {};
887 pm8921_l14: l14 {};
888 pm8921_l15: l15 {};
889 pm8921_l16: l16 {};
890 pm8921_l17: l17 {};
891 pm8921_l18: l18 {};
892 pm8921_l21: l21 {};
893 pm8921_l22: l22 {};
894 pm8921_l23: l23 {};
895 pm8921_l24: l24 {};
896 pm8921_l25: l25 {};
897 pm8921_l26: l26 {};
898 pm8921_l27: l27 {};
899 pm8921_l28: l28 {};
900 pm8921_l29: l29 {};
901
902 pm8921_lvs1: lvs1 {};
903 pm8921_lvs2: lvs2 {};
904 pm8921_lvs3: lvs3 {};
905 pm8921_lvs4: lvs4 {};
906 pm8921_lvs5: lvs5 {};
907 pm8921_lvs6: lvs6 {};
908 pm8921_lvs7: lvs7 {};
909
910 pm8921_usb_switch: usb-switch {};
911
912 pm8921_hdmi_switch: hdmi-switch {
913 bias-pull-down;
914 };
915
916 pm8921_ncp: ncp {};
917 };
918 };
919
920 usb1: usb@12500000 {
921 compatible = "qcom,ci-hdrc";
922 reg = <0x12500000 0x200>,
923 <0x12500200 0x200>;
924 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
925 clocks = <&gcc USB_HS1_XCVR_CLK>, <&gcc USB_HS1_H_CLK>;
926 clock-names = "core", "iface";
927 assigned-clocks = <&gcc USB_HS1_XCVR_CLK>;
928 assigned-clock-rates = <60000000>;
929 resets = <&gcc USB_HS1_RESET>;
930 reset-names = "core";
931 phy_type = "ulpi";
932 ahb-burst-config = <0>;
933 phys = <&usb_hs1_phy>;
934 phy-names = "usb-phy";
935 status = "disabled";
936 #reset-cells = <1>;
937
938 ulpi {
939 usb_hs1_phy: phy {
940 compatible = "qcom,usb-hs-phy-apq8064",
941 "qcom,usb-hs-phy";
942 clocks = <&sleep_clk>, <&cxo_board>;
943 clock-names = "sleep", "ref";
944 resets = <&usb1 0>;
945 reset-names = "por";
946 #phy-cells = <0>;
947 };
948 };
949 };
950
951 usb3: usb@12520000 {
952 compatible = "qcom,ci-hdrc";
953 reg = <0x12520000 0x200>,
954 <0x12520200 0x200>;
955 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
956 clocks = <&gcc USB_HS3_XCVR_CLK>, <&gcc USB_HS3_H_CLK>;
957 clock-names = "core", "iface";
958 assigned-clocks = <&gcc USB_HS3_XCVR_CLK>;
959 assigned-clock-rates = <60000000>;
960 resets = <&gcc USB_HS3_RESET>;
961 reset-names = "core";
962 phy_type = "ulpi";
963 ahb-burst-config = <0>;
964 phys = <&usb_hs3_phy>;
965 phy-names = "usb-phy";
966 status = "disabled";
967 #reset-cells = <1>;
968
969 ulpi {
970 usb_hs3_phy: phy {
971 compatible = "qcom,usb-hs-phy-apq8064",
972 "qcom,usb-hs-phy";
973 #phy-cells = <0>;
974 clocks = <&sleep_clk>, <&cxo_board>;
975 clock-names = "sleep", "ref";
976 resets = <&usb3 0>;
977 reset-names = "por";
978 };
979 };
980 };
981
982 usb4: usb@12530000 {
983 compatible = "qcom,ci-hdrc";
984 reg = <0x12530000 0x200>,
985 <0x12530200 0x200>;
986 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
987 clocks = <&gcc USB_HS4_XCVR_CLK>, <&gcc USB_HS4_H_CLK>;
988 clock-names = "core", "iface";
989 assigned-clocks = <&gcc USB_HS4_XCVR_CLK>;
990 assigned-clock-rates = <60000000>;
991 resets = <&gcc USB_HS4_RESET>;
992 reset-names = "core";
993 phy_type = "ulpi";
994 ahb-burst-config = <0>;
995 phys = <&usb_hs4_phy>;
996 phy-names = "usb-phy";
997 status = "disabled";
998 #reset-cells = <1>;
999
1000 ulpi {
1001 usb_hs4_phy: phy {
1002 compatible = "qcom,usb-hs-phy-apq8064",
1003 "qcom,usb-hs-phy";
1004 #phy-cells = <0>;
1005 clocks = <&sleep_clk>, <&cxo_board>;
1006 clock-names = "sleep", "ref";
1007 resets = <&usb4 0>;
1008 reset-names = "por";
1009 };
1010 };
1011 };
1012
1013 sata_phy0: phy@1b400000 {
1014 compatible = "qcom,apq8064-sata-phy";
1015 status = "disabled";
1016 reg = <0x1b400000 0x200>;
1017 reg-names = "phy_mem";
1018 clocks = <&gcc SATA_PHY_CFG_CLK>;
1019 clock-names = "cfg";
1020 #phy-cells = <0>;
1021 };
1022
1023 sata0: sata@29000000 {
1024 compatible = "qcom,apq8064-ahci", "generic-ahci";
1025 status = "disabled";
1026 reg = <0x29000000 0x180>;
1027 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
1028
1029 clocks = <&gcc SFAB_SATA_S_H_CLK>,
1030 <&gcc SATA_H_CLK>,
1031 <&gcc SATA_A_CLK>,
1032 <&gcc SATA_RXOOB_CLK>,
1033 <&gcc SATA_PMALIVE_CLK>;
1034 clock-names = "slave_iface",
1035 "iface",
1036 "bus",
1037 "rxoob",
1038 "core_pmalive";
1039
1040 assigned-clocks = <&gcc SATA_RXOOB_CLK>,
1041 <&gcc SATA_PMALIVE_CLK>;
1042 assigned-clock-rates = <100000000>, <100000000>;
1043
1044 phys = <&sata_phy0>;
1045 phy-names = "sata-phy";
1046 ports-implemented = <0x1>;
1047 };
1048
1049 /* Temporary fixed regulator */
1050 sdcc1bam:dma@12402000{
1051 compatible = "qcom,bam-v1.3.0";
1052 reg = <0x12402000 0x8000>;
1053 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
1054 clocks = <&gcc SDC1_H_CLK>;
1055 clock-names = "bam_clk";
1056 #dma-cells = <1>;
1057 qcom,ee = <0>;
1058 };
1059
1060 sdcc3bam:dma@12182000{
1061 compatible = "qcom,bam-v1.3.0";
1062 reg = <0x12182000 0x8000>;
1063 interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
1064 clocks = <&gcc SDC3_H_CLK>;
1065 clock-names = "bam_clk";
1066 #dma-cells = <1>;
1067 qcom,ee = <0>;
1068 };
1069
1070 sdcc4bam:dma@121c2000{
1071 compatible = "qcom,bam-v1.3.0";
1072 reg = <0x121c2000 0x8000>;
1073 interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
1074 clocks = <&gcc SDC4_H_CLK>;
1075 clock-names = "bam_clk";
1076 #dma-cells = <1>;
1077 qcom,ee = <0>;
1078 };
1079
1080 amba {
1081 compatible = "simple-bus";
1082 #address-cells = <1>;
1083 #size-cells = <1>;
1084 ranges;
1085 sdcc1: sdcc@12400000 {
1086 status = "disabled";
1087 compatible = "arm,pl18x", "arm,primecell";
1088 pinctrl-names = "default";
1089 pinctrl-0 = <&sdcc1_pins>;
1090 arm,primecell-periphid = <0x00051180>;
1091 reg = <0x12400000 0x2000>;
1092 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1093 interrupt-names = "cmd_irq";
1094 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
1095 clock-names = "mclk", "apb_pclk";
1096 bus-width = <8>;
1097 max-frequency = <96000000>;
1098 non-removable;
1099 cap-sd-highspeed;
1100 cap-mmc-highspeed;
1101 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
1102 dma-names = "tx", "rx";
1103 };
1104
1105 sdcc3: sdcc@12180000 {
1106 compatible = "arm,pl18x", "arm,primecell";
1107 arm,primecell-periphid = <0x00051180>;
1108 status = "disabled";
1109 reg = <0x12180000 0x2000>;
1110 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1111 interrupt-names = "cmd_irq";
1112 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
1113 clock-names = "mclk", "apb_pclk";
1114 bus-width = <4>;
1115 cap-sd-highspeed;
1116 cap-mmc-highspeed;
1117 max-frequency = <192000000>;
1118 no-1-8-v;
1119 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
1120 dma-names = "tx", "rx";
1121 };
1122
1123 sdcc4: sdcc@121c0000 {
1124 compatible = "arm,pl18x", "arm,primecell";
1125 arm,primecell-periphid = <0x00051180>;
1126 status = "disabled";
1127 reg = <0x121c0000 0x2000>;
1128 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1129 interrupt-names = "cmd_irq";
1130 clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
1131 clock-names = "mclk", "apb_pclk";
1132 bus-width = <4>;
1133 cap-sd-highspeed;
1134 cap-mmc-highspeed;
1135 max-frequency = <48000000>;
1136 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
1137 dma-names = "tx", "rx";
1138 pinctrl-names = "default";
1139 pinctrl-0 = <&sdc4_gpios>;
1140 };
1141 };
1142
1143 tcsr: syscon@1a400000 {
1144 compatible = "qcom,tcsr-apq8064", "syscon";
1145 reg = <0x1a400000 0x100>;
1146 };
1147
1148 gpu: adreno-3xx@4300000 {
1149 compatible = "qcom,adreno-3xx";
1150 reg = <0x04300000 0x20000>;
1151 reg-names = "kgsl_3d0_reg_memory";
1152 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1153 interrupt-names = "kgsl_3d0_irq";
1154 clock-names =
1155 "core_clk",
1156 "iface_clk",
1157 "mem_clk",
1158 "mem_iface_clk";
1159 clocks =
1160 <&mmcc GFX3D_CLK>,
1161 <&mmcc GFX3D_AHB_CLK>,
1162 <&mmcc GFX3D_AXI_CLK>,
1163 <&mmcc MMSS_IMEM_AHB_CLK>;
1164 qcom,chipid = <0x03020002>;
1165
1166 iommus = <&gfx3d 0
1167 &gfx3d 1
1168 &gfx3d 2
1169 &gfx3d 3
1170 &gfx3d 4
1171 &gfx3d 5
1172 &gfx3d 6
1173 &gfx3d 7
1174 &gfx3d 8
1175 &gfx3d 9
1176 &gfx3d 10
1177 &gfx3d 11
1178 &gfx3d 12
1179 &gfx3d 13
1180 &gfx3d 14
1181 &gfx3d 15
1182 &gfx3d 16
1183 &gfx3d 17
1184 &gfx3d 18
1185 &gfx3d 19
1186 &gfx3d 20
1187 &gfx3d 21
1188 &gfx3d 22
1189 &gfx3d 23
1190 &gfx3d 24
1191 &gfx3d 25
1192 &gfx3d 26
1193 &gfx3d 27
1194 &gfx3d 28
1195 &gfx3d 29
1196 &gfx3d 30
1197 &gfx3d 31
1198 &gfx3d1 0
1199 &gfx3d1 1
1200 &gfx3d1 2
1201 &gfx3d1 3
1202 &gfx3d1 4
1203 &gfx3d1 5
1204 &gfx3d1 6
1205 &gfx3d1 7
1206 &gfx3d1 8
1207 &gfx3d1 9
1208 &gfx3d1 10
1209 &gfx3d1 11
1210 &gfx3d1 12
1211 &gfx3d1 13
1212 &gfx3d1 14
1213 &gfx3d1 15
1214 &gfx3d1 16
1215 &gfx3d1 17
1216 &gfx3d1 18
1217 &gfx3d1 19
1218 &gfx3d1 20
1219 &gfx3d1 21
1220 &gfx3d1 22
1221 &gfx3d1 23
1222 &gfx3d1 24
1223 &gfx3d1 25
1224 &gfx3d1 26
1225 &gfx3d1 27
1226 &gfx3d1 28
1227 &gfx3d1 29
1228 &gfx3d1 30
1229 &gfx3d1 31>;
1230
1231 qcom,gpu-pwrlevels {
1232 compatible = "qcom,gpu-pwrlevels";
1233 qcom,gpu-pwrlevel@0 {
1234 qcom,gpu-freq = <450000000>;
1235 };
1236 qcom,gpu-pwrlevel@1 {
1237 qcom,gpu-freq = <27000000>;
1238 };
1239 };
1240 };
1241
1242 mmss_sfpb: syscon@5700000 {
1243 compatible = "syscon";
1244 reg = <0x5700000 0x70>;
1245 };
1246
1247 dsi0: mdss_dsi@4700000 {
1248 compatible = "qcom,mdss-dsi-ctrl";
1249 label = "MDSS DSI CTRL->0";
1250 #address-cells = <1>;
1251 #size-cells = <0>;
1252 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1253 reg = <0x04700000 0x200>;
1254 reg-names = "dsi_ctrl";
1255
1256 clocks = <&mmcc DSI_M_AHB_CLK>,
1257 <&mmcc DSI_S_AHB_CLK>,
1258 <&mmcc AMP_AHB_CLK>,
1259 <&mmcc DSI_CLK>,
1260 <&mmcc DSI1_BYTE_CLK>,
1261 <&mmcc DSI_PIXEL_CLK>,
1262 <&mmcc DSI1_ESC_CLK>;
1263 clock-names = "iface_clk", "bus_clk", "core_mmss_clk",
1264 "src_clk", "byte_clk", "pixel_clk",
1265 "core_clk";
1266
1267 assigned-clocks = <&mmcc DSI1_BYTE_SRC>,
1268 <&mmcc DSI1_ESC_SRC>,
1269 <&mmcc DSI_SRC>,
1270 <&mmcc DSI_PIXEL_SRC>;
1271 assigned-clock-parents = <&dsi0_phy 0>,
1272 <&dsi0_phy 0>,
1273 <&dsi0_phy 1>,
1274 <&dsi0_phy 1>;
1275 syscon-sfpb = <&mmss_sfpb>;
1276 phys = <&dsi0_phy>;
1277 ports {
1278 #address-cells = <1>;
1279 #size-cells = <0>;
1280
1281 port@0 {
1282 reg = <0>;
1283 dsi0_in: endpoint {
1284 };
1285 };
1286
1287 port@1 {
1288 reg = <1>;
1289 dsi0_out: endpoint {
1290 };
1291 };
1292 };
1293 };
1294
1295
1296 dsi0_phy: dsi-phy@4700200 {
1297 compatible = "qcom,dsi-phy-28nm-8960";
1298 #clock-cells = <1>;
1299 #phy-cells = <0>;
1300
1301 reg = <0x04700200 0x100>,
1302 <0x04700300 0x200>,
1303 <0x04700500 0x5c>;
1304 reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator";
1305 clock-names = "iface_clk";
1306 clocks = <&mmcc DSI_M_AHB_CLK>;
1307 };
1308
1309
1310 mdp_port0: iommu@7500000 {
1311 compatible = "qcom,apq8064-iommu";
1312 #iommu-cells = <1>;
1313 clock-names =
1314 "smmu_pclk",
1315 "iommu_clk";
1316 clocks =
1317 <&mmcc SMMU_AHB_CLK>,
1318 <&mmcc MDP_AXI_CLK>;
1319 reg = <0x07500000 0x100000>;
1320 interrupts =
1321 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
1322 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
1323 qcom,ncb = <2>;
1324 };
1325
1326 mdp_port1: iommu@7600000 {
1327 compatible = "qcom,apq8064-iommu";
1328 #iommu-cells = <1>;
1329 clock-names =
1330 "smmu_pclk",
1331 "iommu_clk";
1332 clocks =
1333 <&mmcc SMMU_AHB_CLK>,
1334 <&mmcc MDP_AXI_CLK>;
1335 reg = <0x07600000 0x100000>;
1336 interrupts =
1337 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
1338 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1339 qcom,ncb = <2>;
1340 };
1341
1342 gfx3d: iommu@7c00000 {
1343 compatible = "qcom,apq8064-iommu";
1344 #iommu-cells = <1>;
1345 clock-names =
1346 "smmu_pclk",
1347 "iommu_clk";
1348 clocks =
1349 <&mmcc SMMU_AHB_CLK>,
1350 <&mmcc GFX3D_AXI_CLK>;
1351 reg = <0x07c00000 0x100000>;
1352 interrupts =
1353 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
1354 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1355 qcom,ncb = <3>;
1356 };
1357
1358 gfx3d1: iommu@7d00000 {
1359 compatible = "qcom,apq8064-iommu";
1360 #iommu-cells = <1>;
1361 clock-names =
1362 "smmu_pclk",
1363 "iommu_clk";
1364 clocks =
1365 <&mmcc SMMU_AHB_CLK>,
1366 <&mmcc GFX3D_AXI_CLK>;
1367 reg = <0x07d00000 0x100000>;
1368 interrupts =
1369 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
1370 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
1371 qcom,ncb = <3>;
1372 };
1373
1374 pcie: pci@1b500000 {
1375 compatible = "qcom,pcie-apq8064", "snps,dw-pcie";
1376 reg = <0x1b500000 0x1000
1377 0x1b502000 0x80
1378 0x1b600000 0x100
1379 0x0ff00000 0x100000>;
1380 reg-names = "dbi", "elbi", "parf", "config";
1381 device_type = "pci";
1382 linux,pci-domain = <0>;
1383 bus-range = <0x00 0xff>;
1384 num-lanes = <1>;
1385 #address-cells = <3>;
1386 #size-cells = <2>;
1387 ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* I/O */
1388 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* memory */
1389 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
1390 interrupt-names = "msi";
1391 #interrupt-cells = <1>;
1392 interrupt-map-mask = <0 0 0 0x7>;
1393 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1394 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1395 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1396 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1397 clocks = <&gcc PCIE_A_CLK>,
1398 <&gcc PCIE_H_CLK>,
1399 <&gcc PCIE_PHY_REF_CLK>;
1400 clock-names = "core", "iface", "phy";
1401 resets = <&gcc PCIE_ACLK_RESET>,
1402 <&gcc PCIE_HCLK_RESET>,
1403 <&gcc PCIE_POR_RESET>,
1404 <&gcc PCIE_PCI_RESET>,
1405 <&gcc PCIE_PHY_RESET>;
1406 reset-names = "axi", "ahb", "por", "pci", "phy";
1407 status = "disabled";
1408 };
1409
1410 hdmi: hdmi-tx@4a00000 {
1411 compatible = "qcom,hdmi-tx-8960";
1412 pinctrl-names = "default";
1413 pinctrl-0 = <&hdmi_pinctrl>;
1414 reg = <0x04a00000 0x2f0>;
1415 reg-names = "core_physical";
1416 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1417 clocks = <&mmcc HDMI_APP_CLK>,
1418 <&mmcc HDMI_M_AHB_CLK>,
1419 <&mmcc HDMI_S_AHB_CLK>;
1420 clock-names = "core_clk",
1421 "master_iface_clk",
1422 "slave_iface_clk";
1423
1424 phys = <&hdmi_phy>;
1425 phy-names = "hdmi-phy";
1426
1427 ports {
1428 #address-cells = <1>;
1429 #size-cells = <0>;
1430
1431 port@0 {
1432 reg = <0>;
1433 hdmi_in: endpoint {
1434 };
1435 };
1436
1437 port@1 {
1438 reg = <1>;
1439 hdmi_out: endpoint {
1440 };
1441 };
1442 };
1443 };
1444
1445 hdmi_phy: hdmi-phy@4a00400 {
1446 compatible = "qcom,hdmi-phy-8960";
1447 reg = <0x4a00400 0x60>,
1448 <0x4a00500 0x100>;
1449 reg-names = "hdmi_phy",
1450 "hdmi_pll";
1451
1452 clocks = <&mmcc HDMI_S_AHB_CLK>;
1453 clock-names = "slave_iface_clk";
1454 #phy-cells = <0>;
1455 };
1456
1457 mdp: mdp@5100000 {
1458 compatible = "qcom,mdp4";
1459 reg = <0x05100000 0xf0000>;
1460 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1461 clocks = <&mmcc MDP_CLK>,
1462 <&mmcc MDP_AHB_CLK>,
1463 <&mmcc MDP_AXI_CLK>,
1464 <&mmcc MDP_LUT_CLK>,
1465 <&mmcc HDMI_TV_CLK>,
1466 <&mmcc MDP_TV_CLK>;
1467 clock-names = "core_clk",
1468 "iface_clk",
1469 "bus_clk",
1470 "lut_clk",
1471 "hdmi_clk",
1472 "tv_clk";
1473
1474 iommus = <&mdp_port0 0
1475 &mdp_port0 2
1476 &mdp_port1 0
1477 &mdp_port1 2>;
1478
1479 ports {
1480 #address-cells = <1>;
1481 #size-cells = <0>;
1482
1483 port@0 {
1484 reg = <0>;
1485 mdp_lvds_out: endpoint {
1486 };
1487 };
1488
1489 port@1 {
1490 reg = <1>;
1491 mdp_dsi1_out: endpoint {
1492 };
1493 };
1494
1495 port@2 {
1496 reg = <2>;
1497 mdp_dsi2_out: endpoint {
1498 };
1499 };
1500
1501 port@3 {
1502 reg = <3>;
1503 mdp_dtv_out: endpoint {
1504 };
1505 };
1506 };
1507 };
1508
1509 riva: riva-pil@3204000 {
1510 compatible = "qcom,riva-pil";
1511
1512 reg = <0x03200800 0x1000>, <0x03202000 0x2000>, <0x03204000 0x100>;
1513 reg-names = "ccu", "dxe", "pmu";
1514
1515 interrupts-extended = <&intc GIC_SPI 199 IRQ_TYPE_EDGE_RISING>,
1516 <&wcnss_smsm 6 IRQ_TYPE_EDGE_RISING>;
1517 interrupt-names = "wdog", "fatal";
1518
1519 memory-region = <&wcnss_mem>;
1520
1521 vddcx-supply = <&pm8921_s3>;
1522 vddmx-supply = <&pm8921_l24>;
1523 vddpx-supply = <&pm8921_s4>;
1524
1525 status = "disabled";
1526
1527 iris {
1528 compatible = "qcom,wcn3660";
1529
1530 clocks = <&cxo_board>;
1531 clock-names = "xo";
1532
1533 vddxo-supply = <&pm8921_l4>;
1534 vddrfa-supply = <&pm8921_s2>;
1535 vddpa-supply = <&pm8921_l10>;
1536 vdddig-supply = <&pm8921_lvs2>;
1537 };
1538
1539 smd-edge {
1540 interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>;
1541
1542 qcom,ipc = <&l2cc 8 25>;
1543 qcom,smd-edge = <6>;
1544
1545 label = "riva";
1546
1547 wcnss {
1548 compatible = "qcom,wcnss";
1549 qcom,smd-channels = "WCNSS_CTRL";
1550
1551 qcom,mmio = <&riva>;
1552
1553 bt {
1554 compatible = "qcom,wcnss-bt";
1555 };
1556
1557 wifi {
1558 compatible = "qcom,wcnss-wlan";
1559
1560 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
1561 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
1562 interrupt-names = "tx", "rx";
1563
1564 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
1565 qcom,smem-state-names = "tx-enable", "tx-rings-empty";
1566 };
1567 };
1568 };
1569 };
1570
1571 etb@1a01000 {
1572 compatible = "coresight-etb10", "arm,primecell";
1573 reg = <0x1a01000 0x1000>;
1574
1575 clocks = <&rpmcc RPM_QDSS_CLK>;
1576 clock-names = "apb_pclk";
1577
1578 in-ports {
1579 port {
1580 etb_in: endpoint {
1581 remote-endpoint = <&replicator_out0>;
1582 };
1583 };
1584 };
1585 };
1586
1587 tpiu@1a03000 {
1588 compatible = "arm,coresight-tpiu", "arm,primecell";
1589 reg = <0x1a03000 0x1000>;
1590
1591 clocks = <&rpmcc RPM_QDSS_CLK>;
1592 clock-names = "apb_pclk";
1593
1594 in-ports {
1595 port {
1596 tpiu_in: endpoint {
1597 remote-endpoint = <&replicator_out1>;
1598 };
1599 };
1600 };
1601 };
1602
1603 replicator {
1604 compatible = "arm,coresight-replicator";
1605
1606 clocks = <&rpmcc RPM_QDSS_CLK>;
1607 clock-names = "apb_pclk";
1608
1609 out-ports {
1610 #address-cells = <1>;
1611 #size-cells = <0>;
1612
1613 port@0 {
1614 reg = <0>;
1615 replicator_out0: endpoint {
1616 remote-endpoint = <&etb_in>;
1617 };
1618 };
1619 port@1 {
1620 reg = <1>;
1621 replicator_out1: endpoint {
1622 remote-endpoint = <&tpiu_in>;
1623 };
1624 };
1625 };
1626
1627 in-ports {
1628 port {
1629 replicator_in: endpoint {
1630 remote-endpoint = <&funnel_out>;
1631 };
1632 };
1633 };
1634 };
1635
1636 funnel@1a04000 {
1637 compatible = "arm,coresight-funnel", "arm,primecell";
1638 reg = <0x1a04000 0x1000>;
1639
1640 clocks = <&rpmcc RPM_QDSS_CLK>;
1641 clock-names = "apb_pclk";
1642
1643 in-ports {
1644 #address-cells = <1>;
1645 #size-cells = <0>;
1646
1647 /*
1648 * Not described input ports:
1649 * 2 - connected to STM component
1650 * 3 - not-connected
1651 * 6 - not-connected
1652 * 7 - not-connected
1653 */
1654 port@0 {
1655 reg = <0>;
1656 funnel_in0: endpoint {
1657 remote-endpoint = <&etm0_out>;
1658 };
1659 };
1660 port@1 {
1661 reg = <1>;
1662 funnel_in1: endpoint {
1663 remote-endpoint = <&etm1_out>;
1664 };
1665 };
1666 port@4 {
1667 reg = <4>;
1668 funnel_in4: endpoint {
1669 remote-endpoint = <&etm2_out>;
1670 };
1671 };
1672 port@5 {
1673 reg = <5>;
1674 funnel_in5: endpoint {
1675 remote-endpoint = <&etm3_out>;
1676 };
1677 };
1678 };
1679
1680 out-ports {
1681 port {
1682 funnel_out: endpoint {
1683 remote-endpoint = <&replicator_in>;
1684 };
1685 };
1686 };
1687 };
1688
1689 etm@1a1c000 {
1690 compatible = "arm,coresight-etm3x", "arm,primecell";
1691 reg = <0x1a1c000 0x1000>;
1692
1693 clocks = <&rpmcc RPM_QDSS_CLK>;
1694 clock-names = "apb_pclk";
1695
1696 cpu = <&CPU0>;
1697
1698 out-ports {
1699 port {
1700 etm0_out: endpoint {
1701 remote-endpoint = <&funnel_in0>;
1702 };
1703 };
1704 };
1705 };
1706
1707 etm@1a1d000 {
1708 compatible = "arm,coresight-etm3x", "arm,primecell";
1709 reg = <0x1a1d000 0x1000>;
1710
1711 clocks = <&rpmcc RPM_QDSS_CLK>;
1712 clock-names = "apb_pclk";
1713
1714 cpu = <&CPU1>;
1715
1716 out-ports {
1717 port {
1718 etm1_out: endpoint {
1719 remote-endpoint = <&funnel_in1>;
1720 };
1721 };
1722 };
1723 };
1724
1725 etm@1a1e000 {
1726 compatible = "arm,coresight-etm3x", "arm,primecell";
1727 reg = <0x1a1e000 0x1000>;
1728
1729 clocks = <&rpmcc RPM_QDSS_CLK>;
1730 clock-names = "apb_pclk";
1731
1732 cpu = <&CPU2>;
1733
1734 out-ports {
1735 port {
1736 etm2_out: endpoint {
1737 remote-endpoint = <&funnel_in4>;
1738 };
1739 };
1740 };
1741 };
1742
1743 etm@1a1f000 {
1744 compatible = "arm,coresight-etm3x", "arm,primecell";
1745 reg = <0x1a1f000 0x1000>;
1746
1747 clocks = <&rpmcc RPM_QDSS_CLK>;
1748 clock-names = "apb_pclk";
1749
1750 cpu = <&CPU3>;
1751
1752 out-ports {
1753 port {
1754 etm3_out: endpoint {
1755 remote-endpoint = <&funnel_in5>;
1756 };
1757 };
1758 };
1759 };
1760 };
1761 };
1762 #include "qcom-apq8064-pins.dtsi"
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