arch/arm/boot/dts/qcom-ipq4019.dtsi

   1 /*
   2  * Copyright (c) 2015, The Linux Foundation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 and
   6  * only version 2 as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 /dts-v1/;
  15
  16 #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
  17 #include <dt-bindings/interrupt-controller/arm-gic.h>
  18 #include <dt-bindings/interrupt-controller/irq.h>
  19
  20 / {
  21         #address-cells = <1>;
  22         #size-cells = <1>;
  23
  24         model = "Qualcomm Technologies, Inc. IPQ4019";
  25         compatible = "qcom,ipq4019";
  26         interrupt-parent = <&intc>;
  27
  28         reserved-memory {
  29                 #address-cells = <0x1>;
  30                 #size-cells = <0x1>;
  31                 ranges;
  32
  33                 smem_region: smem@87e00000 {
  34                         reg = <0x87e00000 0x080000>;
  35                         no-map;
  36                 };
  37
  38                 tz@87e80000 {
  39                         reg = <0x87e80000 0x180000>;
  40                         no-map;
  41                 };
  42         };
  43
  44         aliases {
  45                 spi0 = &blsp1_spi1;
  46                 spi1 = &blsp1_spi2;
  47                 i2c0 = &blsp1_i2c3;
  48                 i2c1 = &blsp1_i2c4;
  49         };
  50
  51         cpus {
  52                 #address-cells = <1>;
  53                 #size-cells = <0>;
  54                 cpu@0 {
  55                         device_type = "cpu";
  56                         compatible = "arm,cortex-a7";
  57                         enable-method = "qcom,kpss-acc-v2";
  58                         next-level-cache = <&L2>;
  59                         qcom,acc = <&acc0>;
  60                         qcom,saw = <&saw0>;
  61                         reg = <0x0>;
  62                         clocks = <&gcc GCC_APPS_CLK_SRC>;
  63                         clock-frequency = <0>;
  64                         clock-latency = <256000>;
  65                         operating-points-v2 = <&cpu0_opp_table>;
  66                 };
  67
  68                 cpu@1 {
  69                         device_type = "cpu";
  70                         compatible = "arm,cortex-a7";
  71                         enable-method = "qcom,kpss-acc-v2";
  72                         next-level-cache = <&L2>;
  73                         qcom,acc = <&acc1>;
  74                         qcom,saw = <&saw1>;
  75                         reg = <0x1>;
  76                         clocks = <&gcc GCC_APPS_CLK_SRC>;
  77                         clock-frequency = <0>;
  78                         clock-latency = <256000>;
  79                         operating-points-v2 = <&cpu0_opp_table>;
  80                 };
  81
  82                 cpu@2 {
  83                         device_type = "cpu";
  84                         compatible = "arm,cortex-a7";
  85                         enable-method = "qcom,kpss-acc-v2";
  86                         next-level-cache = <&L2>;
  87                         qcom,acc = <&acc2>;
  88                         qcom,saw = <&saw2>;
  89                         reg = <0x2>;
  90                         clocks = <&gcc GCC_APPS_CLK_SRC>;
  91                         clock-frequency = <0>;
  92                         clock-latency = <256000>;
  93                         operating-points-v2 = <&cpu0_opp_table>;
  94                 };
  95
  96                 cpu@3 {
  97                         device_type = "cpu";
  98                         compatible = "arm,cortex-a7";
  99                         enable-method = "qcom,kpss-acc-v2";
 100                         next-level-cache = <&L2>;
 101                         qcom,acc = <&acc3>;
 102                         qcom,saw = <&saw3>;
 103                         reg = <0x3>;
 104                         clocks = <&gcc GCC_APPS_CLK_SRC>;
 105                         clock-frequency = <0>;
 106                         clock-latency = <256000>;
 107                         operating-points-v2 = <&cpu0_opp_table>;
 108                 };
 109
 110                 L2: l2-cache {
 111                         compatible = "cache";
 112                         cache-level = <2>;
 113                 };
 114         };
 115
 116         cpu0_opp_table: opp_table0 {
 117                 compatible = "operating-points-v2";
 118                 opp-shared;
 119
 120                 opp-48000000 {
 121                         opp-hz = /bits/ 64 <48000000>;
 122                         clock-latency-ns = <256000>;
 123                 };
 124                 opp-200000000 {
 125                         opp-hz = /bits/ 64 <200000000>;
 126                         clock-latency-ns = <256000>;
 127                 };
 128                 opp-500000000 {
 129                         opp-hz = /bits/ 64 <500000000>;
 130                         clock-latency-ns = <256000>;
 131                 };
 132                 opp-716000000 {
 133                         opp-hz = /bits/ 64 <716000000>;
 134                         clock-latency-ns = <256000>;
 135                 };
 136         };
 137
 138         memory {
 139                 device_type = "memory";
 140                 reg = <0x0 0x0>;
 141         };
 142
 143         pmu {
 144                 compatible = "arm,cortex-a7-pmu";
 145                 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
 146                                          IRQ_TYPE_LEVEL_HIGH)>;
 147         };
 148
 149         clocks {
 150                 sleep_clk: sleep_clk {
 151                         compatible = "fixed-clock";
 152                         clock-frequency = <32768>;
 153                         #clock-cells = <0>;
 154                 };
 155
 156                 xo: xo {
 157                         compatible = "fixed-clock";
 158                         clock-frequency = <48000000>;
 159                         #clock-cells = <0>;
 160                 };
 161         };
 162
 163         firmware {
 164                 scm {
 165                         compatible = "qcom,scm-ipq4019";
 166                 };
 167         };
 168
 169         timer {
 170                 compatible = "arm,armv7-timer";
 171                 interrupts = <1 2 0xf08>,
 172                              <1 3 0xf08>,
 173                              <1 4 0xf08>,
 174                              <1 1 0xf08>;
 175                 clock-frequency = <48000000>;
 176         };
 177
 178         soc {
 179                 #address-cells = <1>;
 180                 #size-cells = <1>;
 181                 ranges;
 182                 compatible = "simple-bus";
 183
 184                 intc: interrupt-controller@b000000 {
 185                         compatible = "qcom,msm-qgic2";
 186                         interrupt-controller;
 187                         #interrupt-cells = <3>;
 188                         reg = <0x0b000000 0x1000>,
 189                         <0x0b002000 0x1000>;
 190                 };
 191
 192                 gcc: clock-controller@1800000 {
 193                         compatible = "qcom,gcc-ipq4019";
 194                         #clock-cells = <1>;
 195                         #reset-cells = <1>;
 196                         reg = <0x1800000 0x60000>;
 197                 };
 198
 199                 rng@22000 {
 200                         compatible = "qcom,prng";
 201                         reg = <0x22000 0x140>;
 202                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 203                         clock-names = "core";
 204                         status = "disabled";
 205                 };
 206
 207                 tlmm: pinctrl@1000000 {
 208                         compatible = "qcom,ipq4019-pinctrl";
 209                         reg = <0x01000000 0x300000>;
 210                         gpio-controller;
 211                         #gpio-cells = <2>;
 212                         interrupt-controller;
 213                         #interrupt-cells = <2>;
 214                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 215                 };
 216
 217                 blsp_dma: dma@7884000 {
 218                         compatible = "qcom,bam-v1.7.0";
 219                         reg = <0x07884000 0x23000>;
 220                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
 221                         clocks = <&gcc GCC_BLSP1_AHB_CLK>;
 222                         clock-names = "bam_clk";
 223                         #dma-cells = <1>;
 224                         qcom,ee = <0>;
 225                         status = "disabled";
 226                 };
 227
 228                 blsp1_spi1: spi@78b5000 { /* BLSP1 QUP1 */
 229                         compatible = "qcom,spi-qup-v2.2.1";
 230                         reg = <0x78b5000 0x600>;
 231                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 232                         clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
 233                                  <&gcc GCC_BLSP1_AHB_CLK>;
 234                         clock-names = "core", "iface";
 235                         #address-cells = <1>;
 236                         #size-cells = <0>;
 237                         dmas = <&blsp_dma 5>, <&blsp_dma 4>;
 238                         dma-names = "rx", "tx";
 239                         status = "disabled";
 240                 };
 241
 242                 blsp1_spi2: spi@78b6000 { /* BLSP1 QUP2 */
 243                         compatible = "qcom,spi-qup-v2.2.1";
 244                         reg = <0x78b6000 0x600>;
 245                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 246                         clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
 247                                 <&gcc GCC_BLSP1_AHB_CLK>;
 248                         clock-names = "core", "iface";
 249                         #address-cells = <1>;
 250                         #size-cells = <0>;
 251                         dmas = <&blsp_dma 7>, <&blsp_dma 6>;
 252                         dma-names = "rx", "tx";
 253                         status = "disabled";
 254                 };
 255
 256                 blsp1_i2c3: i2c@78b7000 { /* BLSP1 QUP3 */
 257                         compatible = "qcom,i2c-qup-v2.2.1";
 258                         reg = <0x78b7000 0x600>;
 259                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 260                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 261                                  <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
 262                         clock-names = "iface", "core";
 263                         #address-cells = <1>;
 264                         #size-cells = <0>;
 265                         dmas = <&blsp_dma 9>, <&blsp_dma 8>;
 266                         dma-names = "rx", "tx";
 267                         status = "disabled";
 268                 };
 269
 270                 blsp1_i2c4: i2c@78b8000 { /* BLSP1 QUP4 */
 271                         compatible = "qcom,i2c-qup-v2.2.1";
 272                         reg = <0x78b8000 0x600>;
 273                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 274                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 275                                  <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
 276                         clock-names = "iface", "core";
 277                         #address-cells = <1>;
 278                         #size-cells = <0>;
 279                         dmas = <&blsp_dma 11>, <&blsp_dma 10>;
 280                         dma-names = "rx", "tx";
 281                         status = "disabled";
 282                 };
 283
 284                 cryptobam: dma@8e04000 {
 285                         compatible = "qcom,bam-v1.7.0";
 286                         reg = <0x08e04000 0x20000>;
 287                         interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
 288                         clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
 289                         clock-names = "bam_clk";
 290                         #dma-cells = <1>;
 291                         qcom,ee = <1>;
 292                         qcom,controlled-remotely;
 293                         status = "disabled";
 294                 };
 295
 296                 crypto@8e3a000 {
 297                         compatible = "qcom,crypto-v5.1";
 298                         reg = <0x08e3a000 0x6000>;
 299                         clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
 300                                  <&gcc GCC_CRYPTO_AXI_CLK>,
 301                                  <&gcc GCC_CRYPTO_CLK>;
 302                         clock-names = "iface", "bus", "core";
 303                         dmas = <&cryptobam 2>, <&cryptobam 3>;
 304                         dma-names = "rx", "tx";
 305                         status = "disabled";
 306                 };
 307
 308                 acc0: clock-controller@b088000 {
 309                         compatible = "qcom,kpss-acc-v2";
 310                         reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
 311                 };
 312
 313                 acc1: clock-controller@b098000 {
 314                         compatible = "qcom,kpss-acc-v2";
 315                         reg = <0x0b098000 0x1000>, <0xb008000 0x1000>;
 316                 };
 317
 318                 acc2: clock-controller@b0a8000 {
 319                         compatible = "qcom,kpss-acc-v2";
 320                         reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>;
 321                 };
 322
 323                 acc3: clock-controller@b0b8000 {
 324                         compatible = "qcom,kpss-acc-v2";
 325                         reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
 326                 };
 327
 328                 saw0: regulator@b089000 {
 329                         compatible = "qcom,saw2";
 330                         reg = <0x0b089000 0x1000>, <0x0b009000 0x1000>;
 331                         regulator;
 332                 };
 333
 334                 saw1: regulator@b099000 {
 335                         compatible = "qcom,saw2";
 336                         reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>;
 337                         regulator;
 338                 };
 339
 340                 saw2: regulator@b0a9000 {
 341                         compatible = "qcom,saw2";
 342                         reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>;
 343                         regulator;
 344                 };
 345
 346                 saw3: regulator@b0b9000 {
 347                         compatible = "qcom,saw2";
 348                         reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>;
 349                         regulator;
 350                 };
 351
 352                 blsp1_uart1: serial@78af000 {
 353                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 354                         reg = <0x78af000 0x200>;
 355                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 356                         status = "disabled";
 357                         clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
 358                                 <&gcc GCC_BLSP1_AHB_CLK>;
 359                         clock-names = "core", "iface";
 360                         dmas = <&blsp_dma 1>, <&blsp_dma 0>;
 361                         dma-names = "rx", "tx";
 362                 };
 363
 364                 blsp1_uart2: serial@78b0000 {
 365                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 366                         reg = <0x78b0000 0x200>;
 367                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 368                         status = "disabled";
 369                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
 370                                 <&gcc GCC_BLSP1_AHB_CLK>;
 371                         clock-names = "core", "iface";
 372                         dmas = <&blsp_dma 3>, <&blsp_dma 2>;
 373                         dma-names = "rx", "tx";
 374                 };
 375
 376                 watchdog@b017000 {
 377                         compatible = "qcom,kpss-wdt", "qcom,kpss-wdt-ipq4019";
 378                         reg = <0xb017000 0x40>;
 379                         clocks = <&sleep_clk>;
 380                         timeout-sec = <10>;
 381                         status = "disabled";
 382                 };
 383
 384                 restart@4ab000 {
 385                         compatible = "qcom,pshold";
 386                         reg = <0x4ab000 0x4>;
 387                 };
 388
 389                 pcie0: pci@40000000 {
 390                         compatible = "qcom,pcie-ipq4019", "snps,dw-pcie";
 391                         reg =  <0x40000000 0xf1d
 392                                 0x40000f20 0xa8
 393                                 0x80000 0x2000
 394                                 0x40100000 0x1000>;
 395                         reg-names = "dbi", "elbi", "parf", "config";
 396                         device_type = "pci";
 397                         linux,pci-domain = <0>;
 398                         bus-range = <0x00 0xff>;
 399                         num-lanes = <1>;
 400                         #address-cells = <3>;
 401                         #size-cells = <2>;
 402
 403                         ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000
 404                                   0x82000000 0 0x40300000 0x40300000 0 0x400000>;
 405
 406                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
 407                         interrupt-names = "msi";
 408                         #interrupt-cells = <1>;
 409                         interrupt-map-mask = <0 0 0 0x7>;
 410                         interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 411                                         <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 412                                         <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 413                                         <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 414                         clocks = <&gcc GCC_PCIE_AHB_CLK>,
 415                                  <&gcc GCC_PCIE_AXI_M_CLK>,
 416                                  <&gcc GCC_PCIE_AXI_S_CLK>;
 417                         clock-names = "aux",
 418                                       "master_bus",
 419                                       "slave_bus";
 420
 421                         resets = <&gcc PCIE_AXI_M_ARES>,
 422                                  <&gcc PCIE_AXI_S_ARES>,
 423                                  <&gcc PCIE_PIPE_ARES>,
 424                                  <&gcc PCIE_AXI_M_VMIDMT_ARES>,
 425                                  <&gcc PCIE_AXI_S_XPU_ARES>,
 426                                  <&gcc PCIE_PARF_XPU_ARES>,
 427                                  <&gcc PCIE_PHY_ARES>,
 428                                  <&gcc PCIE_AXI_M_STICKY_ARES>,
 429                                  <&gcc PCIE_PIPE_STICKY_ARES>,
 430                                  <&gcc PCIE_PWR_ARES>,
 431                                  <&gcc PCIE_AHB_ARES>,
 432                                  <&gcc PCIE_PHY_AHB_ARES>;
 433                         reset-names = "axi_m",
 434                                       "axi_s",
 435                                       "pipe",
 436                                       "axi_m_vmid",
 437                                       "axi_s_xpu",
 438                                       "parf",
 439                                       "phy",
 440                                       "axi_m_sticky",
 441                                       "pipe_sticky",
 442                                       "pwr",
 443                                       "ahb",
 444                                       "phy_ahb";
 445
 446                         status = "disabled";
 447                 };
 448
 449                 qpic_bam: dma@7984000 {
 450                         compatible = "qcom,bam-v1.7.0";
 451                         reg = <0x7984000 0x1a000>;
 452                         interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 453                         clocks = <&gcc GCC_QPIC_CLK>;
 454                         clock-names = "bam_clk";
 455                         #dma-cells = <1>;
 456                         qcom,ee = <0>;
 457                         status = "disabled";
 458                 };
 459
 460                 nand: qpic-nand@79b0000 {
 461                         compatible = "qcom,ipq4019-nand";
 462                         reg = <0x79b0000 0x1000>;
 463                         #address-cells = <1>;
 464                         #size-cells = <0>;
 465                         clocks = <&gcc GCC_QPIC_CLK>,
 466                                  <&gcc GCC_QPIC_AHB_CLK>;
 467                         clock-names = "core", "aon";
 468
 469                         dmas = <&qpic_bam 0>,
 470                                <&qpic_bam 1>,
 471                                <&qpic_bam 2>;
 472                         dma-names = "tx", "rx", "cmd";
 473                         status = "disabled";
 474
 475                         nand@0 {
 476                                 reg = <0>;
 477
 478                                 nand-ecc-strength = <4>;
 479                                 nand-ecc-step-size = <512>;
 480                                 nand-bus-width = <8>;
 481                         };
 482                 };
 483
 484                 wifi0: wifi@a000000 {
 485                         compatible = "qcom,ipq4019-wifi";
 486                         reg = <0xa000000 0x200000>;
 487                         resets = <&gcc WIFI0_CPU_INIT_RESET>,
 488                                  <&gcc WIFI0_RADIO_SRIF_RESET>,
 489                                  <&gcc WIFI0_RADIO_WARM_RESET>,
 490                                  <&gcc WIFI0_RADIO_COLD_RESET>,
 491                                  <&gcc WIFI0_CORE_WARM_RESET>,
 492                                  <&gcc WIFI0_CORE_COLD_RESET>;
 493                         reset-names = "wifi_cpu_init", "wifi_radio_srif",
 494                                       "wifi_radio_warm", "wifi_radio_cold",
 495                                       "wifi_core_warm", "wifi_core_cold";
 496                         clocks = <&gcc GCC_WCSS2G_CLK>,
 497                                  <&gcc GCC_WCSS2G_REF_CLK>,
 498                                  <&gcc GCC_WCSS2G_RTC_CLK>;
 499                         clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
 500                                       "wifi_wcss_rtc";
 501                         interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
 502                                      <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
 503                                      <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
 504                                      <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
 505                                      <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
 506                                      <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
 507                                      <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>,
 508                                      <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>,
 509                                      <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>,
 510                                      <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>,
 511                                      <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>,
 512                                      <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>,
 513                                      <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>,
 514                                      <GIC_SPI 45 IRQ_TYPE_EDGE_RISING>,
 515                                      <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>,
 516                                      <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>,
 517                                      <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
 518                         interrupt-names =  "msi0",  "msi1",  "msi2",  "msi3",
 519                                            "msi4",  "msi5",  "msi6",  "msi7",
 520                                            "msi8",  "msi9", "msi10", "msi11",
 521                                           "msi12", "msi13", "msi14", "msi15",
 522                                           "legacy";
 523                         status = "disabled";
 524                 };
 525
 526                 wifi1: wifi@a800000 {
 527                         compatible = "qcom,ipq4019-wifi";
 528                         reg = <0xa800000 0x200000>;
 529                         resets = <&gcc WIFI1_CPU_INIT_RESET>,
 530                                  <&gcc WIFI1_RADIO_SRIF_RESET>,
 531                                  <&gcc WIFI1_RADIO_WARM_RESET>,
 532                                  <&gcc WIFI1_RADIO_COLD_RESET>,
 533                                  <&gcc WIFI1_CORE_WARM_RESET>,
 534                                  <&gcc WIFI1_CORE_COLD_RESET>;
 535                         reset-names = "wifi_cpu_init", "wifi_radio_srif",
 536                                       "wifi_radio_warm", "wifi_radio_cold",
 537                                       "wifi_core_warm", "wifi_core_cold";
 538                         clocks = <&gcc GCC_WCSS5G_CLK>,
 539                                  <&gcc GCC_WCSS5G_REF_CLK>,
 540                                  <&gcc GCC_WCSS5G_RTC_CLK>;
 541                         clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
 542                                       "wifi_wcss_rtc";
 543                         interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>,
 544                                      <GIC_SPI 49 IRQ_TYPE_EDGE_RISING>,
 545                                      <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>,
 546                                      <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
 547                                      <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
 548                                      <GIC_SPI 53 IRQ_TYPE_EDGE_RISING>,
 549                                      <GIC_SPI 54 IRQ_TYPE_EDGE_RISING>,
 550                                      <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
 551                                      <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>,
 552                                      <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>,
 553                                      <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>,
 554                                      <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>,
 555                                      <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>,
 556                                      <GIC_SPI 61 IRQ_TYPE_EDGE_RISING>,
 557                                      <GIC_SPI 62 IRQ_TYPE_EDGE_RISING>,
 558                                      <GIC_SPI 63 IRQ_TYPE_EDGE_RISING>,
 559                                      <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
 560                         interrupt-names =  "msi0",  "msi1",  "msi2",  "msi3",
 561                                            "msi4",  "msi5",  "msi6",  "msi7",
 562                                            "msi8",  "msi9", "msi10", "msi11",
 563                                           "msi12", "msi13", "msi14", "msi15",
 564                                           "legacy";
 565                         status = "disabled";
 566                 };
 567         };
 568 };