arch/arm/boot/dts/qcom-mdm9615-wp8548.dtsi

   1 /*
   2  * Device Tree Source for Sierra Wireless WP8548 Module
   3  *
   4  * Copyright (C) 2016 BayLibre, SAS.
   5  * Author : Neil Armstrong <narmstrong@baylibre.com>
   6  *
   7  * This file is dual-licensed: you can use it either under the terms
   8  * of the GPL or the X11 license, at your option. Note that this dual
   9  * licensing only applies to this file, and not this project as a
  10  * whole.
  11  *
  12  *  a) This file is free software; you can redistribute it and/or
  13  *     modify it under the terms of the GNU General Public License as
  14  *     published by the Free Software Foundation; either version 2 of the
  15  *     License, or (at your option) any later version.
  16  *
  17  *     This file is distributed in the hope that it will be useful,
  18  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  *     GNU General Public License for more details.
  21  *
  22  * Or, alternatively,
  23  *
  24  *  b) Permission is hereby granted, free of charge, to any person
  25  *     obtaining a copy of this software and associated documentation
  26  *     files (the "Software"), to deal in the Software without
  27  *     restriction, including without limitation the rights to use,
  28  *     copy, modify, merge, publish, distribute, sublicense, and/or
  29  *     sell copies of the Software, and to permit persons to whom the
  30  *     Software is furnished to do so, subject to the following
  31  *     conditions:
  32  *
  33  *     The above copyright notice and this permission notice shall be
  34  *     included in all copies or substantial portions of the Software.
  35  *
  36  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  37  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  38  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  39  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  40  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  41  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  42  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  43  *     OTHER DEALINGS IN THE SOFTWARE.
  44  */
  45
  46 #include "qcom-mdm9615.dtsi"
  47
  48 / {
  49         model = "Sierra Wireless WP8548 Module";
  50         compatible = "swir,wp8548", "qcom,mdm9615";
  51
  52         memory {
  53                 reg = <0x48000000 0x7F00000>;
  54         };
  55 };
  56
  57 &msmgpio {
  58         pinctrl-0 = <&reset_out_pins>;
  59         pinctrl-names = "default";
  60
  61         gsbi3_pins: gsbi3_pins {
  62                 mux {
  63                         pins = "gpio8", "gpio9", "gpio10", "gpio11";
  64                         function = "gsbi3";
  65                         drive-strength = <8>;
  66                         bias-disable;
  67                 };
  68         };
  69
  70         gsbi4_pins: gsbi4_pins {
  71                 mux {
  72                         pins = "gpio12", "gpio13", "gpio14", "gpio15";
  73                         function = "gsbi4";
  74                         drive-strength = <8>;
  75                         bias-disable;
  76                 };
  77         };
  78
  79         gsbi5_i2c_pins: gsbi5_i2c_pins {
  80                 pin16 {
  81                         pins = "gpio16";
  82                         function = "gsbi5_i2c";
  83                         drive-strength = <8>;
  84                         bias-disable;
  85                 };
  86
  87                 pin17 {
  88                         pins = "gpio17";
  89                         function = "gsbi5_i2c";
  90                         drive-strength = <2>;
  91                         bias-disable;
  92                 };
  93         };
  94
  95         gsbi5_uart_pins: gsbi5_uart_pins {
  96                 mux {
  97                         pins = "gpio18", "gpio19";
  98                         function = "gsbi5_uart";
  99                         drive-strength = <8>;
 100                         bias-disable;
 101                 };
 102         };
 103
 104         reset_out_pins: reset_out_pins {
 105                 pins {
 106                         pins = "gpio66";
 107                         function = "gpio";
 108                         drive-strength = <2>;
 109                         bias-pull-up;
 110                         output-high;
 111                 };
 112         };
 113 };
 114
 115 &pmicgpio {
 116         usb_vbus_5v_pins: usb_vbus_5v_pins {
 117                 pins = "gpio4";
 118                 function = "normal";
 119                 output-high;
 120                 bias-disable;
 121                 qcom,drive-strength = <1>;
 122                 power-source = <2>;
 123         };
 124 };
 125
 126 &gsbi3 {
 127         status = "ok";
 128         qcom,mode = <GSBI_PROT_SPI>;
 129 };
 130
 131 &gsbi3_spi {
 132         status = "ok";
 133         pinctrl-0 = <&gsbi3_pins>;
 134         pinctrl-names = "default";
 135         assigned-clocks = <&gcc GSBI3_QUP_CLK>;
 136         assigned-clock-rates = <24000000>;
 137 };
 138
 139 &gsbi4 {
 140         status = "ok";
 141         qcom,mode = <GSBI_PROT_UART_W_FC>;
 142 };
 143
 144 &gsbi4_serial {
 145         status = "ok";
 146         pinctrl-0 = <&gsbi4_pins>;
 147         pinctrl-names = "default";
 148 };
 149
 150 &gsbi5 {
 151         status = "ok";
 152         qcom,mode = <GSBI_PROT_I2C_UART>;
 153 };
 154
 155 &gsbi5_i2c {
 156         status = "ok";
 157         clock-frequency = <200000>;
 158         pinctrl-0 = <&gsbi5_i2c_pins>;
 159         pinctrl-names = "default";
 160 };
 161
 162 &gsbi5_serial {
 163         status = "ok";
 164         pinctrl-0 = <&gsbi5_uart_pins>;
 165         pinctrl-names = "default";
 166 };
 167
 168 &sdcc1 {
 169         status = "ok";
 170 };