arch/arm/boot/dts/r7s72100.dtsi

   1 /*
   2  * Device Tree Source for the r7s72100 SoC
   3  *
   4  * Copyright (C) 2013-14 Renesas Solutions Corp.
   5  * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
   6  *
   7  * This file is licensed under the terms of the GNU General Public License
   8  * version 2.  This program is licensed "as is" without any warranty of any
   9  * kind, whether express or implied.
  10  */
  11
  12 #include <dt-bindings/clock/r7s72100-clock.h>
  13 #include <dt-bindings/interrupt-controller/arm-gic.h>
  14 #include <dt-bindings/interrupt-controller/irq.h>
  15
  16 / {
  17         compatible = "renesas,r7s72100";
  18         #address-cells = <1>;
  19         #size-cells = <1>;
  20
  21         aliases {
  22                 i2c0 = &i2c0;
  23                 i2c1 = &i2c1;
  24                 i2c2 = &i2c2;
  25                 i2c3 = &i2c3;
  26                 spi0 = &spi0;
  27                 spi1 = &spi1;
  28                 spi2 = &spi2;
  29                 spi3 = &spi3;
  30                 spi4 = &spi4;
  31         };
  32
  33         /* Fixed factor clocks */
  34         b_clk: b {
  35                 #clock-cells = <0>;
  36                 compatible = "fixed-factor-clock";
  37                 clocks = <&cpg_clocks R7S72100_CLK_PLL>;
  38                 clock-mult = <1>;
  39                 clock-div = <3>;
  40         };
  41
  42         cpus {
  43                 #address-cells = <1>;
  44                 #size-cells = <0>;
  45
  46                 cpu@0 {
  47                         device_type = "cpu";
  48                         compatible = "arm,cortex-a9";
  49                         reg = <0>;
  50                         clock-frequency = <400000000>;
  51                         clocks = <&cpg_clocks R7S72100_CLK_I>;
  52                         next-level-cache = <&L2>;
  53                 };
  54         };
  55
  56         /* External clocks */
  57         extal_clk: extal {
  58                 #clock-cells = <0>;
  59                 compatible = "fixed-clock";
  60                 /* If clk present, value must be set by board */
  61                 clock-frequency = <0>;
  62         };
  63
  64         p0_clk: p0 {
  65                 #clock-cells = <0>;
  66                 compatible = "fixed-factor-clock";
  67                 clocks = <&cpg_clocks R7S72100_CLK_PLL>;
  68                 clock-mult = <1>;
  69                 clock-div = <12>;
  70         };
  71
  72         p1_clk: p1 {
  73                 #clock-cells = <0>;
  74                 compatible = "fixed-factor-clock";
  75                 clocks = <&cpg_clocks R7S72100_CLK_PLL>;
  76                 clock-mult = <1>;
  77                 clock-div = <6>;
  78         };
  79
  80         pmu {
  81                 compatible = "arm,cortex-a9-pmu";
  82                 interrupts-extended = <&gic GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>;
  83         };
  84
  85         rtc_x1_clk: rtc_x1 {
  86                 #clock-cells = <0>;
  87                 compatible = "fixed-clock";
  88                 /* If clk present, value must be set by board to 32678 */
  89                 clock-frequency = <0>;
  90         };
  91
  92         rtc_x3_clk: rtc_x3 {
  93                 #clock-cells = <0>;
  94                 compatible = "fixed-clock";
  95                 /* If clk present, value must be set by board to 4000000 */
  96                 clock-frequency = <0>;
  97         };
  98
  99         soc {
 100                 compatible = "simple-bus";
 101                 interrupt-parent = <&gic>;
 102
 103                 #address-cells = <1>;
 104                 #size-cells = <1>;
 105                 ranges;
 106
 107                 L2: cache-controller@3ffff000 {
 108                         compatible = "arm,pl310-cache";
 109                         reg = <0x3ffff000 0x1000>;
 110                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 111                         arm,early-bresp-disable;
 112                         arm,full-line-zero-disable;
 113                         cache-unified;
 114                         cache-level = <2>;
 115                 };
 116
 117                 scif0: serial@e8007000 {
 118                         compatible = "renesas,scif-r7s72100", "renesas,scif";
 119                         reg = <0xe8007000 64>;
 120                         interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
 121                                      <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
 122                                      <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
 123                                      <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
 124                         clocks = <&mstp4_clks R7S72100_CLK_SCIF0>;
 125                         clock-names = "fck";
 126                         power-domains = <&cpg_clocks>;
 127                         status = "disabled";
 128                 };
 129
 130                 scif1: serial@e8007800 {
 131                         compatible = "renesas,scif-r7s72100", "renesas,scif";
 132                         reg = <0xe8007800 64>;
 133                         interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
 134                                      <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
 135                                      <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
 136                                      <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
 137                         clocks = <&mstp4_clks R7S72100_CLK_SCIF1>;
 138                         clock-names = "fck";
 139                         power-domains = <&cpg_clocks>;
 140                         status = "disabled";
 141                 };
 142
 143                 scif2: serial@e8008000 {
 144                         compatible = "renesas,scif-r7s72100", "renesas,scif";
 145                         reg = <0xe8008000 64>;
 146                         interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
 147                                      <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
 148                                      <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
 149                                      <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
 150                         clocks = <&mstp4_clks R7S72100_CLK_SCIF2>;
 151                         clock-names = "fck";
 152                         power-domains = <&cpg_clocks>;
 153                         status = "disabled";
 154                 };
 155
 156                 scif3: serial@e8008800 {
 157                         compatible = "renesas,scif-r7s72100", "renesas,scif";
 158                         reg = <0xe8008800 64>;
 159                         interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
 160                                      <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
 161                                      <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
 162                                      <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
 163                         clocks = <&mstp4_clks R7S72100_CLK_SCIF3>;
 164                         clock-names = "fck";
 165                         power-domains = <&cpg_clocks>;
 166                         status = "disabled";
 167                 };
 168
 169                 scif4: serial@e8009000 {
 170                         compatible = "renesas,scif-r7s72100", "renesas,scif";
 171                         reg = <0xe8009000 64>;
 172                         interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
 173                                      <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
 174                                      <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
 175                                      <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
 176                         clocks = <&mstp4_clks R7S72100_CLK_SCIF4>;
 177                         clock-names = "fck";
 178                         power-domains = <&cpg_clocks>;
 179                         status = "disabled";
 180                 };
 181
 182                 scif5: serial@e8009800 {
 183                         compatible = "renesas,scif-r7s72100", "renesas,scif";
 184                         reg = <0xe8009800 64>;
 185                         interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
 186                                      <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
 187                                      <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
 188                                      <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
 189                         clocks = <&mstp4_clks R7S72100_CLK_SCIF5>;
 190                         clock-names = "fck";
 191                         power-domains = <&cpg_clocks>;
 192                         status = "disabled";
 193                 };
 194
 195                 scif6: serial@e800a000 {
 196                         compatible = "renesas,scif-r7s72100", "renesas,scif";
 197                         reg = <0xe800a000 64>;
 198                         interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
 199                                      <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
 200                                      <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
 201                                      <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
 202                         clocks = <&mstp4_clks R7S72100_CLK_SCIF6>;
 203                         clock-names = "fck";
 204                         power-domains = <&cpg_clocks>;
 205                         status = "disabled";
 206                 };
 207
 208                 scif7: serial@e800a800 {
 209                         compatible = "renesas,scif-r7s72100", "renesas,scif";
 210                         reg = <0xe800a800 64>;
 211                         interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
 212                                      <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
 213                                      <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
 214                                      <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
 215                         clocks = <&mstp4_clks R7S72100_CLK_SCIF7>;
 216                         clock-names = "fck";
 217                         power-domains = <&cpg_clocks>;
 218                         status = "disabled";
 219                 };
 220
 221                 spi0: spi@e800c800 {
 222                         compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
 223                         reg = <0xe800c800 0x24>;
 224                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
 225                                      <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
 226                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
 227                         interrupt-names = "error", "rx", "tx";
 228                         clocks = <&mstp10_clks R7S72100_CLK_SPI0>;
 229                         power-domains = <&cpg_clocks>;
 230                         num-cs = <1>;
 231                         #address-cells = <1>;
 232                         #size-cells = <0>;
 233                         status = "disabled";
 234                 };
 235
 236                 spi1: spi@e800d000 {
 237                         compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
 238                         reg = <0xe800d000 0x24>;
 239                         interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
 240                                      <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
 241                                      <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
 242                         interrupt-names = "error", "rx", "tx";
 243                         clocks = <&mstp10_clks R7S72100_CLK_SPI1>;
 244                         power-domains = <&cpg_clocks>;
 245                         num-cs = <1>;
 246                         #address-cells = <1>;
 247                         #size-cells = <0>;
 248                         status = "disabled";
 249                 };
 250
 251                 spi2: spi@e800d800 {
 252                         compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
 253                         reg = <0xe800d800 0x24>;
 254                         interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
 255                                      <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
 256                                      <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
 257                         interrupt-names = "error", "rx", "tx";
 258                         clocks = <&mstp10_clks R7S72100_CLK_SPI2>;
 259                         power-domains = <&cpg_clocks>;
 260                         num-cs = <1>;
 261                         #address-cells = <1>;
 262                         #size-cells = <0>;
 263                         status = "disabled";
 264                 };
 265
 266                 spi3: spi@e800e000 {
 267                         compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
 268                         reg = <0xe800e000 0x24>;
 269                         interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
 270                                      <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
 271                                      <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
 272                         interrupt-names = "error", "rx", "tx";
 273                         clocks = <&mstp10_clks R7S72100_CLK_SPI3>;
 274                         power-domains = <&cpg_clocks>;
 275                         num-cs = <1>;
 276                         #address-cells = <1>;
 277                         #size-cells = <0>;
 278                         status = "disabled";
 279                 };
 280
 281                 spi4: spi@e800e800 {
 282                         compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
 283                         reg = <0xe800e800 0x24>;
 284                         interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
 285                                      <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
 286                                      <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
 287                         interrupt-names = "error", "rx", "tx";
 288                         clocks = <&mstp10_clks R7S72100_CLK_SPI4>;
 289                         power-domains = <&cpg_clocks>;
 290                         num-cs = <1>;
 291                         #address-cells = <1>;
 292                         #size-cells = <0>;
 293                         status = "disabled";
 294                 };
 295
 296                 usbhs0: usb@e8010000 {
 297                         compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs";
 298                         reg = <0xe8010000 0x1a0>;
 299                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 300                         clocks = <&mstp7_clks R7S72100_CLK_USB0>;
 301                         renesas,buswait = <4>;
 302                         power-domains = <&cpg_clocks>;
 303                         status = "disabled";
 304                 };
 305
 306                 usbhs1: usb@e8207000 {
 307                         compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs";
 308                         reg = <0xe8207000 0x1a0>;
 309                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 310                         clocks = <&mstp7_clks R7S72100_CLK_USB1>;
 311                         renesas,buswait = <4>;
 312                         power-domains = <&cpg_clocks>;
 313                         status = "disabled";
 314                 };
 315
 316                 mmcif: mmc@e804c800 {
 317                         compatible = "renesas,mmcif-r7s72100", "renesas,sh-mmcif";
 318                         reg = <0xe804c800 0x80>;
 319                         interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH
 320                                       GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH
 321                                       GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
 322                         clocks = <&mstp8_clks R7S72100_CLK_MMCIF>;
 323                         power-domains = <&cpg_clocks>;
 324                         reg-io-width = <4>;
 325                         bus-width = <8>;
 326                         status = "disabled";
 327                 };
 328
 329                 sdhi0: sd@e804e000 {
 330                         compatible = "renesas,sdhi-r7s72100";
 331                         reg = <0xe804e000 0x100>;
 332                         interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH
 333                                       GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH
 334                                       GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
 335
 336                         clocks = <&mstp12_clks R7S72100_CLK_SDHI00>,
 337                                  <&mstp12_clks R7S72100_CLK_SDHI01>;
 338                         clock-names = "core", "cd";
 339                         power-domains = <&cpg_clocks>;
 340                         cap-sd-highspeed;
 341                         cap-sdio-irq;
 342                         status = "disabled";
 343                 };
 344
 345                 sdhi1: sd@e804e800 {
 346                         compatible = "renesas,sdhi-r7s72100";
 347                         reg = <0xe804e800 0x100>;
 348                         interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH
 349                                       GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH
 350                                       GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>;
 351
 352                         clocks = <&mstp12_clks R7S72100_CLK_SDHI10>,
 353                                  <&mstp12_clks R7S72100_CLK_SDHI11>;
 354                         clock-names = "core", "cd";
 355                         power-domains = <&cpg_clocks>;
 356                         cap-sd-highspeed;
 357                         cap-sdio-irq;
 358                         status = "disabled";
 359                 };
 360
 361                 gic: interrupt-controller@e8201000 {
 362                         compatible = "arm,pl390";
 363                         #interrupt-cells = <3>;
 364                         #address-cells = <0>;
 365                         interrupt-controller;
 366                         reg = <0xe8201000 0x1000>,
 367                                 <0xe8202000 0x1000>;
 368                 };
 369
 370                 ether: ethernet@e8203000 {
 371                         compatible = "renesas,ether-r7s72100";
 372                         reg = <0xe8203000 0x800>,
 373                               <0xe8204800 0x200>;
 374                         interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
 375                         clocks = <&mstp7_clks R7S72100_CLK_ETHER>;
 376                         power-domains = <&cpg_clocks>;
 377                         phy-mode = "mii";
 378                         #address-cells = <1>;
 379                         #size-cells = <0>;
 380                         status = "disabled";
 381                 };
 382
 383                 ceu: camera@e8210000 {
 384                         reg = <0xe8210000 0x3000>;
 385                         compatible = "renesas,r7s72100-ceu";
 386                         interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
 387                         clocks = <&mstp6_clks R7S72100_CLK_CEU>;
 388                         power-domains = <&cpg_clocks>;
 389                         status = "disabled";
 390                 };
 391
 392                 wdt: watchdog@fcfe0000 {
 393                         compatible = "renesas,r7s72100-wdt", "renesas,rza-wdt";
 394                         reg = <0xfcfe0000 0x6>;
 395                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 396                         clocks = <&p0_clk>;
 397                 };
 398
 399                 /* Special CPG clocks */
 400                 cpg_clocks: cpg_clocks@fcfe0000 {
 401                         #clock-cells = <1>;
 402                         compatible = "renesas,r7s72100-cpg-clocks",
 403                                      "renesas,rz-cpg-clocks";
 404                         reg = <0xfcfe0000 0x18>;
 405                         clocks = <&extal_clk>, <&usb_x1_clk>;
 406                         clock-output-names = "pll", "i", "g";
 407                         #power-domain-cells = <0>;
 408                 };
 409
 410                 /* MSTP clocks */
 411                 mstp3_clks: mstp3_clks@fcfe0420 {
 412                         #clock-cells = <1>;
 413                         compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
 414                         reg = <0xfcfe0420 4>;
 415                         clocks = <&p0_clk>;
 416                         clock-indices = <R7S72100_CLK_MTU2>;
 417                         clock-output-names = "mtu2";
 418                 };
 419
 420                 mstp4_clks: mstp4_clks@fcfe0424 {
 421                         #clock-cells = <1>;
 422                         compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
 423                         reg = <0xfcfe0424 4>;
 424                         clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>,
 425                                  <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>;
 426                         clock-indices = <
 427                                 R7S72100_CLK_SCIF0 R7S72100_CLK_SCIF1 R7S72100_CLK_SCIF2 R7S72100_CLK_SCIF3
 428                                 R7S72100_CLK_SCIF4 R7S72100_CLK_SCIF5 R7S72100_CLK_SCIF6 R7S72100_CLK_SCIF7
 429                         >;
 430                         clock-output-names = "scif0", "scif1", "scif2", "scif3", "scif4", "scif5", "scif6", "scif7";
 431                 };
 432
 433                 mstp5_clks: mstp5_clks@fcfe0428 {
 434                         #clock-cells = <1>;
 435                         compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
 436                         reg = <0xfcfe0428 4>;
 437                         clocks = <&p0_clk>, <&p0_clk>;
 438                         clock-indices = <R7S72100_CLK_OSTM0 R7S72100_CLK_OSTM1>;
 439                         clock-output-names = "ostm0", "ostm1";
 440                 };
 441
 442                 mstp6_clks: mstp6_clks@fcfe042c {
 443                         #clock-cells = <1>;
 444                         compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
 445                         reg = <0xfcfe042c 4>;
 446                         clocks = <&b_clk>, <&p0_clk>;
 447                         clock-indices = <R7S72100_CLK_CEU R7S72100_CLK_RTC>;
 448                         clock-output-names = "ceu", "rtc";
 449                 };
 450
 451                 mstp7_clks: mstp7_clks@fcfe0430 {
 452                         #clock-cells = <1>;
 453                         compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
 454                         reg = <0xfcfe0430 4>;
 455                         clocks = <&b_clk>, <&p1_clk>, <&p1_clk>;
 456                         clock-indices = <R7S72100_CLK_ETHER R7S72100_CLK_USB0 R7S72100_CLK_USB1>;
 457                         clock-output-names = "ether", "usb0", "usb1";
 458                 };
 459
 460                 mstp8_clks: mstp8_clks@fcfe0434 {
 461                         #clock-cells = <1>;
 462                         compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
 463                         reg = <0xfcfe0434 4>;
 464                         clocks = <&p1_clk>;
 465                         clock-indices = <R7S72100_CLK_MMCIF>;
 466                         clock-output-names = "mmcif";
 467                 };
 468
 469                 mstp9_clks: mstp9_clks@fcfe0438 {
 470                         #clock-cells = <1>;
 471                         compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
 472                         reg = <0xfcfe0438 4>;
 473                         clocks = <&p0_clk>, <&p0_clk>, <&p0_clk>, <&p0_clk>;
 474                         clock-indices = <
 475                                 R7S72100_CLK_I2C0 R7S72100_CLK_I2C1 R7S72100_CLK_I2C2 R7S72100_CLK_I2C3
 476                         >;
 477                         clock-output-names = "i2c0", "i2c1", "i2c2", "i2c3";
 478                 };
 479
 480                 mstp10_clks: mstp10_clks@fcfe043c {
 481                         #clock-cells = <1>;
 482                         compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
 483                         reg = <0xfcfe043c 4>;
 484                         clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>,
 485                                  <&p1_clk>;
 486                         clock-indices = <
 487                                 R7S72100_CLK_SPI0 R7S72100_CLK_SPI1 R7S72100_CLK_SPI2 R7S72100_CLK_SPI3
 488                                 R7S72100_CLK_SPI4
 489                         >;
 490                         clock-output-names = "spi0", "spi1", "spi2", "spi3", "spi4";
 491                 };
 492                 mstp12_clks: mstp12_clks@fcfe0444 {
 493                         #clock-cells = <1>;
 494                         compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
 495                         reg = <0xfcfe0444 4>;
 496                         clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>;
 497                         clock-indices = <
 498                                 R7S72100_CLK_SDHI00 R7S72100_CLK_SDHI01
 499                                 R7S72100_CLK_SDHI10 R7S72100_CLK_SDHI11
 500                         >;
 501                         clock-output-names = "sdhi00", "sdhi01", "sdhi10", "sdhi11";
 502                 };
 503
 504                 pinctrl: pin-controller@fcfe3000 {
 505                         compatible = "renesas,r7s72100-ports";
 506
 507                         reg = <0xfcfe3000 0x4230>;
 508
 509                         port0: gpio-0 {
 510                                 gpio-controller;
 511                                 #gpio-cells = <2>;
 512                                 gpio-ranges = <&pinctrl 0 0 6>;
 513                         };
 514
 515                         port1: gpio-1 {
 516                                 gpio-controller;
 517                                 #gpio-cells = <2>;
 518                                 gpio-ranges = <&pinctrl 0 16 16>;
 519                         };
 520
 521                         port2: gpio-2 {
 522                                 gpio-controller;
 523                                 #gpio-cells = <2>;
 524                                 gpio-ranges = <&pinctrl 0 32 16>;
 525                         };
 526
 527                         port3: gpio-3 {
 528                                 gpio-controller;
 529                                 #gpio-cells = <2>;
 530                                 gpio-ranges = <&pinctrl 0 48 16>;
 531                         };
 532
 533                         port4: gpio-4 {
 534                                 gpio-controller;
 535                                 #gpio-cells = <2>;
 536                                 gpio-ranges = <&pinctrl 0 64 16>;
 537                         };
 538
 539                         port5: gpio-5 {
 540                                 gpio-controller;
 541                                 #gpio-cells = <2>;
 542                                 gpio-ranges = <&pinctrl 0 80 11>;
 543                         };
 544
 545                         port6: gpio-6 {
 546                                 gpio-controller;
 547                                 #gpio-cells = <2>;
 548                                 gpio-ranges = <&pinctrl 0 96 16>;
 549                         };
 550
 551                         port7: gpio-7 {
 552                                 gpio-controller;
 553                                 #gpio-cells = <2>;
 554                                 gpio-ranges = <&pinctrl 0 112 16>;
 555                         };
 556
 557                         port8: gpio-8 {
 558                                 gpio-controller;
 559                                 #gpio-cells = <2>;
 560                                 gpio-ranges = <&pinctrl 0 128 16>;
 561                         };
 562
 563                         port9: gpio-9 {
 564                                 gpio-controller;
 565                                 #gpio-cells = <2>;
 566                                 gpio-ranges = <&pinctrl 0 144 8>;
 567                         };
 568
 569                         port10: gpio-10 {
 570                                 gpio-controller;
 571                                 #gpio-cells = <2>;
 572                                 gpio-ranges = <&pinctrl 0 160 16>;
 573                         };
 574
 575                         port11: gpio-11 {
 576                                 gpio-controller;
 577                                 #gpio-cells = <2>;
 578                                 gpio-ranges = <&pinctrl 0 176 16>;
 579                         };
 580                 };
 581
 582                 ostm0: timer@fcfec000 {
 583                         compatible = "renesas,r7s72100-ostm", "renesas,ostm";
 584                         reg = <0xfcfec000 0x30>;
 585                         interrupts = <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>;
 586                         clocks = <&mstp5_clks R7S72100_CLK_OSTM0>;
 587                         power-domains = <&cpg_clocks>;
 588                         status = "disabled";
 589                 };
 590
 591                 ostm1: timer@fcfec400 {
 592                         compatible = "renesas,r7s72100-ostm", "renesas,ostm";
 593                         reg = <0xfcfec400 0x30>;
 594                         interrupts = <GIC_SPI 103 IRQ_TYPE_EDGE_RISING>;
 595                         clocks = <&mstp5_clks R7S72100_CLK_OSTM1>;
 596                         power-domains = <&cpg_clocks>;
 597                         status = "disabled";
 598                 };
 599
 600                 i2c0: i2c@fcfee000 {
 601                         #address-cells = <1>;
 602                         #size-cells = <0>;
 603                         compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
 604                         reg = <0xfcfee000 0x44>;
 605                         interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
 606                                      <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>,
 607                                      <GIC_SPI 159 IRQ_TYPE_EDGE_RISING>,
 608                                      <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
 609                                      <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
 610                                      <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
 611                                      <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
 612                                      <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
 613                         clocks = <&mstp9_clks R7S72100_CLK_I2C0>;
 614                         clock-frequency = <100000>;
 615                         power-domains = <&cpg_clocks>;
 616                         status = "disabled";
 617                 };
 618
 619                 i2c1: i2c@fcfee400 {
 620                         #address-cells = <1>;
 621                         #size-cells = <0>;
 622                         compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
 623                         reg = <0xfcfee400 0x44>;
 624                         interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
 625                                      <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>,
 626                                      <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>,
 627                                      <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
 628                                      <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
 629                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 630                                      <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
 631                                      <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
 632                         clocks = <&mstp9_clks R7S72100_CLK_I2C1>;
 633                         clock-frequency = <100000>;
 634                         power-domains = <&cpg_clocks>;
 635                         status = "disabled";
 636                 };
 637
 638                 i2c2: i2c@fcfee800 {
 639                         #address-cells = <1>;
 640                         #size-cells = <0>;
 641                         compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
 642                         reg = <0xfcfee800 0x44>;
 643                         interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
 644                                      <GIC_SPI 174 IRQ_TYPE_EDGE_RISING>,
 645                                      <GIC_SPI 175 IRQ_TYPE_EDGE_RISING>,
 646                                      <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
 647                                      <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
 648                                      <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
 649                                      <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
 650                                      <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
 651                         clocks = <&mstp9_clks R7S72100_CLK_I2C2>;
 652                         clock-frequency = <100000>;
 653                         power-domains = <&cpg_clocks>;
 654                         status = "disabled";
 655                 };
 656
 657                 i2c3: i2c@fcfeec00 {
 658                         #address-cells = <1>;
 659                         #size-cells = <0>;
 660                         compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
 661                         reg = <0xfcfeec00 0x44>;
 662                         interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
 663                                      <GIC_SPI 182 IRQ_TYPE_EDGE_RISING>,
 664                                      <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>,
 665                                      <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
 666                                      <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
 667                                      <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
 668                                      <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
 669                                      <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
 670                         clocks = <&mstp9_clks R7S72100_CLK_I2C3>;
 671                         clock-frequency = <100000>;
 672                         power-domains = <&cpg_clocks>;
 673                         status = "disabled";
 674                 };
 675
 676                 mtu2: timer@fcff0000 {
 677                         compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
 678                         reg = <0xfcff0000 0x400>;
 679                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 680                         interrupt-names = "tgi0a";
 681                         clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
 682                         clock-names = "fck";
 683                         power-domains = <&cpg_clocks>;
 684                         status = "disabled";
 685                 };
 686
 687                 rtc: rtc@fcff1000 {
 688                         compatible = "renesas,r7s72100-rtc", "renesas,sh-rtc";
 689                         reg = <0xfcff1000 0x2e>;
 690                         interrupts = <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
 691                                      <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
 692                                      <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
 693                         interrupt-names = "alarm", "period", "carry";
 694                         clocks = <&mstp6_clks R7S72100_CLK_RTC>, <&rtc_x1_clk>,
 695                                  <&rtc_x3_clk>, <&extal_clk>;
 696                         clock-names = "fck", "rtc_x1", "rtc_x3", "extal";
 697                         power-domains = <&cpg_clocks>;
 698                         status = "disabled";
 699                 };
 700         };
 701
 702         usb_x1_clk: usb_x1 {
 703                 #clock-cells = <0>;
 704                 compatible = "fixed-clock";
 705                 /* If clk present, value must be set by board */
 706                 clock-frequency = <0>;
 707         };
 708 };