arch/arm/boot/dts/r8a7745.dtsi

   1 /*
   2  * Device Tree Source for the r8a7745 SoC
   3  *
   4  * Copyright (C) 2016-2017 Cogent Embedded Inc.
   5  *
   6  * This file is licensed under the terms of the GNU General Public License
   7  * version 2. This program is licensed "as is" without any warranty of any
   8  * kind, whether express or implied.
   9  */
  10
  11 #include <dt-bindings/interrupt-controller/irq.h>
  12 #include <dt-bindings/interrupt-controller/arm-gic.h>
  13 #include <dt-bindings/clock/r8a7745-cpg-mssr.h>
  14 #include <dt-bindings/power/r8a7745-sysc.h>
  15
  16 / {
  17         compatible = "renesas,r8a7745";
  18         #address-cells = <2>;
  19         #size-cells = <2>;
  20
  21         cpus {
  22                 #address-cells = <1>;
  23                 #size-cells = <0>;
  24
  25                 cpu0: cpu@0 {
  26                         device_type = "cpu";
  27                         compatible = "arm,cortex-a7";
  28                         reg = <0>;
  29                         clock-frequency = <1000000000>;
  30                         clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>;
  31                         power-domains = <&sysc R8A7745_PD_CA7_CPU0>;
  32                         next-level-cache = <&L2_CA7>;
  33                 };
  34
  35                 L2_CA7: cache-controller-0 {
  36                         compatible = "cache";
  37                         cache-unified;
  38                         cache-level = <2>;
  39                         power-domains = <&sysc R8A7745_PD_CA7_SCU>;
  40                 };
  41         };
  42
  43         soc {
  44                 compatible = "simple-bus";
  45                 interrupt-parent = <&gic>;
  46
  47                 #address-cells = <2>;
  48                 #size-cells = <2>;
  49                 ranges;
  50
  51                 gic: interrupt-controller@f1001000 {
  52                         compatible = "arm,gic-400";
  53                         #interrupt-cells = <3>;
  54                         #address-cells = <0>;
  55                         interrupt-controller;
  56                         reg = <0 0xf1001000 0 0x1000>,
  57                               <0 0xf1002000 0 0x2000>,
  58                               <0 0xf1004000 0 0x2000>,
  59                               <0 0xf1006000 0 0x2000>;
  60                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
  61                                                  IRQ_TYPE_LEVEL_HIGH)>;
  62                         clocks = <&cpg CPG_MOD 408>;
  63                         clock-names = "clk";
  64                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
  65                         resets = <&cpg 408>;
  66                 };
  67
  68                 irqc: interrupt-controller@e61c0000 {
  69                         compatible = "renesas,irqc-r8a7745", "renesas,irqc";
  70                         #interrupt-cells = <2>;
  71                         interrupt-controller;
  72                         reg = <0 0xe61c0000 0 0x200>;
  73                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
  74                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
  75                                      <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
  76                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
  77                                      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
  78                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
  79                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
  80                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
  81                                      <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
  82                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
  83                         clocks = <&cpg CPG_MOD 407>;
  84                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
  85                         resets = <&cpg 407>;
  86                 };
  87
  88                 timer {
  89                         compatible = "arm,armv7-timer";
  90                         interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
  91                                                   IRQ_TYPE_LEVEL_LOW)>,
  92                                      <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
  93                                                   IRQ_TYPE_LEVEL_LOW)>,
  94                                      <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
  95                                                   IRQ_TYPE_LEVEL_LOW)>,
  96                                      <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
  97                                                   IRQ_TYPE_LEVEL_LOW)>;
  98                 };
  99
 100                 cpg: clock-controller@e6150000 {
 101                         compatible = "renesas,r8a7745-cpg-mssr";
 102                         reg = <0 0xe6150000 0 0x1000>;
 103                         clocks = <&extal_clk>, <&usb_extal_clk>;
 104                         clock-names = "extal", "usb_extal";
 105                         #clock-cells = <2>;
 106                         #power-domain-cells = <0>;
 107                         #reset-cells = <1>;
 108                 };
 109
 110                 prr: chipid@ff000044 {
 111                         compatible = "renesas,prr";
 112                         reg = <0 0xff000044 0 4>;
 113                 };
 114
 115                 rst: reset-controller@e6160000 {
 116                         compatible = "renesas,r8a7745-rst";
 117                         reg = <0 0xe6160000 0 0x100>;
 118                 };
 119
 120                 sysc: system-controller@e6180000 {
 121                         compatible = "renesas,r8a7745-sysc";
 122                         reg = <0 0xe6180000 0 0x200>;
 123                         #power-domain-cells = <1>;
 124                 };
 125
 126                 pfc: pin-controller@e6060000 {
 127                         compatible = "renesas,pfc-r8a7745";
 128                         reg = <0 0xe6060000 0 0x11c>;
 129                 };
 130
 131                 dmac0: dma-controller@e6700000 {
 132                         compatible = "renesas,dmac-r8a7745",
 133                                      "renesas,rcar-dmac";
 134                         reg = <0 0xe6700000 0 0x20000>;
 135                         interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
 136                                       GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
 137                                       GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
 138                                       GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
 139                                       GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
 140                                       GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
 141                                       GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
 142                                       GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
 143                                       GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
 144                                       GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
 145                                       GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
 146                                       GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
 147                                       GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
 148                                       GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
 149                                       GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
 150                                       GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
 151                         interrupt-names = "error",
 152                                         "ch0", "ch1", "ch2", "ch3",
 153                                         "ch4", "ch5", "ch6", "ch7",
 154                                         "ch8", "ch9", "ch10", "ch11",
 155                                         "ch12", "ch13", "ch14";
 156                         clocks = <&cpg CPG_MOD 219>;
 157                         clock-names = "fck";
 158                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
 159                         resets = <&cpg 219>;
 160                         #dma-cells = <1>;
 161                         dma-channels = <15>;
 162                 };
 163
 164                 dmac1: dma-controller@e6720000 {
 165                         compatible = "renesas,dmac-r8a7745",
 166                                      "renesas,rcar-dmac";
 167                         reg = <0 0xe6720000 0 0x20000>;
 168                         interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
 169                                       GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
 170                                       GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
 171                                       GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
 172                                       GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
 173                                       GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
 174                                       GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
 175                                       GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
 176                                       GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
 177                                       GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
 178                                       GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
 179                                       GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
 180                                       GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
 181                                       GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
 182                                       GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
 183                                       GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
 184                         interrupt-names = "error",
 185                                         "ch0", "ch1", "ch2", "ch3",
 186                                         "ch4", "ch5", "ch6", "ch7",
 187                                         "ch8", "ch9", "ch10", "ch11",
 188                                         "ch12", "ch13", "ch14";
 189                         clocks = <&cpg CPG_MOD 218>;
 190                         clock-names = "fck";
 191                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
 192                         resets = <&cpg 218>;
 193                         #dma-cells = <1>;
 194                         dma-channels = <15>;
 195                 };
 196
 197                 scifa0: serial@e6c40000 {
 198                         compatible = "renesas,scifa-r8a7745",
 199                                      "renesas,rcar-gen2-scifa", "renesas,scifa";
 200                         reg = <0 0xe6c40000 0 0x40>;
 201                         interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 202                         clocks = <&cpg CPG_MOD 204>;
 203                         clock-names = "fck";
 204                         dmas = <&dmac0 0x21>, <&dmac0 0x22>,
 205                                <&dmac1 0x21>, <&dmac1 0x22>;
 206                         dma-names = "tx", "rx", "tx", "rx";
 207                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
 208                         resets = <&cpg 204>;
 209                         status = "disabled";
 210                 };
 211
 212                 scifa1: serial@e6c50000 {
 213                         compatible = "renesas,scifa-r8a7745",
 214                                      "renesas,rcar-gen2-scifa", "renesas,scifa";
 215                         reg = <0 0xe6c50000 0 0x40>;
 216                         interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
 217                         clocks = <&cpg CPG_MOD 203>;
 218                         clock-names = "fck";
 219                         dmas = <&dmac0 0x25>, <&dmac0 0x26>,
 220                                <&dmac1 0x25>, <&dmac1 0x26>;
 221                         dma-names = "tx", "rx", "tx", "rx";
 222                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
 223                         resets = <&cpg 203>;
 224                         status = "disabled";
 225                 };
 226
 227                 scifa2: serial@e6c60000 {
 228                         compatible = "renesas,scifa-r8a7745",
 229                                      "renesas,rcar-gen2-scifa", "renesas,scifa";
 230                         reg = <0 0xe6c60000 0 0x40>;
 231                         interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
 232                         clocks = <&cpg CPG_MOD 202>;
 233                         clock-names = "fck";
 234                         dmas = <&dmac0 0x27>, <&dmac0 0x28>,
 235                                <&dmac1 0x27>, <&dmac1 0x28>;
 236                         dma-names = "tx", "rx", "tx", "rx";
 237                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
 238                         resets = <&cpg 202>;
 239                         status = "disabled";
 240                 };
 241
 242                 scifa3: serial@e6c70000 {
 243                         compatible = "renesas,scifa-r8a7745",
 244                                      "renesas,rcar-gen2-scifa", "renesas,scifa";
 245                         reg = <0 0xe6c70000 0 0x40>;
 246                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 247                         clocks = <&cpg CPG_MOD 1106>;
 248                         clock-names = "fck";
 249                         dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
 250                                <&dmac1 0x1b>, <&dmac1 0x1c>;
 251                         dma-names = "tx", "rx", "tx", "rx";
 252                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
 253                         resets = <&cpg 1106>;
 254                         status = "disabled";
 255                 };
 256
 257                 scifa4: serial@e6c78000 {
 258                         compatible = "renesas,scifa-r8a7745",
 259                                      "renesas,rcar-gen2-scifa", "renesas,scifa";
 260                         reg = <0 0xe6c78000 0 0x40>;
 261                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 262                         clocks = <&cpg CPG_MOD 1107>;
 263                         clock-names = "fck";
 264                         dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
 265                                <&dmac1 0x1f>, <&dmac1 0x20>;
 266                         dma-names = "tx", "rx", "tx", "rx";
 267                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
 268                         resets = <&cpg 1107>;
 269                         status = "disabled";
 270                 };
 271
 272                 scifa5: serial@e6c80000 {
 273                         compatible = "renesas,scifa-r8a7745",
 274                                      "renesas,rcar-gen2-scifa", "renesas,scifa";
 275                         reg = <0 0xe6c80000 0 0x40>;
 276                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 277                         clocks = <&cpg CPG_MOD 1108>;
 278                         clock-names = "fck";
 279                         dmas = <&dmac0 0x23>, <&dmac0 0x24>,
 280                                <&dmac1 0x23>, <&dmac1 0x24>;
 281                         dma-names = "tx", "rx", "tx", "rx";
 282                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
 283                         resets = <&cpg 1108>;
 284                         status = "disabled";
 285                 };
 286
 287                 scifb0: serial@e6c20000 {
 288                         compatible = "renesas,scifb-r8a7745",
 289                                      "renesas,rcar-gen2-scifb", "renesas,scifb";
 290                         reg = <0 0xe6c20000 0 0x100>;
 291                         interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
 292                         clocks = <&cpg CPG_MOD 206>;
 293                         clock-names = "fck";
 294                         dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
 295                                <&dmac1 0x3d>, <&dmac1 0x3e>;
 296                         dma-names = "tx", "rx", "tx", "rx";
 297                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
 298                         resets = <&cpg 206>;
 299                         status = "disabled";
 300                 };
 301
 302                 scifb1: serial@e6c30000 {
 303                         compatible = "renesas,scifb-r8a7745",
 304                                      "renesas,rcar-gen2-scifb", "renesas,scifb";
 305                         reg = <0 0xe6c30000 0 0x100>;
 306                         interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 307                         clocks = <&cpg CPG_MOD 207>;
 308                         clock-names = "fck";
 309                         dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
 310                                <&dmac1 0x19>, <&dmac1 0x1a>;
 311                         dma-names = "tx", "rx", "tx", "rx";
 312                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
 313                         resets = <&cpg 207>;
 314                         status = "disabled";
 315                 };
 316
 317                 scifb2: serial@e6ce0000 {
 318                         compatible = "renesas,scifb-r8a7745",
 319                                      "renesas,rcar-gen2-scifb", "renesas,scifb";
 320                         reg = <0 0xe6ce0000 0 0x100>;
 321                         interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
 322                         clocks = <&cpg CPG_MOD 216>;
 323                         clock-names = "fck";
 324                         dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
 325                                <&dmac1 0x1d>, <&dmac1 0x1e>;
 326                         dma-names = "tx", "rx", "tx", "rx";
 327                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
 328                         resets = <&cpg 216>;
 329                         status = "disabled";
 330                 };
 331
 332                 scif0: serial@e6e60000 {
 333                         compatible = "renesas,scif-r8a7745",
 334                                      "renesas,rcar-gen2-scif", "renesas,scif";
 335                         reg = <0 0xe6e60000 0 0x40>;
 336                         interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
 337                         clocks = <&cpg CPG_MOD 721>,
 338                                  <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
 339                         clock-names = "fck", "brg_int", "scif_clk";
 340                         dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
 341                                <&dmac1 0x29>, <&dmac1 0x2a>;
 342                         dma-names = "tx", "rx", "tx", "rx";
 343                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
 344                         resets = <&cpg 721>;
 345                         status = "disabled";
 346                 };
 347
 348                 scif1: serial@e6e68000 {
 349                         compatible = "renesas,scif-r8a7745",
 350                                      "renesas,rcar-gen2-scif", "renesas,scif";
 351                         reg = <0 0xe6e68000 0 0x40>;
 352                         interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 353                         clocks = <&cpg CPG_MOD 720>,
 354                                  <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
 355                         clock-names = "fck", "brg_int", "scif_clk";
 356                         dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
 357                                <&dmac1 0x2d>, <&dmac1 0x2e>;
 358                         dma-names = "tx", "rx", "tx", "rx";
 359                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
 360                         resets = <&cpg 720>;
 361                         status = "disabled";
 362                 };
 363
 364                 scif2: serial@e6e58000 {
 365                         compatible = "renesas,scif-r8a7745",
 366                                      "renesas,rcar-gen2-scif", "renesas,scif";
 367                         reg = <0 0xe6e58000 0 0x40>;
 368                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 369                         clocks = <&cpg CPG_MOD 719>,
 370                                  <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
 371                         clock-names = "fck", "brg_int", "scif_clk";
 372                         dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
 373                                <&dmac1 0x2b>, <&dmac1 0x2c>;
 374                         dma-names = "tx", "rx", "tx", "rx";
 375                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
 376                         resets = <&cpg 719>;
 377                         status = "disabled";
 378                 };
 379
 380                 scif3: serial@e6ea8000 {
 381                         compatible = "renesas,scif-r8a7745",
 382                                      "renesas,rcar-gen2-scif", "renesas,scif";
 383                         reg = <0 0xe6ea8000 0 0x40>;
 384                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 385                         clocks = <&cpg CPG_MOD 718>,
 386                                  <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
 387                         clock-names = "fck", "brg_int", "scif_clk";
 388                         dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
 389                                <&dmac1 0x2f>, <&dmac1 0x30>;
 390                         dma-names = "tx", "rx", "tx", "rx";
 391                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
 392                         resets = <&cpg 718>;
 393                         status = "disabled";
 394                 };
 395
 396                 scif4: serial@e6ee0000 {
 397                         compatible = "renesas,scif-r8a7745",
 398                                      "renesas,rcar-gen2-scif", "renesas,scif";
 399                         reg = <0 0xe6ee0000 0 0x40>;
 400                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 401                         clocks = <&cpg CPG_MOD 715>,
 402                                  <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
 403                         clock-names = "fck", "brg_int", "scif_clk";
 404                         dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
 405                                <&dmac1 0xfb>, <&dmac1 0xfc>;
 406                         dma-names = "tx", "rx", "tx", "rx";
 407                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
 408                         resets = <&cpg 715>;
 409                         status = "disabled";
 410                 };
 411
 412                 scif5: serial@e6ee8000 {
 413                         compatible = "renesas,scif-r8a7745",
 414                                      "renesas,rcar-gen2-scif", "renesas,scif";
 415                         reg = <0 0xe6ee8000 0 0x40>;
 416                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 417                         clocks = <&cpg CPG_MOD 714>,
 418                                  <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
 419                         clock-names = "fck", "brg_int", "scif_clk";
 420                         dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
 421                                <&dmac1 0xfd>, <&dmac1 0xfe>;
 422                         dma-names = "tx", "rx", "tx", "rx";
 423                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
 424                         resets = <&cpg 714>;
 425                         status = "disabled";
 426                 };
 427
 428                 hscif0: serial@e62c0000 {
 429                         compatible = "renesas,hscif-r8a7745",
 430                                      "renesas,rcar-gen2-hscif", "renesas,hscif";
 431                         reg = <0 0xe62c0000 0 0x60>;
 432                         interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 433                         clocks = <&cpg CPG_MOD 717>,
 434                                  <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
 435                         clock-names = "fck", "brg_int", "scif_clk";
 436                         dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
 437                                <&dmac1 0x39>, <&dmac1 0x3a>;
 438                         dma-names = "tx", "rx", "tx", "rx";
 439                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
 440                         resets = <&cpg 717>;
 441                         status = "disabled";
 442                 };
 443
 444                 hscif1: serial@e62c8000 {
 445                         compatible = "renesas,hscif-r8a7745",
 446                                      "renesas,rcar-gen2-hscif", "renesas,hscif";
 447                         reg = <0 0xe62c8000 0 0x60>;
 448                         interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
 449                         clocks = <&cpg CPG_MOD 716>,
 450                                  <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
 451                         clock-names = "fck", "brg_int", "scif_clk";
 452                         dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
 453                                <&dmac1 0x4d>, <&dmac1 0x4e>;
 454                         dma-names = "tx", "rx", "tx", "rx";
 455                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
 456                         resets = <&cpg 716>;
 457                         status = "disabled";
 458                 };
 459
 460                 hscif2: serial@e62d0000 {
 461                         compatible = "renesas,hscif-r8a7745",
 462                                      "renesas,rcar-gen2-hscif", "renesas,hscif";
 463                         reg = <0 0xe62d0000 0 0x60>;
 464                         interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 465                         clocks = <&cpg CPG_MOD 713>,
 466                                  <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
 467                         clock-names = "fck", "brg_int", "scif_clk";
 468                         dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
 469                                <&dmac1 0x3b>, <&dmac1 0x3c>;
 470                         dma-names = "tx", "rx", "tx", "rx";
 471                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
 472                         resets = <&cpg 713>;
 473                         status = "disabled";
 474                 };
 475
 476                 icram2: sram@e6300000 {
 477                         compatible = "mmio-sram";
 478                         reg = <0 0xe6300000 0 0x40000>;
 479                 };
 480
 481                 icram0: sram@e63a0000 {
 482                         compatible = "mmio-sram";
 483                         reg = <0 0xe63a0000 0 0x12000>;
 484                 };
 485
 486                 icram1: sram@e63c0000 {
 487                         compatible = "mmio-sram";
 488                         reg = <0 0xe63c0000 0 0x1000>;
 489                         #address-cells = <1>;
 490                         #size-cells = <1>;
 491                         ranges = <0 0 0xe63c0000 0x1000>;
 492
 493                         smp-sram@0 {
 494                                 compatible = "renesas,smp-sram";
 495                                 reg = <0 0x10>;
 496                         };
 497                 };
 498
 499                 ether: ethernet@ee700000 {
 500                         compatible = "renesas,ether-r8a7745";
 501                         reg = <0 0xee700000 0 0x400>;
 502                         interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
 503                         clocks = <&cpg CPG_MOD 813>;
 504                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
 505                         resets = <&cpg 813>;
 506                         phy-mode = "rmii";
 507                         #address-cells = <1>;
 508                         #size-cells = <0>;
 509                         status = "disabled";
 510                 };
 511         };
 512
 513         /* External root clock */
 514         extal_clk: extal {
 515                 compatible = "fixed-clock";
 516                 #clock-cells = <0>;
 517                 /* This value must be overridden by the board. */
 518                 clock-frequency = <0>;
 519         };
 520
 521         /* External USB clock - can be overridden by the board */
 522         usb_extal_clk: usb_extal {
 523                 compatible = "fixed-clock";
 524                 #clock-cells = <0>;
 525                 clock-frequency = <48000000>;
 526         };
 527
 528         /* External SCIF clock */
 529         scif_clk: scif {
 530                 compatible = "fixed-clock";
 531                 #clock-cells = <0>;
 532                 /* This value must be overridden by the board. */
 533                 clock-frequency = <0>;
 534         };
 535 };