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Merge branch 'for-rc' of git://git.kernel.org/pub/scm/linux/kernel/git/rzhang/linux
[mirror_ubuntu-artful-kernel.git] / arch / arm / boot / dts / r8a7790.dtsi
1 /*
2 * Device Tree Source for the r8a7790 SoC
3 *
4 * Copyright (C) 2015 Renesas Electronics Corporation
5 * Copyright (C) 2013-2014 Renesas Solutions Corp.
6 * Copyright (C) 2014 Cogent Embedded Inc.
7 *
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
11 */
12
13 #include <dt-bindings/clock/r8a7790-clock.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/interrupt-controller/irq.h>
16 #include <dt-bindings/power/r8a7790-sysc.h>
17
18 / {
19 compatible = "renesas,r8a7790";
20 interrupt-parent = <&gic>;
21 #address-cells = <2>;
22 #size-cells = <2>;
23
24 aliases {
25 i2c0 = &i2c0;
26 i2c1 = &i2c1;
27 i2c2 = &i2c2;
28 i2c3 = &i2c3;
29 i2c4 = &iic0;
30 i2c5 = &iic1;
31 i2c6 = &iic2;
32 i2c7 = &iic3;
33 spi0 = &qspi;
34 spi1 = &msiof0;
35 spi2 = &msiof1;
36 spi3 = &msiof2;
37 spi4 = &msiof3;
38 vin0 = &vin0;
39 vin1 = &vin1;
40 vin2 = &vin2;
41 vin3 = &vin3;
42 };
43
44 cpus {
45 #address-cells = <1>;
46 #size-cells = <0>;
47 enable-method = "renesas,apmu";
48
49 cpu0: cpu@0 {
50 device_type = "cpu";
51 compatible = "arm,cortex-a15";
52 reg = <0>;
53 clock-frequency = <1300000000>;
54 voltage-tolerance = <1>; /* 1% */
55 clocks = <&cpg_clocks R8A7790_CLK_Z>;
56 clock-latency = <300000>; /* 300 us */
57 power-domains = <&sysc R8A7790_PD_CA15_CPU0>;
58 next-level-cache = <&L2_CA15>;
59
60 /* kHz - uV - OPPs unknown yet */
61 operating-points = <1400000 1000000>,
62 <1225000 1000000>,
63 <1050000 1000000>,
64 < 875000 1000000>,
65 < 700000 1000000>,
66 < 350000 1000000>;
67 };
68
69 cpu1: cpu@1 {
70 device_type = "cpu";
71 compatible = "arm,cortex-a15";
72 reg = <1>;
73 clock-frequency = <1300000000>;
74 power-domains = <&sysc R8A7790_PD_CA15_CPU1>;
75 next-level-cache = <&L2_CA15>;
76 };
77
78 cpu2: cpu@2 {
79 device_type = "cpu";
80 compatible = "arm,cortex-a15";
81 reg = <2>;
82 clock-frequency = <1300000000>;
83 power-domains = <&sysc R8A7790_PD_CA15_CPU2>;
84 next-level-cache = <&L2_CA15>;
85 };
86
87 cpu3: cpu@3 {
88 device_type = "cpu";
89 compatible = "arm,cortex-a15";
90 reg = <3>;
91 clock-frequency = <1300000000>;
92 power-domains = <&sysc R8A7790_PD_CA15_CPU3>;
93 next-level-cache = <&L2_CA15>;
94 };
95
96 cpu4: cpu@100 {
97 device_type = "cpu";
98 compatible = "arm,cortex-a7";
99 reg = <0x100>;
100 clock-frequency = <780000000>;
101 power-domains = <&sysc R8A7790_PD_CA7_CPU0>;
102 next-level-cache = <&L2_CA7>;
103 };
104
105 cpu5: cpu@101 {
106 device_type = "cpu";
107 compatible = "arm,cortex-a7";
108 reg = <0x101>;
109 clock-frequency = <780000000>;
110 power-domains = <&sysc R8A7790_PD_CA7_CPU1>;
111 next-level-cache = <&L2_CA7>;
112 };
113
114 cpu6: cpu@102 {
115 device_type = "cpu";
116 compatible = "arm,cortex-a7";
117 reg = <0x102>;
118 clock-frequency = <780000000>;
119 power-domains = <&sysc R8A7790_PD_CA7_CPU2>;
120 next-level-cache = <&L2_CA7>;
121 };
122
123 cpu7: cpu@103 {
124 device_type = "cpu";
125 compatible = "arm,cortex-a7";
126 reg = <0x103>;
127 clock-frequency = <780000000>;
128 power-domains = <&sysc R8A7790_PD_CA7_CPU3>;
129 next-level-cache = <&L2_CA7>;
130 };
131
132 L2_CA15: cache-controller@0 {
133 compatible = "cache";
134 reg = <0>;
135 power-domains = <&sysc R8A7790_PD_CA15_SCU>;
136 cache-unified;
137 cache-level = <2>;
138 };
139
140 L2_CA7: cache-controller@100 {
141 compatible = "cache";
142 reg = <0x100>;
143 power-domains = <&sysc R8A7790_PD_CA7_SCU>;
144 cache-unified;
145 cache-level = <2>;
146 };
147 };
148
149 thermal-zones {
150 cpu_thermal: cpu-thermal {
151 polling-delay-passive = <0>;
152 polling-delay = <0>;
153
154 thermal-sensors = <&thermal>;
155
156 trips {
157 cpu-crit {
158 temperature = <115000>;
159 hysteresis = <0>;
160 type = "critical";
161 };
162 };
163 cooling-maps {
164 };
165 };
166 };
167
168 apmu@e6151000 {
169 compatible = "renesas,r8a7790-apmu", "renesas,apmu";
170 reg = <0 0xe6151000 0 0x188>;
171 cpus = <&cpu4 &cpu5 &cpu6 &cpu7>;
172 };
173
174 apmu@e6152000 {
175 compatible = "renesas,r8a7790-apmu", "renesas,apmu";
176 reg = <0 0xe6152000 0 0x188>;
177 cpus = <&cpu0 &cpu1 &cpu2 &cpu3>;
178 };
179
180 gic: interrupt-controller@f1001000 {
181 compatible = "arm,gic-400";
182 #interrupt-cells = <3>;
183 #address-cells = <0>;
184 interrupt-controller;
185 reg = <0 0xf1001000 0 0x1000>,
186 <0 0xf1002000 0 0x1000>,
187 <0 0xf1004000 0 0x2000>,
188 <0 0xf1006000 0 0x2000>;
189 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
190 };
191
192 gpio0: gpio@e6050000 {
193 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
194 reg = <0 0xe6050000 0 0x50>;
195 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
196 #gpio-cells = <2>;
197 gpio-controller;
198 gpio-ranges = <&pfc 0 0 32>;
199 #interrupt-cells = <2>;
200 interrupt-controller;
201 clocks = <&mstp9_clks R8A7790_CLK_GPIO0>;
202 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
203 };
204
205 gpio1: gpio@e6051000 {
206 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
207 reg = <0 0xe6051000 0 0x50>;
208 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
209 #gpio-cells = <2>;
210 gpio-controller;
211 gpio-ranges = <&pfc 0 32 30>;
212 #interrupt-cells = <2>;
213 interrupt-controller;
214 clocks = <&mstp9_clks R8A7790_CLK_GPIO1>;
215 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
216 };
217
218 gpio2: gpio@e6052000 {
219 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
220 reg = <0 0xe6052000 0 0x50>;
221 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
222 #gpio-cells = <2>;
223 gpio-controller;
224 gpio-ranges = <&pfc 0 64 30>;
225 #interrupt-cells = <2>;
226 interrupt-controller;
227 clocks = <&mstp9_clks R8A7790_CLK_GPIO2>;
228 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
229 };
230
231 gpio3: gpio@e6053000 {
232 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
233 reg = <0 0xe6053000 0 0x50>;
234 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
235 #gpio-cells = <2>;
236 gpio-controller;
237 gpio-ranges = <&pfc 0 96 32>;
238 #interrupt-cells = <2>;
239 interrupt-controller;
240 clocks = <&mstp9_clks R8A7790_CLK_GPIO3>;
241 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
242 };
243
244 gpio4: gpio@e6054000 {
245 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
246 reg = <0 0xe6054000 0 0x50>;
247 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
248 #gpio-cells = <2>;
249 gpio-controller;
250 gpio-ranges = <&pfc 0 128 32>;
251 #interrupt-cells = <2>;
252 interrupt-controller;
253 clocks = <&mstp9_clks R8A7790_CLK_GPIO4>;
254 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
255 };
256
257 gpio5: gpio@e6055000 {
258 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
259 reg = <0 0xe6055000 0 0x50>;
260 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
261 #gpio-cells = <2>;
262 gpio-controller;
263 gpio-ranges = <&pfc 0 160 32>;
264 #interrupt-cells = <2>;
265 interrupt-controller;
266 clocks = <&mstp9_clks R8A7790_CLK_GPIO5>;
267 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
268 };
269
270 thermal: thermal@e61f0000 {
271 compatible = "renesas,thermal-r8a7790",
272 "renesas,rcar-gen2-thermal",
273 "renesas,rcar-thermal";
274 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
275 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
276 clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
277 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
278 #thermal-sensor-cells = <0>;
279 };
280
281 timer {
282 compatible = "arm,armv7-timer";
283 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
284 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
285 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
286 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
287 };
288
289 cmt0: timer@ffca0000 {
290 compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
291 reg = <0 0xffca0000 0 0x1004>;
292 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
293 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
294 clocks = <&mstp1_clks R8A7790_CLK_CMT0>;
295 clock-names = "fck";
296 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
297
298 renesas,channels-mask = <0x60>;
299
300 status = "disabled";
301 };
302
303 cmt1: timer@e6130000 {
304 compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
305 reg = <0 0xe6130000 0 0x1004>;
306 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
307 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
308 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
309 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
310 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
311 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
312 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
313 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
314 clocks = <&mstp3_clks R8A7790_CLK_CMT1>;
315 clock-names = "fck";
316 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
317
318 renesas,channels-mask = <0xff>;
319
320 status = "disabled";
321 };
322
323 irqc0: interrupt-controller@e61c0000 {
324 compatible = "renesas,irqc-r8a7790", "renesas,irqc";
325 #interrupt-cells = <2>;
326 interrupt-controller;
327 reg = <0 0xe61c0000 0 0x200>;
328 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
329 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
330 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
331 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
332 clocks = <&mstp4_clks R8A7790_CLK_IRQC>;
333 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
334 };
335
336 dmac0: dma-controller@e6700000 {
337 compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
338 reg = <0 0xe6700000 0 0x20000>;
339 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
340 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
341 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
342 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
343 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
344 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
345 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
346 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
347 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
348 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
349 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
350 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
351 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
352 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
353 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
354 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
355 interrupt-names = "error",
356 "ch0", "ch1", "ch2", "ch3",
357 "ch4", "ch5", "ch6", "ch7",
358 "ch8", "ch9", "ch10", "ch11",
359 "ch12", "ch13", "ch14";
360 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>;
361 clock-names = "fck";
362 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
363 #dma-cells = <1>;
364 dma-channels = <15>;
365 };
366
367 dmac1: dma-controller@e6720000 {
368 compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
369 reg = <0 0xe6720000 0 0x20000>;
370 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
371 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
372 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
373 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
374 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
375 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
376 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
377 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
378 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
379 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
380 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
381 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
382 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
383 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
384 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
385 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
386 interrupt-names = "error",
387 "ch0", "ch1", "ch2", "ch3",
388 "ch4", "ch5", "ch6", "ch7",
389 "ch8", "ch9", "ch10", "ch11",
390 "ch12", "ch13", "ch14";
391 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>;
392 clock-names = "fck";
393 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
394 #dma-cells = <1>;
395 dma-channels = <15>;
396 };
397
398 audma0: dma-controller@ec700000 {
399 compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
400 reg = <0 0xec700000 0 0x10000>;
401 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
402 GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
403 GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
404 GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
405 GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
406 GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
407 GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
408 GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
409 GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
410 GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
411 GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
412 GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
413 GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
414 GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
415 interrupt-names = "error",
416 "ch0", "ch1", "ch2", "ch3",
417 "ch4", "ch5", "ch6", "ch7",
418 "ch8", "ch9", "ch10", "ch11",
419 "ch12";
420 clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC0>;
421 clock-names = "fck";
422 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
423 #dma-cells = <1>;
424 dma-channels = <13>;
425 };
426
427 audma1: dma-controller@ec720000 {
428 compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
429 reg = <0 0xec720000 0 0x10000>;
430 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
431 GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
432 GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
433 GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
434 GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
435 GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
436 GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
437 GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
438 GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
439 GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
440 GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
441 GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
442 GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
443 GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
444 interrupt-names = "error",
445 "ch0", "ch1", "ch2", "ch3",
446 "ch4", "ch5", "ch6", "ch7",
447 "ch8", "ch9", "ch10", "ch11",
448 "ch12";
449 clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC1>;
450 clock-names = "fck";
451 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
452 #dma-cells = <1>;
453 dma-channels = <13>;
454 };
455
456 usb_dmac0: dma-controller@e65a0000 {
457 compatible = "renesas,r8a7790-usb-dmac", "renesas,usb-dmac";
458 reg = <0 0xe65a0000 0 0x100>;
459 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
460 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
461 interrupt-names = "ch0", "ch1";
462 clocks = <&mstp3_clks R8A7790_CLK_USBDMAC0>;
463 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
464 #dma-cells = <1>;
465 dma-channels = <2>;
466 };
467
468 usb_dmac1: dma-controller@e65b0000 {
469 compatible = "renesas,r8a7790-usb-dmac", "renesas,usb-dmac";
470 reg = <0 0xe65b0000 0 0x100>;
471 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
472 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
473 interrupt-names = "ch0", "ch1";
474 clocks = <&mstp3_clks R8A7790_CLK_USBDMAC1>;
475 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
476 #dma-cells = <1>;
477 dma-channels = <2>;
478 };
479
480 i2c0: i2c@e6508000 {
481 #address-cells = <1>;
482 #size-cells = <0>;
483 compatible = "renesas,i2c-r8a7790";
484 reg = <0 0xe6508000 0 0x40>;
485 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
486 clocks = <&mstp9_clks R8A7790_CLK_I2C0>;
487 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
488 i2c-scl-internal-delay-ns = <110>;
489 status = "disabled";
490 };
491
492 i2c1: i2c@e6518000 {
493 #address-cells = <1>;
494 #size-cells = <0>;
495 compatible = "renesas,i2c-r8a7790";
496 reg = <0 0xe6518000 0 0x40>;
497 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
498 clocks = <&mstp9_clks R8A7790_CLK_I2C1>;
499 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
500 i2c-scl-internal-delay-ns = <6>;
501 status = "disabled";
502 };
503
504 i2c2: i2c@e6530000 {
505 #address-cells = <1>;
506 #size-cells = <0>;
507 compatible = "renesas,i2c-r8a7790";
508 reg = <0 0xe6530000 0 0x40>;
509 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
510 clocks = <&mstp9_clks R8A7790_CLK_I2C2>;
511 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
512 i2c-scl-internal-delay-ns = <6>;
513 status = "disabled";
514 };
515
516 i2c3: i2c@e6540000 {
517 #address-cells = <1>;
518 #size-cells = <0>;
519 compatible = "renesas,i2c-r8a7790";
520 reg = <0 0xe6540000 0 0x40>;
521 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
522 clocks = <&mstp9_clks R8A7790_CLK_I2C3>;
523 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
524 i2c-scl-internal-delay-ns = <110>;
525 status = "disabled";
526 };
527
528 iic0: i2c@e6500000 {
529 #address-cells = <1>;
530 #size-cells = <0>;
531 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
532 reg = <0 0xe6500000 0 0x425>;
533 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
534 clocks = <&mstp3_clks R8A7790_CLK_IIC0>;
535 dmas = <&dmac0 0x61>, <&dmac0 0x62>,
536 <&dmac1 0x61>, <&dmac1 0x62>;
537 dma-names = "tx", "rx", "tx", "rx";
538 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
539 status = "disabled";
540 };
541
542 iic1: i2c@e6510000 {
543 #address-cells = <1>;
544 #size-cells = <0>;
545 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
546 reg = <0 0xe6510000 0 0x425>;
547 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
548 clocks = <&mstp3_clks R8A7790_CLK_IIC1>;
549 dmas = <&dmac0 0x65>, <&dmac0 0x66>,
550 <&dmac1 0x65>, <&dmac1 0x66>;
551 dma-names = "tx", "rx", "tx", "rx";
552 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
553 status = "disabled";
554 };
555
556 iic2: i2c@e6520000 {
557 #address-cells = <1>;
558 #size-cells = <0>;
559 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
560 reg = <0 0xe6520000 0 0x425>;
561 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
562 clocks = <&mstp3_clks R8A7790_CLK_IIC2>;
563 dmas = <&dmac0 0x69>, <&dmac0 0x6a>,
564 <&dmac1 0x69>, <&dmac1 0x6a>;
565 dma-names = "tx", "rx", "tx", "rx";
566 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
567 status = "disabled";
568 };
569
570 iic3: i2c@e60b0000 {
571 #address-cells = <1>;
572 #size-cells = <0>;
573 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
574 reg = <0 0xe60b0000 0 0x425>;
575 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
576 clocks = <&mstp9_clks R8A7790_CLK_IICDVFS>;
577 dmas = <&dmac0 0x77>, <&dmac0 0x78>,
578 <&dmac1 0x77>, <&dmac1 0x78>;
579 dma-names = "tx", "rx", "tx", "rx";
580 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
581 status = "disabled";
582 };
583
584 mmcif0: mmc@ee200000 {
585 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
586 reg = <0 0xee200000 0 0x80>;
587 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
588 clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>;
589 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
590 <&dmac1 0xd1>, <&dmac1 0xd2>;
591 dma-names = "tx", "rx", "tx", "rx";
592 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
593 reg-io-width = <4>;
594 status = "disabled";
595 max-frequency = <97500000>;
596 };
597
598 mmcif1: mmc@ee220000 {
599 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
600 reg = <0 0xee220000 0 0x80>;
601 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
602 clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>;
603 dmas = <&dmac0 0xe1>, <&dmac0 0xe2>,
604 <&dmac1 0xe1>, <&dmac1 0xe2>;
605 dma-names = "tx", "rx", "tx", "rx";
606 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
607 reg-io-width = <4>;
608 status = "disabled";
609 max-frequency = <97500000>;
610 };
611
612 pfc: pfc@e6060000 {
613 compatible = "renesas,pfc-r8a7790";
614 reg = <0 0xe6060000 0 0x250>;
615 };
616
617 sdhi0: sd@ee100000 {
618 compatible = "renesas,sdhi-r8a7790";
619 reg = <0 0xee100000 0 0x328>;
620 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
621 clocks = <&mstp3_clks R8A7790_CLK_SDHI0>;
622 dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
623 <&dmac1 0xcd>, <&dmac1 0xce>;
624 dma-names = "tx", "rx", "tx", "rx";
625 max-frequency = <195000000>;
626 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
627 status = "disabled";
628 };
629
630 sdhi1: sd@ee120000 {
631 compatible = "renesas,sdhi-r8a7790";
632 reg = <0 0xee120000 0 0x328>;
633 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
634 clocks = <&mstp3_clks R8A7790_CLK_SDHI1>;
635 dmas = <&dmac0 0xc9>, <&dmac0 0xca>,
636 <&dmac1 0xc9>, <&dmac1 0xca>;
637 dma-names = "tx", "rx", "tx", "rx";
638 max-frequency = <195000000>;
639 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
640 status = "disabled";
641 };
642
643 sdhi2: sd@ee140000 {
644 compatible = "renesas,sdhi-r8a7790";
645 reg = <0 0xee140000 0 0x100>;
646 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
647 clocks = <&mstp3_clks R8A7790_CLK_SDHI2>;
648 dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
649 <&dmac1 0xc1>, <&dmac1 0xc2>;
650 dma-names = "tx", "rx", "tx", "rx";
651 max-frequency = <97500000>;
652 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
653 status = "disabled";
654 };
655
656 sdhi3: sd@ee160000 {
657 compatible = "renesas,sdhi-r8a7790";
658 reg = <0 0xee160000 0 0x100>;
659 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
660 clocks = <&mstp3_clks R8A7790_CLK_SDHI3>;
661 dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
662 <&dmac1 0xd3>, <&dmac1 0xd4>;
663 dma-names = "tx", "rx", "tx", "rx";
664 max-frequency = <97500000>;
665 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
666 status = "disabled";
667 };
668
669 scifa0: serial@e6c40000 {
670 compatible = "renesas,scifa-r8a7790",
671 "renesas,rcar-gen2-scifa", "renesas,scifa";
672 reg = <0 0xe6c40000 0 64>;
673 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
674 clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>;
675 clock-names = "fck";
676 dmas = <&dmac0 0x21>, <&dmac0 0x22>,
677 <&dmac1 0x21>, <&dmac1 0x22>;
678 dma-names = "tx", "rx", "tx", "rx";
679 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
680 status = "disabled";
681 };
682
683 scifa1: serial@e6c50000 {
684 compatible = "renesas,scifa-r8a7790",
685 "renesas,rcar-gen2-scifa", "renesas,scifa";
686 reg = <0 0xe6c50000 0 64>;
687 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
688 clocks = <&mstp2_clks R8A7790_CLK_SCIFA1>;
689 clock-names = "fck";
690 dmas = <&dmac0 0x25>, <&dmac0 0x26>,
691 <&dmac1 0x25>, <&dmac1 0x26>;
692 dma-names = "tx", "rx", "tx", "rx";
693 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
694 status = "disabled";
695 };
696
697 scifa2: serial@e6c60000 {
698 compatible = "renesas,scifa-r8a7790",
699 "renesas,rcar-gen2-scifa", "renesas,scifa";
700 reg = <0 0xe6c60000 0 64>;
701 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
702 clocks = <&mstp2_clks R8A7790_CLK_SCIFA2>;
703 clock-names = "fck";
704 dmas = <&dmac0 0x27>, <&dmac0 0x28>,
705 <&dmac1 0x27>, <&dmac1 0x28>;
706 dma-names = "tx", "rx", "tx", "rx";
707 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
708 status = "disabled";
709 };
710
711 scifb0: serial@e6c20000 {
712 compatible = "renesas,scifb-r8a7790",
713 "renesas,rcar-gen2-scifb", "renesas,scifb";
714 reg = <0 0xe6c20000 0 0x100>;
715 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
716 clocks = <&mstp2_clks R8A7790_CLK_SCIFB0>;
717 clock-names = "fck";
718 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
719 <&dmac1 0x3d>, <&dmac1 0x3e>;
720 dma-names = "tx", "rx", "tx", "rx";
721 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
722 status = "disabled";
723 };
724
725 scifb1: serial@e6c30000 {
726 compatible = "renesas,scifb-r8a7790",
727 "renesas,rcar-gen2-scifb", "renesas,scifb";
728 reg = <0 0xe6c30000 0 0x100>;
729 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
730 clocks = <&mstp2_clks R8A7790_CLK_SCIFB1>;
731 clock-names = "fck";
732 dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
733 <&dmac1 0x19>, <&dmac1 0x1a>;
734 dma-names = "tx", "rx", "tx", "rx";
735 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
736 status = "disabled";
737 };
738
739 scifb2: serial@e6ce0000 {
740 compatible = "renesas,scifb-r8a7790",
741 "renesas,rcar-gen2-scifb", "renesas,scifb";
742 reg = <0 0xe6ce0000 0 0x100>;
743 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
744 clocks = <&mstp2_clks R8A7790_CLK_SCIFB2>;
745 clock-names = "fck";
746 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
747 <&dmac1 0x1d>, <&dmac1 0x1e>;
748 dma-names = "tx", "rx", "tx", "rx";
749 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
750 status = "disabled";
751 };
752
753 scif0: serial@e6e60000 {
754 compatible = "renesas,scif-r8a7790", "renesas,rcar-gen2-scif",
755 "renesas,scif";
756 reg = <0 0xe6e60000 0 64>;
757 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
758 clocks = <&mstp7_clks R8A7790_CLK_SCIF0>, <&zs_clk>,
759 <&scif_clk>;
760 clock-names = "fck", "brg_int", "scif_clk";
761 dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
762 <&dmac1 0x29>, <&dmac1 0x2a>;
763 dma-names = "tx", "rx", "tx", "rx";
764 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
765 status = "disabled";
766 };
767
768 scif1: serial@e6e68000 {
769 compatible = "renesas,scif-r8a7790", "renesas,rcar-gen2-scif",
770 "renesas,scif";
771 reg = <0 0xe6e68000 0 64>;
772 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
773 clocks = <&mstp7_clks R8A7790_CLK_SCIF1>, <&zs_clk>,
774 <&scif_clk>;
775 clock-names = "fck", "brg_int", "scif_clk";
776 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
777 <&dmac1 0x2d>, <&dmac1 0x2e>;
778 dma-names = "tx", "rx", "tx", "rx";
779 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
780 status = "disabled";
781 };
782
783 scif2: serial@e6e56000 {
784 compatible = "renesas,scif-r8a7790", "renesas,rcar-gen2-scif",
785 "renesas,scif";
786 reg = <0 0xe6e56000 0 64>;
787 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
788 clocks = <&mstp3_clks R8A7790_CLK_SCIF2>, <&zs_clk>,
789 <&scif_clk>;
790 clock-names = "fck", "brg_int", "scif_clk";
791 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
792 <&dmac1 0x2b>, <&dmac1 0x2c>;
793 dma-names = "tx", "rx", "tx", "rx";
794 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
795 status = "disabled";
796 };
797
798 hscif0: serial@e62c0000 {
799 compatible = "renesas,hscif-r8a7790",
800 "renesas,rcar-gen2-hscif", "renesas,hscif";
801 reg = <0 0xe62c0000 0 96>;
802 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
803 clocks = <&mstp7_clks R8A7790_CLK_HSCIF0>, <&zs_clk>,
804 <&scif_clk>;
805 clock-names = "fck", "brg_int", "scif_clk";
806 dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
807 <&dmac1 0x39>, <&dmac1 0x3a>;
808 dma-names = "tx", "rx", "tx", "rx";
809 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
810 status = "disabled";
811 };
812
813 hscif1: serial@e62c8000 {
814 compatible = "renesas,hscif-r8a7790",
815 "renesas,rcar-gen2-hscif", "renesas,hscif";
816 reg = <0 0xe62c8000 0 96>;
817 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
818 clocks = <&mstp7_clks R8A7790_CLK_HSCIF1>, <&zs_clk>,
819 <&scif_clk>;
820 clock-names = "fck", "brg_int", "scif_clk";
821 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
822 <&dmac1 0x4d>, <&dmac1 0x4e>;
823 dma-names = "tx", "rx", "tx", "rx";
824 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
825 status = "disabled";
826 };
827
828 ether: ethernet@ee700000 {
829 compatible = "renesas,ether-r8a7790";
830 reg = <0 0xee700000 0 0x400>;
831 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
832 clocks = <&mstp8_clks R8A7790_CLK_ETHER>;
833 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
834 phy-mode = "rmii";
835 #address-cells = <1>;
836 #size-cells = <0>;
837 status = "disabled";
838 };
839
840 avb: ethernet@e6800000 {
841 compatible = "renesas,etheravb-r8a7790",
842 "renesas,etheravb-rcar-gen2";
843 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
844 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
845 clocks = <&mstp8_clks R8A7790_CLK_ETHERAVB>;
846 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
847 #address-cells = <1>;
848 #size-cells = <0>;
849 status = "disabled";
850 };
851
852 sata0: sata@ee300000 {
853 compatible = "renesas,sata-r8a7790";
854 reg = <0 0xee300000 0 0x2000>;
855 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
856 clocks = <&mstp8_clks R8A7790_CLK_SATA0>;
857 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
858 status = "disabled";
859 };
860
861 sata1: sata@ee500000 {
862 compatible = "renesas,sata-r8a7790";
863 reg = <0 0xee500000 0 0x2000>;
864 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
865 clocks = <&mstp8_clks R8A7790_CLK_SATA1>;
866 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
867 status = "disabled";
868 };
869
870 hsusb: usb@e6590000 {
871 compatible = "renesas,usbhs-r8a7790", "renesas,rcar-gen2-usbhs";
872 reg = <0 0xe6590000 0 0x100>;
873 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
874 clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
875 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
876 <&usb_dmac1 0>, <&usb_dmac1 1>;
877 dma-names = "ch0", "ch1", "ch2", "ch3";
878 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
879 renesas,buswait = <4>;
880 phys = <&usb0 1>;
881 phy-names = "usb";
882 status = "disabled";
883 };
884
885 usbphy: usb-phy@e6590100 {
886 compatible = "renesas,usb-phy-r8a7790";
887 reg = <0 0xe6590100 0 0x100>;
888 #address-cells = <1>;
889 #size-cells = <0>;
890 clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
891 clock-names = "usbhs";
892 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
893 status = "disabled";
894
895 usb0: usb-channel@0 {
896 reg = <0>;
897 #phy-cells = <1>;
898 };
899 usb2: usb-channel@2 {
900 reg = <2>;
901 #phy-cells = <1>;
902 };
903 };
904
905 vin0: video@e6ef0000 {
906 compatible = "renesas,vin-r8a7790";
907 reg = <0 0xe6ef0000 0 0x1000>;
908 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
909 clocks = <&mstp8_clks R8A7790_CLK_VIN0>;
910 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
911 status = "disabled";
912 };
913
914 vin1: video@e6ef1000 {
915 compatible = "renesas,vin-r8a7790";
916 reg = <0 0xe6ef1000 0 0x1000>;
917 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
918 clocks = <&mstp8_clks R8A7790_CLK_VIN1>;
919 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
920 status = "disabled";
921 };
922
923 vin2: video@e6ef2000 {
924 compatible = "renesas,vin-r8a7790";
925 reg = <0 0xe6ef2000 0 0x1000>;
926 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
927 clocks = <&mstp8_clks R8A7790_CLK_VIN2>;
928 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
929 status = "disabled";
930 };
931
932 vin3: video@e6ef3000 {
933 compatible = "renesas,vin-r8a7790";
934 reg = <0 0xe6ef3000 0 0x1000>;
935 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
936 clocks = <&mstp8_clks R8A7790_CLK_VIN3>;
937 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
938 status = "disabled";
939 };
940
941 vsp1@fe920000 {
942 compatible = "renesas,vsp1";
943 reg = <0 0xfe920000 0 0x8000>;
944 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
945 clocks = <&mstp1_clks R8A7790_CLK_VSP1_R>;
946 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
947 };
948
949 vsp1@fe928000 {
950 compatible = "renesas,vsp1";
951 reg = <0 0xfe928000 0 0x8000>;
952 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
953 clocks = <&mstp1_clks R8A7790_CLK_VSP1_S>;
954 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
955 };
956
957 vsp1@fe930000 {
958 compatible = "renesas,vsp1";
959 reg = <0 0xfe930000 0 0x8000>;
960 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
961 clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU0>;
962 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
963 };
964
965 vsp1@fe938000 {
966 compatible = "renesas,vsp1";
967 reg = <0 0xfe938000 0 0x8000>;
968 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
969 clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU1>;
970 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
971 };
972
973 du: display@feb00000 {
974 compatible = "renesas,du-r8a7790";
975 reg = <0 0xfeb00000 0 0x70000>,
976 <0 0xfeb90000 0 0x1c>,
977 <0 0xfeb94000 0 0x1c>;
978 reg-names = "du", "lvds.0", "lvds.1";
979 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
980 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
981 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
982 clocks = <&mstp7_clks R8A7790_CLK_DU0>,
983 <&mstp7_clks R8A7790_CLK_DU1>,
984 <&mstp7_clks R8A7790_CLK_DU2>,
985 <&mstp7_clks R8A7790_CLK_LVDS0>,
986 <&mstp7_clks R8A7790_CLK_LVDS1>;
987 clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1";
988 status = "disabled";
989
990 ports {
991 #address-cells = <1>;
992 #size-cells = <0>;
993
994 port@0 {
995 reg = <0>;
996 du_out_rgb: endpoint {
997 };
998 };
999 port@1 {
1000 reg = <1>;
1001 du_out_lvds0: endpoint {
1002 };
1003 };
1004 port@2 {
1005 reg = <2>;
1006 du_out_lvds1: endpoint {
1007 };
1008 };
1009 };
1010 };
1011
1012 can0: can@e6e80000 {
1013 compatible = "renesas,can-r8a7790", "renesas,rcar-gen2-can";
1014 reg = <0 0xe6e80000 0 0x1000>;
1015 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
1016 clocks = <&mstp9_clks R8A7790_CLK_RCAN0>,
1017 <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>;
1018 clock-names = "clkp1", "clkp2", "can_clk";
1019 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1020 status = "disabled";
1021 };
1022
1023 can1: can@e6e88000 {
1024 compatible = "renesas,can-r8a7790", "renesas,rcar-gen2-can";
1025 reg = <0 0xe6e88000 0 0x1000>;
1026 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
1027 clocks = <&mstp9_clks R8A7790_CLK_RCAN1>,
1028 <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>;
1029 clock-names = "clkp1", "clkp2", "can_clk";
1030 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1031 status = "disabled";
1032 };
1033
1034 jpu: jpeg-codec@fe980000 {
1035 compatible = "renesas,jpu-r8a7790", "renesas,rcar-gen2-jpu";
1036 reg = <0 0xfe980000 0 0x10300>;
1037 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
1038 clocks = <&mstp1_clks R8A7790_CLK_JPU>;
1039 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1040 };
1041
1042 clocks {
1043 #address-cells = <2>;
1044 #size-cells = <2>;
1045 ranges;
1046
1047 /* External root clock */
1048 extal_clk: extal {
1049 compatible = "fixed-clock";
1050 #clock-cells = <0>;
1051 /* This value must be overriden by the board. */
1052 clock-frequency = <0>;
1053 };
1054
1055 /* External PCIe clock - can be overridden by the board */
1056 pcie_bus_clk: pcie_bus {
1057 compatible = "fixed-clock";
1058 #clock-cells = <0>;
1059 clock-frequency = <0>;
1060 };
1061
1062 /*
1063 * The external audio clocks are configured as 0 Hz fixed frequency clocks by
1064 * default. Boards that provide audio clocks should override them.
1065 */
1066 audio_clk_a: audio_clk_a {
1067 compatible = "fixed-clock";
1068 #clock-cells = <0>;
1069 clock-frequency = <0>;
1070 };
1071 audio_clk_b: audio_clk_b {
1072 compatible = "fixed-clock";
1073 #clock-cells = <0>;
1074 clock-frequency = <0>;
1075 };
1076 audio_clk_c: audio_clk_c {
1077 compatible = "fixed-clock";
1078 #clock-cells = <0>;
1079 clock-frequency = <0>;
1080 };
1081
1082 /* External SCIF clock */
1083 scif_clk: scif {
1084 compatible = "fixed-clock";
1085 #clock-cells = <0>;
1086 /* This value must be overridden by the board. */
1087 clock-frequency = <0>;
1088 };
1089
1090 /* External USB clock - can be overridden by the board */
1091 usb_extal_clk: usb_extal {
1092 compatible = "fixed-clock";
1093 #clock-cells = <0>;
1094 clock-frequency = <48000000>;
1095 };
1096
1097 /* External CAN clock */
1098 can_clk: can_clk {
1099 compatible = "fixed-clock";
1100 #clock-cells = <0>;
1101 /* This value must be overridden by the board. */
1102 clock-frequency = <0>;
1103 };
1104
1105 /* Special CPG clocks */
1106 cpg_clocks: cpg_clocks@e6150000 {
1107 compatible = "renesas,r8a7790-cpg-clocks",
1108 "renesas,rcar-gen2-cpg-clocks";
1109 reg = <0 0xe6150000 0 0x1000>;
1110 clocks = <&extal_clk &usb_extal_clk>;
1111 #clock-cells = <1>;
1112 clock-output-names = "main", "pll0", "pll1", "pll3",
1113 "lb", "qspi", "sdh", "sd0", "sd1",
1114 "z", "rcan", "adsp";
1115 #power-domain-cells = <0>;
1116 };
1117
1118 /* Variable factor clocks */
1119 sd2_clk: sd2@e6150078 {
1120 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1121 reg = <0 0xe6150078 0 4>;
1122 clocks = <&pll1_div2_clk>;
1123 #clock-cells = <0>;
1124 };
1125 sd3_clk: sd3@e615026c {
1126 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1127 reg = <0 0xe615026c 0 4>;
1128 clocks = <&pll1_div2_clk>;
1129 #clock-cells = <0>;
1130 };
1131 mmc0_clk: mmc0@e6150240 {
1132 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1133 reg = <0 0xe6150240 0 4>;
1134 clocks = <&pll1_div2_clk>;
1135 #clock-cells = <0>;
1136 };
1137 mmc1_clk: mmc1@e6150244 {
1138 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1139 reg = <0 0xe6150244 0 4>;
1140 clocks = <&pll1_div2_clk>;
1141 #clock-cells = <0>;
1142 };
1143 ssp_clk: ssp@e6150248 {
1144 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1145 reg = <0 0xe6150248 0 4>;
1146 clocks = <&pll1_div2_clk>;
1147 #clock-cells = <0>;
1148 };
1149 ssprs_clk: ssprs@e615024c {
1150 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1151 reg = <0 0xe615024c 0 4>;
1152 clocks = <&pll1_div2_clk>;
1153 #clock-cells = <0>;
1154 };
1155
1156 /* Fixed factor clocks */
1157 pll1_div2_clk: pll1_div2 {
1158 compatible = "fixed-factor-clock";
1159 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1160 #clock-cells = <0>;
1161 clock-div = <2>;
1162 clock-mult = <1>;
1163 };
1164 z2_clk: z2 {
1165 compatible = "fixed-factor-clock";
1166 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1167 #clock-cells = <0>;
1168 clock-div = <2>;
1169 clock-mult = <1>;
1170 };
1171 zg_clk: zg {
1172 compatible = "fixed-factor-clock";
1173 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1174 #clock-cells = <0>;
1175 clock-div = <3>;
1176 clock-mult = <1>;
1177 };
1178 zx_clk: zx {
1179 compatible = "fixed-factor-clock";
1180 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1181 #clock-cells = <0>;
1182 clock-div = <3>;
1183 clock-mult = <1>;
1184 };
1185 zs_clk: zs {
1186 compatible = "fixed-factor-clock";
1187 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1188 #clock-cells = <0>;
1189 clock-div = <6>;
1190 clock-mult = <1>;
1191 };
1192 hp_clk: hp {
1193 compatible = "fixed-factor-clock";
1194 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1195 #clock-cells = <0>;
1196 clock-div = <12>;
1197 clock-mult = <1>;
1198 };
1199 i_clk: i {
1200 compatible = "fixed-factor-clock";
1201 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1202 #clock-cells = <0>;
1203 clock-div = <2>;
1204 clock-mult = <1>;
1205 };
1206 b_clk: b {
1207 compatible = "fixed-factor-clock";
1208 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1209 #clock-cells = <0>;
1210 clock-div = <12>;
1211 clock-mult = <1>;
1212 };
1213 p_clk: p {
1214 compatible = "fixed-factor-clock";
1215 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1216 #clock-cells = <0>;
1217 clock-div = <24>;
1218 clock-mult = <1>;
1219 };
1220 cl_clk: cl {
1221 compatible = "fixed-factor-clock";
1222 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1223 #clock-cells = <0>;
1224 clock-div = <48>;
1225 clock-mult = <1>;
1226 };
1227 m2_clk: m2 {
1228 compatible = "fixed-factor-clock";
1229 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1230 #clock-cells = <0>;
1231 clock-div = <8>;
1232 clock-mult = <1>;
1233 };
1234 imp_clk: imp {
1235 compatible = "fixed-factor-clock";
1236 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1237 #clock-cells = <0>;
1238 clock-div = <4>;
1239 clock-mult = <1>;
1240 };
1241 rclk_clk: rclk {
1242 compatible = "fixed-factor-clock";
1243 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1244 #clock-cells = <0>;
1245 clock-div = <(48 * 1024)>;
1246 clock-mult = <1>;
1247 };
1248 oscclk_clk: oscclk {
1249 compatible = "fixed-factor-clock";
1250 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1251 #clock-cells = <0>;
1252 clock-div = <(12 * 1024)>;
1253 clock-mult = <1>;
1254 };
1255 zb3_clk: zb3 {
1256 compatible = "fixed-factor-clock";
1257 clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
1258 #clock-cells = <0>;
1259 clock-div = <4>;
1260 clock-mult = <1>;
1261 };
1262 zb3d2_clk: zb3d2 {
1263 compatible = "fixed-factor-clock";
1264 clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
1265 #clock-cells = <0>;
1266 clock-div = <8>;
1267 clock-mult = <1>;
1268 };
1269 ddr_clk: ddr {
1270 compatible = "fixed-factor-clock";
1271 clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
1272 #clock-cells = <0>;
1273 clock-div = <8>;
1274 clock-mult = <1>;
1275 };
1276 mp_clk: mp {
1277 compatible = "fixed-factor-clock";
1278 clocks = <&pll1_div2_clk>;
1279 #clock-cells = <0>;
1280 clock-div = <15>;
1281 clock-mult = <1>;
1282 };
1283 cp_clk: cp {
1284 compatible = "fixed-factor-clock";
1285 clocks = <&extal_clk>;
1286 #clock-cells = <0>;
1287 clock-div = <2>;
1288 clock-mult = <1>;
1289 };
1290
1291 /* Gate clocks */
1292 mstp0_clks: mstp0_clks@e6150130 {
1293 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1294 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
1295 clocks = <&mp_clk>;
1296 #clock-cells = <1>;
1297 clock-indices = <R8A7790_CLK_MSIOF0>;
1298 clock-output-names = "msiof0";
1299 };
1300 mstp1_clks: mstp1_clks@e6150134 {
1301 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1302 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
1303 clocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&m2_clk>,
1304 <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>, <&zs_clk>,
1305 <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
1306 <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
1307 #clock-cells = <1>;
1308 clock-indices = <
1309 R8A7790_CLK_VCP1 R8A7790_CLK_VCP0 R8A7790_CLK_VPC1
1310 R8A7790_CLK_VPC0 R8A7790_CLK_JPU R8A7790_CLK_SSP1
1311 R8A7790_CLK_TMU1 R8A7790_CLK_3DG R8A7790_CLK_2DDMAC
1312 R8A7790_CLK_FDP1_2 R8A7790_CLK_FDP1_1 R8A7790_CLK_FDP1_0
1313 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2 R8A7790_CLK_CMT0
1314 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1 R8A7790_CLK_VSP1_DU0
1315 R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S
1316 >;
1317 clock-output-names =
1318 "vcp1", "vcp0", "vpc1", "vpc0", "jpu", "ssp1",
1319 "tmu1", "3dg", "2ddmac", "fdp1-2", "fdp1-1",
1320 "fdp1-0", "tmu3", "tmu2", "cmt0", "tmu0",
1321 "vsp1-du1", "vsp1-du0", "vsp1-rt", "vsp1-sy";
1322 };
1323 mstp2_clks: mstp2_clks@e6150138 {
1324 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1325 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
1326 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
1327 <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&zs_clk>,
1328 <&zs_clk>;
1329 #clock-cells = <1>;
1330 clock-indices = <
1331 R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0
1332 R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1
1333 R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2
1334 R8A7790_CLK_SYS_DMAC1 R8A7790_CLK_SYS_DMAC0
1335 >;
1336 clock-output-names =
1337 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
1338 "scifb1", "msiof1", "msiof3", "scifb2",
1339 "sys-dmac1", "sys-dmac0";
1340 };
1341 mstp3_clks: mstp3_clks@e615013c {
1342 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1343 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
1344 clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&p_clk>, <&sd3_clk>,
1345 <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>,
1346 <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>,
1347 <&hp_clk>, <&hp_clk>;
1348 #clock-cells = <1>;
1349 clock-indices = <
1350 R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SCIF2 R8A7790_CLK_SDHI3
1351 R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0
1352 R8A7790_CLK_IIC0 R8A7790_CLK_PCIEC R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1
1353 R8A7790_CLK_USBDMAC0 R8A7790_CLK_USBDMAC1
1354 >;
1355 clock-output-names =
1356 "iic2", "tpu0", "mmcif1", "scif2", "sdhi3",
1357 "sdhi2", "sdhi1", "sdhi0", "mmcif0",
1358 "iic0", "pciec", "iic1", "ssusb", "cmt1",
1359 "usbdmac0", "usbdmac1";
1360 };
1361 mstp4_clks: mstp4_clks@e6150140 {
1362 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1363 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
1364 clocks = <&cp_clk>;
1365 #clock-cells = <1>;
1366 clock-indices = <R8A7790_CLK_IRQC>;
1367 clock-output-names = "irqc";
1368 };
1369 mstp5_clks: mstp5_clks@e6150144 {
1370 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1371 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
1372 clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7790_CLK_ADSP>,
1373 <&extal_clk>, <&p_clk>;
1374 #clock-cells = <1>;
1375 clock-indices = <
1376 R8A7790_CLK_AUDIO_DMAC0 R8A7790_CLK_AUDIO_DMAC1
1377 R8A7790_CLK_ADSP_MOD R8A7790_CLK_THERMAL
1378 R8A7790_CLK_PWM
1379 >;
1380 clock-output-names = "audmac0", "audmac1", "adsp_mod",
1381 "thermal", "pwm";
1382 };
1383 mstp7_clks: mstp7_clks@e615014c {
1384 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1385 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
1386 clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
1387 <&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>,
1388 <&zx_clk>;
1389 #clock-cells = <1>;
1390 clock-indices = <
1391 R8A7790_CLK_EHCI R8A7790_CLK_HSUSB R8A7790_CLK_HSCIF1
1392 R8A7790_CLK_HSCIF0 R8A7790_CLK_SCIF1 R8A7790_CLK_SCIF0
1393 R8A7790_CLK_DU2 R8A7790_CLK_DU1 R8A7790_CLK_DU0
1394 R8A7790_CLK_LVDS1 R8A7790_CLK_LVDS0
1395 >;
1396 clock-output-names =
1397 "ehci", "hsusb", "hscif1", "hscif0", "scif1",
1398 "scif0", "du2", "du1", "du0", "lvds1", "lvds0";
1399 };
1400 mstp8_clks: mstp8_clks@e6150990 {
1401 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1402 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
1403 clocks = <&hp_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
1404 <&zg_clk>, <&hp_clk>, <&p_clk>, <&zs_clk>,
1405 <&zs_clk>;
1406 #clock-cells = <1>;
1407 clock-indices = <
1408 R8A7790_CLK_MLB R8A7790_CLK_VIN3 R8A7790_CLK_VIN2
1409 R8A7790_CLK_VIN1 R8A7790_CLK_VIN0
1410 R8A7790_CLK_ETHERAVB R8A7790_CLK_ETHER
1411 R8A7790_CLK_SATA1 R8A7790_CLK_SATA0
1412 >;
1413 clock-output-names =
1414 "mlb", "vin3", "vin2", "vin1", "vin0",
1415 "etheravb", "ether", "sata1", "sata0";
1416 };
1417 mstp9_clks: mstp9_clks@e6150994 {
1418 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1419 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
1420 clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>,
1421 <&cp_clk>, <&cp_clk>, <&cp_clk>,
1422 <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>, <&cp_clk>,
1423 <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
1424 #clock-cells = <1>;
1425 clock-indices = <
1426 R8A7790_CLK_GPIO5 R8A7790_CLK_GPIO4 R8A7790_CLK_GPIO3
1427 R8A7790_CLK_GPIO2 R8A7790_CLK_GPIO1 R8A7790_CLK_GPIO0
1428 R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD R8A7790_CLK_IICDVFS
1429 R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1 R8A7790_CLK_I2C0
1430 >;
1431 clock-output-names =
1432 "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0",
1433 "rcan1", "rcan0", "qspi_mod", "iic3",
1434 "i2c3", "i2c2", "i2c1", "i2c0";
1435 };
1436 mstp10_clks: mstp10_clks@e6150998 {
1437 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1438 reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
1439 clocks = <&p_clk>,
1440 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1441 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1442 <&p_clk>,
1443 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1444 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1445 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1446 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1447 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1448 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1449 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>;
1450
1451 #clock-cells = <1>;
1452 clock-indices = <
1453 R8A7790_CLK_SSI_ALL
1454 R8A7790_CLK_SSI9 R8A7790_CLK_SSI8 R8A7790_CLK_SSI7 R8A7790_CLK_SSI6 R8A7790_CLK_SSI5
1455 R8A7790_CLK_SSI4 R8A7790_CLK_SSI3 R8A7790_CLK_SSI2 R8A7790_CLK_SSI1 R8A7790_CLK_SSI0
1456 R8A7790_CLK_SCU_ALL
1457 R8A7790_CLK_SCU_DVC1 R8A7790_CLK_SCU_DVC0
1458 R8A7790_CLK_SCU_CTU1_MIX1 R8A7790_CLK_SCU_CTU0_MIX0
1459 R8A7790_CLK_SCU_SRC9 R8A7790_CLK_SCU_SRC8 R8A7790_CLK_SCU_SRC7 R8A7790_CLK_SCU_SRC6 R8A7790_CLK_SCU_SRC5
1460 R8A7790_CLK_SCU_SRC4 R8A7790_CLK_SCU_SRC3 R8A7790_CLK_SCU_SRC2 R8A7790_CLK_SCU_SRC1 R8A7790_CLK_SCU_SRC0
1461 >;
1462 clock-output-names =
1463 "ssi-all",
1464 "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
1465 "ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
1466 "scu-all",
1467 "scu-dvc1", "scu-dvc0",
1468 "scu-ctu1-mix1", "scu-ctu0-mix0",
1469 "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
1470 "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
1471 };
1472 };
1473
1474 prr: chipid@ff000044 {
1475 compatible = "renesas,prr";
1476 reg = <0 0xff000044 0 4>;
1477 };
1478
1479 rst: reset-controller@e6160000 {
1480 compatible = "renesas,r8a7790-rst";
1481 reg = <0 0xe6160000 0 0x0100>;
1482 };
1483
1484 sysc: system-controller@e6180000 {
1485 compatible = "renesas,r8a7790-sysc";
1486 reg = <0 0xe6180000 0 0x0200>;
1487 #power-domain-cells = <1>;
1488 };
1489
1490 qspi: spi@e6b10000 {
1491 compatible = "renesas,qspi-r8a7790", "renesas,qspi";
1492 reg = <0 0xe6b10000 0 0x2c>;
1493 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
1494 clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>;
1495 dmas = <&dmac0 0x17>, <&dmac0 0x18>,
1496 <&dmac1 0x17>, <&dmac1 0x18>;
1497 dma-names = "tx", "rx", "tx", "rx";
1498 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1499 num-cs = <1>;
1500 #address-cells = <1>;
1501 #size-cells = <0>;
1502 status = "disabled";
1503 };
1504
1505 msiof0: spi@e6e20000 {
1506 compatible = "renesas,msiof-r8a7790";
1507 reg = <0 0xe6e20000 0 0x0064>;
1508 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1509 clocks = <&mstp0_clks R8A7790_CLK_MSIOF0>;
1510 dmas = <&dmac0 0x51>, <&dmac0 0x52>,
1511 <&dmac1 0x51>, <&dmac1 0x52>;
1512 dma-names = "tx", "rx", "tx", "rx";
1513 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1514 #address-cells = <1>;
1515 #size-cells = <0>;
1516 status = "disabled";
1517 };
1518
1519 msiof1: spi@e6e10000 {
1520 compatible = "renesas,msiof-r8a7790";
1521 reg = <0 0xe6e10000 0 0x0064>;
1522 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1523 clocks = <&mstp2_clks R8A7790_CLK_MSIOF1>;
1524 dmas = <&dmac0 0x55>, <&dmac0 0x56>,
1525 <&dmac1 0x55>, <&dmac1 0x56>;
1526 dma-names = "tx", "rx", "tx", "rx";
1527 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1528 #address-cells = <1>;
1529 #size-cells = <0>;
1530 status = "disabled";
1531 };
1532
1533 msiof2: spi@e6e00000 {
1534 compatible = "renesas,msiof-r8a7790";
1535 reg = <0 0xe6e00000 0 0x0064>;
1536 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1537 clocks = <&mstp2_clks R8A7790_CLK_MSIOF2>;
1538 dmas = <&dmac0 0x41>, <&dmac0 0x42>,
1539 <&dmac1 0x41>, <&dmac1 0x42>;
1540 dma-names = "tx", "rx", "tx", "rx";
1541 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1542 #address-cells = <1>;
1543 #size-cells = <0>;
1544 status = "disabled";
1545 };
1546
1547 msiof3: spi@e6c90000 {
1548 compatible = "renesas,msiof-r8a7790";
1549 reg = <0 0xe6c90000 0 0x0064>;
1550 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1551 clocks = <&mstp2_clks R8A7790_CLK_MSIOF3>;
1552 dmas = <&dmac0 0x45>, <&dmac0 0x46>,
1553 <&dmac1 0x45>, <&dmac1 0x46>;
1554 dma-names = "tx", "rx", "tx", "rx";
1555 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1556 #address-cells = <1>;
1557 #size-cells = <0>;
1558 status = "disabled";
1559 };
1560
1561 xhci: usb@ee000000 {
1562 compatible = "renesas,xhci-r8a7790", "renesas,rcar-gen2-xhci";
1563 reg = <0 0xee000000 0 0xc00>;
1564 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1565 clocks = <&mstp3_clks R8A7790_CLK_SSUSB>;
1566 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1567 phys = <&usb2 1>;
1568 phy-names = "usb";
1569 status = "disabled";
1570 };
1571
1572 pci0: pci@ee090000 {
1573 compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
1574 device_type = "pci";
1575 reg = <0 0xee090000 0 0xc00>,
1576 <0 0xee080000 0 0x1100>;
1577 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1578 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1579 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1580 status = "disabled";
1581
1582 bus-range = <0 0>;
1583 #address-cells = <3>;
1584 #size-cells = <2>;
1585 #interrupt-cells = <1>;
1586 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
1587 interrupt-map-mask = <0xff00 0 0 0x7>;
1588 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
1589 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
1590 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1591
1592 usb@0,1 {
1593 reg = <0x800 0 0 0 0>;
1594 device_type = "pci";
1595 phys = <&usb0 0>;
1596 phy-names = "usb";
1597 };
1598
1599 usb@0,2 {
1600 reg = <0x1000 0 0 0 0>;
1601 device_type = "pci";
1602 phys = <&usb0 0>;
1603 phy-names = "usb";
1604 };
1605 };
1606
1607 pci1: pci@ee0b0000 {
1608 compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
1609 device_type = "pci";
1610 reg = <0 0xee0b0000 0 0xc00>,
1611 <0 0xee0a0000 0 0x1100>;
1612 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1613 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1614 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1615 status = "disabled";
1616
1617 bus-range = <1 1>;
1618 #address-cells = <3>;
1619 #size-cells = <2>;
1620 #interrupt-cells = <1>;
1621 ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>;
1622 interrupt-map-mask = <0xff00 0 0 0x7>;
1623 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH
1624 0x0800 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH
1625 0x1000 0 0 2 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1626 };
1627
1628 pci2: pci@ee0d0000 {
1629 compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
1630 device_type = "pci";
1631 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1632 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1633 reg = <0 0xee0d0000 0 0xc00>,
1634 <0 0xee0c0000 0 0x1100>;
1635 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1636 status = "disabled";
1637
1638 bus-range = <2 2>;
1639 #address-cells = <3>;
1640 #size-cells = <2>;
1641 #interrupt-cells = <1>;
1642 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
1643 interrupt-map-mask = <0xff00 0 0 0x7>;
1644 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
1645 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
1646 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1647
1648 usb@0,1 {
1649 reg = <0x800 0 0 0 0>;
1650 device_type = "pci";
1651 phys = <&usb2 0>;
1652 phy-names = "usb";
1653 };
1654
1655 usb@0,2 {
1656 reg = <0x1000 0 0 0 0>;
1657 device_type = "pci";
1658 phys = <&usb2 0>;
1659 phy-names = "usb";
1660 };
1661 };
1662
1663 pciec: pcie@fe000000 {
1664 compatible = "renesas,pcie-r8a7790", "renesas,pcie-rcar-gen2";
1665 reg = <0 0xfe000000 0 0x80000>;
1666 #address-cells = <3>;
1667 #size-cells = <2>;
1668 bus-range = <0x00 0xff>;
1669 device_type = "pci";
1670 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
1671 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
1672 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
1673 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1674 /* Map all possible DDR as inbound ranges */
1675 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
1676 0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>;
1677 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1678 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1679 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1680 #interrupt-cells = <1>;
1681 interrupt-map-mask = <0 0 0 0>;
1682 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1683 clocks = <&mstp3_clks R8A7790_CLK_PCIEC>, <&pcie_bus_clk>;
1684 clock-names = "pcie", "pcie_bus";
1685 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1686 status = "disabled";
1687 };
1688
1689 rcar_sound: sound@ec500000 {
1690 /*
1691 * #sound-dai-cells is required
1692 *
1693 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1694 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1695 */
1696 compatible = "renesas,rcar_sound-r8a7790", "renesas,rcar_sound-gen2";
1697 reg = <0 0xec500000 0 0x1000>, /* SCU */
1698 <0 0xec5a0000 0 0x100>, /* ADG */
1699 <0 0xec540000 0 0x1000>, /* SSIU */
1700 <0 0xec541000 0 0x280>, /* SSI */
1701 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
1702 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1703
1704 clocks = <&mstp10_clks R8A7790_CLK_SSI_ALL>,
1705 <&mstp10_clks R8A7790_CLK_SSI9>, <&mstp10_clks R8A7790_CLK_SSI8>,
1706 <&mstp10_clks R8A7790_CLK_SSI7>, <&mstp10_clks R8A7790_CLK_SSI6>,
1707 <&mstp10_clks R8A7790_CLK_SSI5>, <&mstp10_clks R8A7790_CLK_SSI4>,
1708 <&mstp10_clks R8A7790_CLK_SSI3>, <&mstp10_clks R8A7790_CLK_SSI2>,
1709 <&mstp10_clks R8A7790_CLK_SSI1>, <&mstp10_clks R8A7790_CLK_SSI0>,
1710 <&mstp10_clks R8A7790_CLK_SCU_SRC9>, <&mstp10_clks R8A7790_CLK_SCU_SRC8>,
1711 <&mstp10_clks R8A7790_CLK_SCU_SRC7>, <&mstp10_clks R8A7790_CLK_SCU_SRC6>,
1712 <&mstp10_clks R8A7790_CLK_SCU_SRC5>, <&mstp10_clks R8A7790_CLK_SCU_SRC4>,
1713 <&mstp10_clks R8A7790_CLK_SCU_SRC3>, <&mstp10_clks R8A7790_CLK_SCU_SRC2>,
1714 <&mstp10_clks R8A7790_CLK_SCU_SRC1>, <&mstp10_clks R8A7790_CLK_SCU_SRC0>,
1715 <&mstp10_clks R8A7790_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7790_CLK_SCU_CTU1_MIX1>,
1716 <&mstp10_clks R8A7790_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7790_CLK_SCU_CTU1_MIX1>,
1717 <&mstp10_clks R8A7790_CLK_SCU_DVC0>, <&mstp10_clks R8A7790_CLK_SCU_DVC1>,
1718 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
1719 clock-names = "ssi-all",
1720 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
1721 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
1722 "src.9", "src.8", "src.7", "src.6", "src.5",
1723 "src.4", "src.3", "src.2", "src.1", "src.0",
1724 "ctu.0", "ctu.1",
1725 "mix.0", "mix.1",
1726 "dvc.0", "dvc.1",
1727 "clk_a", "clk_b", "clk_c", "clk_i";
1728 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1729
1730 status = "disabled";
1731
1732 rcar_sound,dvc {
1733 dvc0: dvc-0 {
1734 dmas = <&audma0 0xbc>;
1735 dma-names = "tx";
1736 };
1737 dvc1: dvc-1 {
1738 dmas = <&audma0 0xbe>;
1739 dma-names = "tx";
1740 };
1741 };
1742
1743 rcar_sound,mix {
1744 mix0: mix-0 { };
1745 mix1: mix-1 { };
1746 };
1747
1748 rcar_sound,ctu {
1749 ctu00: ctu-0 { };
1750 ctu01: ctu-1 { };
1751 ctu02: ctu-2 { };
1752 ctu03: ctu-3 { };
1753 ctu10: ctu-4 { };
1754 ctu11: ctu-5 { };
1755 ctu12: ctu-6 { };
1756 ctu13: ctu-7 { };
1757 };
1758
1759 rcar_sound,src {
1760 src0: src-0 {
1761 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1762 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1763 dma-names = "rx", "tx";
1764 };
1765 src1: src-1 {
1766 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1767 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1768 dma-names = "rx", "tx";
1769 };
1770 src2: src-2 {
1771 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1772 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1773 dma-names = "rx", "tx";
1774 };
1775 src3: src-3 {
1776 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1777 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1778 dma-names = "rx", "tx";
1779 };
1780 src4: src-4 {
1781 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1782 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1783 dma-names = "rx", "tx";
1784 };
1785 src5: src-5 {
1786 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1787 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1788 dma-names = "rx", "tx";
1789 };
1790 src6: src-6 {
1791 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1792 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1793 dma-names = "rx", "tx";
1794 };
1795 src7: src-7 {
1796 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1797 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1798 dma-names = "rx", "tx";
1799 };
1800 src8: src-8 {
1801 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1802 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1803 dma-names = "rx", "tx";
1804 };
1805 src9: src-9 {
1806 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
1807 dmas = <&audma0 0x97>, <&audma1 0xba>;
1808 dma-names = "rx", "tx";
1809 };
1810 };
1811
1812 rcar_sound,ssi {
1813 ssi0: ssi-0 {
1814 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
1815 dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
1816 dma-names = "rx", "tx", "rxu", "txu";
1817 };
1818 ssi1: ssi-1 {
1819 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1820 dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
1821 dma-names = "rx", "tx", "rxu", "txu";
1822 };
1823 ssi2: ssi-2 {
1824 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
1825 dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
1826 dma-names = "rx", "tx", "rxu", "txu";
1827 };
1828 ssi3: ssi-3 {
1829 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1830 dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
1831 dma-names = "rx", "tx", "rxu", "txu";
1832 };
1833 ssi4: ssi-4 {
1834 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1835 dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
1836 dma-names = "rx", "tx", "rxu", "txu";
1837 };
1838 ssi5: ssi-5 {
1839 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1840 dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
1841 dma-names = "rx", "tx", "rxu", "txu";
1842 };
1843 ssi6: ssi-6 {
1844 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
1845 dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
1846 dma-names = "rx", "tx", "rxu", "txu";
1847 };
1848 ssi7: ssi-7 {
1849 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
1850 dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
1851 dma-names = "rx", "tx", "rxu", "txu";
1852 };
1853 ssi8: ssi-8 {
1854 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
1855 dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
1856 dma-names = "rx", "tx", "rxu", "txu";
1857 };
1858 ssi9: ssi-9 {
1859 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
1860 dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
1861 dma-names = "rx", "tx", "rxu", "txu";
1862 };
1863 };
1864 };
1865
1866 ipmmu_sy0: mmu@e6280000 {
1867 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
1868 reg = <0 0xe6280000 0 0x1000>;
1869 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
1870 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
1871 #iommu-cells = <1>;
1872 status = "disabled";
1873 };
1874
1875 ipmmu_sy1: mmu@e6290000 {
1876 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
1877 reg = <0 0xe6290000 0 0x1000>;
1878 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1879 #iommu-cells = <1>;
1880 status = "disabled";
1881 };
1882
1883 ipmmu_ds: mmu@e6740000 {
1884 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
1885 reg = <0 0xe6740000 0 0x1000>;
1886 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
1887 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
1888 #iommu-cells = <1>;
1889 status = "disabled";
1890 };
1891
1892 ipmmu_mp: mmu@ec680000 {
1893 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
1894 reg = <0 0xec680000 0 0x1000>;
1895 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1896 #iommu-cells = <1>;
1897 status = "disabled";
1898 };
1899
1900 ipmmu_mx: mmu@fe951000 {
1901 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
1902 reg = <0 0xfe951000 0 0x1000>;
1903 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
1904 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1905 #iommu-cells = <1>;
1906 status = "disabled";
1907 };
1908
1909 ipmmu_rt: mmu@ffc80000 {
1910 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
1911 reg = <0 0xffc80000 0 0x1000>;
1912 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
1913 #iommu-cells = <1>;
1914 status = "disabled";
1915 };
1916 };
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