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Merge tag 'nfs-for-4.11-1' of git://git.linux-nfs.org/projects/anna/linux-nfs
[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / r8a7790.dtsi
1 /*
2 * Device Tree Source for the r8a7790 SoC
3 *
4 * Copyright (C) 2015 Renesas Electronics Corporation
5 * Copyright (C) 2013-2014 Renesas Solutions Corp.
6 * Copyright (C) 2014 Cogent Embedded Inc.
7 *
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
11 */
12
13 #include <dt-bindings/clock/r8a7790-clock.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/interrupt-controller/irq.h>
16 #include <dt-bindings/power/r8a7790-sysc.h>
17
18 / {
19 compatible = "renesas,r8a7790";
20 interrupt-parent = <&gic>;
21 #address-cells = <2>;
22 #size-cells = <2>;
23
24 aliases {
25 i2c0 = &i2c0;
26 i2c1 = &i2c1;
27 i2c2 = &i2c2;
28 i2c3 = &i2c3;
29 i2c4 = &iic0;
30 i2c5 = &iic1;
31 i2c6 = &iic2;
32 i2c7 = &iic3;
33 spi0 = &qspi;
34 spi1 = &msiof0;
35 spi2 = &msiof1;
36 spi3 = &msiof2;
37 spi4 = &msiof3;
38 vin0 = &vin0;
39 vin1 = &vin1;
40 vin2 = &vin2;
41 vin3 = &vin3;
42 };
43
44 cpus {
45 #address-cells = <1>;
46 #size-cells = <0>;
47 enable-method = "renesas,apmu";
48
49 cpu0: cpu@0 {
50 device_type = "cpu";
51 compatible = "arm,cortex-a15";
52 reg = <0>;
53 clock-frequency = <1300000000>;
54 voltage-tolerance = <1>; /* 1% */
55 clocks = <&cpg_clocks R8A7790_CLK_Z>;
56 clock-latency = <300000>; /* 300 us */
57 power-domains = <&sysc R8A7790_PD_CA15_CPU0>;
58 next-level-cache = <&L2_CA15>;
59
60 /* kHz - uV - OPPs unknown yet */
61 operating-points = <1400000 1000000>,
62 <1225000 1000000>,
63 <1050000 1000000>,
64 < 875000 1000000>,
65 < 700000 1000000>,
66 < 350000 1000000>;
67 };
68
69 cpu1: cpu@1 {
70 device_type = "cpu";
71 compatible = "arm,cortex-a15";
72 reg = <1>;
73 clock-frequency = <1300000000>;
74 power-domains = <&sysc R8A7790_PD_CA15_CPU1>;
75 next-level-cache = <&L2_CA15>;
76 };
77
78 cpu2: cpu@2 {
79 device_type = "cpu";
80 compatible = "arm,cortex-a15";
81 reg = <2>;
82 clock-frequency = <1300000000>;
83 power-domains = <&sysc R8A7790_PD_CA15_CPU2>;
84 next-level-cache = <&L2_CA15>;
85 };
86
87 cpu3: cpu@3 {
88 device_type = "cpu";
89 compatible = "arm,cortex-a15";
90 reg = <3>;
91 clock-frequency = <1300000000>;
92 power-domains = <&sysc R8A7790_PD_CA15_CPU3>;
93 next-level-cache = <&L2_CA15>;
94 };
95
96 cpu4: cpu@100 {
97 device_type = "cpu";
98 compatible = "arm,cortex-a7";
99 reg = <0x100>;
100 clock-frequency = <780000000>;
101 power-domains = <&sysc R8A7790_PD_CA7_CPU0>;
102 next-level-cache = <&L2_CA7>;
103 };
104
105 cpu5: cpu@101 {
106 device_type = "cpu";
107 compatible = "arm,cortex-a7";
108 reg = <0x101>;
109 clock-frequency = <780000000>;
110 power-domains = <&sysc R8A7790_PD_CA7_CPU1>;
111 next-level-cache = <&L2_CA7>;
112 };
113
114 cpu6: cpu@102 {
115 device_type = "cpu";
116 compatible = "arm,cortex-a7";
117 reg = <0x102>;
118 clock-frequency = <780000000>;
119 power-domains = <&sysc R8A7790_PD_CA7_CPU2>;
120 next-level-cache = <&L2_CA7>;
121 };
122
123 cpu7: cpu@103 {
124 device_type = "cpu";
125 compatible = "arm,cortex-a7";
126 reg = <0x103>;
127 clock-frequency = <780000000>;
128 power-domains = <&sysc R8A7790_PD_CA7_CPU3>;
129 next-level-cache = <&L2_CA7>;
130 };
131
132 L2_CA15: cache-controller@0 {
133 compatible = "cache";
134 reg = <0>;
135 power-domains = <&sysc R8A7790_PD_CA15_SCU>;
136 cache-unified;
137 cache-level = <2>;
138 };
139
140 L2_CA7: cache-controller@100 {
141 compatible = "cache";
142 reg = <0x100>;
143 power-domains = <&sysc R8A7790_PD_CA7_SCU>;
144 cache-unified;
145 cache-level = <2>;
146 };
147 };
148
149 thermal-zones {
150 cpu_thermal: cpu-thermal {
151 polling-delay-passive = <0>;
152 polling-delay = <0>;
153
154 thermal-sensors = <&thermal>;
155
156 trips {
157 cpu-crit {
158 temperature = <115000>;
159 hysteresis = <0>;
160 type = "critical";
161 };
162 };
163 cooling-maps {
164 };
165 };
166 };
167
168 apmu@e6151000 {
169 compatible = "renesas,r8a7790-apmu", "renesas,apmu";
170 reg = <0 0xe6151000 0 0x188>;
171 cpus = <&cpu4 &cpu5 &cpu6 &cpu7>;
172 };
173
174 apmu@e6152000 {
175 compatible = "renesas,r8a7790-apmu", "renesas,apmu";
176 reg = <0 0xe6152000 0 0x188>;
177 cpus = <&cpu0 &cpu1 &cpu2 &cpu3>;
178 };
179
180 gic: interrupt-controller@f1001000 {
181 compatible = "arm,gic-400";
182 #interrupt-cells = <3>;
183 #address-cells = <0>;
184 interrupt-controller;
185 reg = <0 0xf1001000 0 0x1000>,
186 <0 0xf1002000 0 0x2000>,
187 <0 0xf1004000 0 0x2000>,
188 <0 0xf1006000 0 0x2000>;
189 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
190 };
191
192 gpio0: gpio@e6050000 {
193 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
194 reg = <0 0xe6050000 0 0x50>;
195 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
196 #gpio-cells = <2>;
197 gpio-controller;
198 gpio-ranges = <&pfc 0 0 32>;
199 #interrupt-cells = <2>;
200 interrupt-controller;
201 clocks = <&mstp9_clks R8A7790_CLK_GPIO0>;
202 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
203 };
204
205 gpio1: gpio@e6051000 {
206 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
207 reg = <0 0xe6051000 0 0x50>;
208 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
209 #gpio-cells = <2>;
210 gpio-controller;
211 gpio-ranges = <&pfc 0 32 30>;
212 #interrupt-cells = <2>;
213 interrupt-controller;
214 clocks = <&mstp9_clks R8A7790_CLK_GPIO1>;
215 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
216 };
217
218 gpio2: gpio@e6052000 {
219 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
220 reg = <0 0xe6052000 0 0x50>;
221 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
222 #gpio-cells = <2>;
223 gpio-controller;
224 gpio-ranges = <&pfc 0 64 30>;
225 #interrupt-cells = <2>;
226 interrupt-controller;
227 clocks = <&mstp9_clks R8A7790_CLK_GPIO2>;
228 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
229 };
230
231 gpio3: gpio@e6053000 {
232 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
233 reg = <0 0xe6053000 0 0x50>;
234 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
235 #gpio-cells = <2>;
236 gpio-controller;
237 gpio-ranges = <&pfc 0 96 32>;
238 #interrupt-cells = <2>;
239 interrupt-controller;
240 clocks = <&mstp9_clks R8A7790_CLK_GPIO3>;
241 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
242 };
243
244 gpio4: gpio@e6054000 {
245 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
246 reg = <0 0xe6054000 0 0x50>;
247 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
248 #gpio-cells = <2>;
249 gpio-controller;
250 gpio-ranges = <&pfc 0 128 32>;
251 #interrupt-cells = <2>;
252 interrupt-controller;
253 clocks = <&mstp9_clks R8A7790_CLK_GPIO4>;
254 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
255 };
256
257 gpio5: gpio@e6055000 {
258 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
259 reg = <0 0xe6055000 0 0x50>;
260 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
261 #gpio-cells = <2>;
262 gpio-controller;
263 gpio-ranges = <&pfc 0 160 32>;
264 #interrupt-cells = <2>;
265 interrupt-controller;
266 clocks = <&mstp9_clks R8A7790_CLK_GPIO5>;
267 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
268 };
269
270 thermal: thermal@e61f0000 {
271 compatible = "renesas,thermal-r8a7790",
272 "renesas,rcar-gen2-thermal",
273 "renesas,rcar-thermal";
274 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
275 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
276 clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
277 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
278 #thermal-sensor-cells = <0>;
279 };
280
281 timer {
282 compatible = "arm,armv7-timer";
283 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
284 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
285 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
286 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
287 };
288
289 cmt0: timer@ffca0000 {
290 compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
291 reg = <0 0xffca0000 0 0x1004>;
292 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
293 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
294 clocks = <&mstp1_clks R8A7790_CLK_CMT0>;
295 clock-names = "fck";
296 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
297
298 renesas,channels-mask = <0x60>;
299
300 status = "disabled";
301 };
302
303 cmt1: timer@e6130000 {
304 compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
305 reg = <0 0xe6130000 0 0x1004>;
306 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
307 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
308 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
309 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
310 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
311 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
312 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
313 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
314 clocks = <&mstp3_clks R8A7790_CLK_CMT1>;
315 clock-names = "fck";
316 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
317
318 renesas,channels-mask = <0xff>;
319
320 status = "disabled";
321 };
322
323 irqc0: interrupt-controller@e61c0000 {
324 compatible = "renesas,irqc-r8a7790", "renesas,irqc";
325 #interrupt-cells = <2>;
326 interrupt-controller;
327 reg = <0 0xe61c0000 0 0x200>;
328 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
329 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
330 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
331 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
332 clocks = <&mstp4_clks R8A7790_CLK_IRQC>;
333 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
334 };
335
336 dmac0: dma-controller@e6700000 {
337 compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
338 reg = <0 0xe6700000 0 0x20000>;
339 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
340 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
341 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
342 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
343 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
344 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
345 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
346 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
347 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
348 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
349 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
350 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
351 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
352 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
353 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
354 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
355 interrupt-names = "error",
356 "ch0", "ch1", "ch2", "ch3",
357 "ch4", "ch5", "ch6", "ch7",
358 "ch8", "ch9", "ch10", "ch11",
359 "ch12", "ch13", "ch14";
360 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>;
361 clock-names = "fck";
362 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
363 #dma-cells = <1>;
364 dma-channels = <15>;
365 };
366
367 dmac1: dma-controller@e6720000 {
368 compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
369 reg = <0 0xe6720000 0 0x20000>;
370 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
371 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
372 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
373 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
374 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
375 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
376 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
377 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
378 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
379 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
380 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
381 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
382 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
383 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
384 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
385 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
386 interrupt-names = "error",
387 "ch0", "ch1", "ch2", "ch3",
388 "ch4", "ch5", "ch6", "ch7",
389 "ch8", "ch9", "ch10", "ch11",
390 "ch12", "ch13", "ch14";
391 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>;
392 clock-names = "fck";
393 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
394 #dma-cells = <1>;
395 dma-channels = <15>;
396 };
397
398 audma0: dma-controller@ec700000 {
399 compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
400 reg = <0 0xec700000 0 0x10000>;
401 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
402 GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
403 GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
404 GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
405 GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
406 GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
407 GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
408 GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
409 GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
410 GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
411 GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
412 GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
413 GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
414 GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
415 interrupt-names = "error",
416 "ch0", "ch1", "ch2", "ch3",
417 "ch4", "ch5", "ch6", "ch7",
418 "ch8", "ch9", "ch10", "ch11",
419 "ch12";
420 clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC0>;
421 clock-names = "fck";
422 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
423 #dma-cells = <1>;
424 dma-channels = <13>;
425 };
426
427 audma1: dma-controller@ec720000 {
428 compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
429 reg = <0 0xec720000 0 0x10000>;
430 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
431 GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
432 GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
433 GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
434 GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
435 GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
436 GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
437 GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
438 GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
439 GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
440 GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
441 GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
442 GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
443 GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
444 interrupt-names = "error",
445 "ch0", "ch1", "ch2", "ch3",
446 "ch4", "ch5", "ch6", "ch7",
447 "ch8", "ch9", "ch10", "ch11",
448 "ch12";
449 clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC1>;
450 clock-names = "fck";
451 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
452 #dma-cells = <1>;
453 dma-channels = <13>;
454 };
455
456 usb_dmac0: dma-controller@e65a0000 {
457 compatible = "renesas,r8a7790-usb-dmac", "renesas,usb-dmac";
458 reg = <0 0xe65a0000 0 0x100>;
459 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
460 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
461 interrupt-names = "ch0", "ch1";
462 clocks = <&mstp3_clks R8A7790_CLK_USBDMAC0>;
463 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
464 #dma-cells = <1>;
465 dma-channels = <2>;
466 };
467
468 usb_dmac1: dma-controller@e65b0000 {
469 compatible = "renesas,r8a7790-usb-dmac", "renesas,usb-dmac";
470 reg = <0 0xe65b0000 0 0x100>;
471 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
472 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
473 interrupt-names = "ch0", "ch1";
474 clocks = <&mstp3_clks R8A7790_CLK_USBDMAC1>;
475 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
476 #dma-cells = <1>;
477 dma-channels = <2>;
478 };
479
480 i2c0: i2c@e6508000 {
481 #address-cells = <1>;
482 #size-cells = <0>;
483 compatible = "renesas,i2c-r8a7790", "renesas,rcar-gen2-i2c";
484 reg = <0 0xe6508000 0 0x40>;
485 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
486 clocks = <&mstp9_clks R8A7790_CLK_I2C0>;
487 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
488 i2c-scl-internal-delay-ns = <110>;
489 status = "disabled";
490 };
491
492 i2c1: i2c@e6518000 {
493 #address-cells = <1>;
494 #size-cells = <0>;
495 compatible = "renesas,i2c-r8a7790", "renesas,rcar-gen2-i2c";
496 reg = <0 0xe6518000 0 0x40>;
497 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
498 clocks = <&mstp9_clks R8A7790_CLK_I2C1>;
499 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
500 i2c-scl-internal-delay-ns = <6>;
501 status = "disabled";
502 };
503
504 i2c2: i2c@e6530000 {
505 #address-cells = <1>;
506 #size-cells = <0>;
507 compatible = "renesas,i2c-r8a7790", "renesas,rcar-gen2-i2c";
508 reg = <0 0xe6530000 0 0x40>;
509 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
510 clocks = <&mstp9_clks R8A7790_CLK_I2C2>;
511 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
512 i2c-scl-internal-delay-ns = <6>;
513 status = "disabled";
514 };
515
516 i2c3: i2c@e6540000 {
517 #address-cells = <1>;
518 #size-cells = <0>;
519 compatible = "renesas,i2c-r8a7790", "renesas,rcar-gen2-i2c";
520 reg = <0 0xe6540000 0 0x40>;
521 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
522 clocks = <&mstp9_clks R8A7790_CLK_I2C3>;
523 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
524 i2c-scl-internal-delay-ns = <110>;
525 status = "disabled";
526 };
527
528 iic0: i2c@e6500000 {
529 #address-cells = <1>;
530 #size-cells = <0>;
531 compatible = "renesas,iic-r8a7790", "renesas,rcar-gen2-iic",
532 "renesas,rmobile-iic";
533 reg = <0 0xe6500000 0 0x425>;
534 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
535 clocks = <&mstp3_clks R8A7790_CLK_IIC0>;
536 dmas = <&dmac0 0x61>, <&dmac0 0x62>,
537 <&dmac1 0x61>, <&dmac1 0x62>;
538 dma-names = "tx", "rx", "tx", "rx";
539 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
540 status = "disabled";
541 };
542
543 iic1: i2c@e6510000 {
544 #address-cells = <1>;
545 #size-cells = <0>;
546 compatible = "renesas,iic-r8a7790", "renesas,rcar-gen2-iic",
547 "renesas,rmobile-iic";
548 reg = <0 0xe6510000 0 0x425>;
549 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
550 clocks = <&mstp3_clks R8A7790_CLK_IIC1>;
551 dmas = <&dmac0 0x65>, <&dmac0 0x66>,
552 <&dmac1 0x65>, <&dmac1 0x66>;
553 dma-names = "tx", "rx", "tx", "rx";
554 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
555 status = "disabled";
556 };
557
558 iic2: i2c@e6520000 {
559 #address-cells = <1>;
560 #size-cells = <0>;
561 compatible = "renesas,iic-r8a7790", "renesas,rcar-gen2-iic",
562 "renesas,rmobile-iic";
563 reg = <0 0xe6520000 0 0x425>;
564 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
565 clocks = <&mstp3_clks R8A7790_CLK_IIC2>;
566 dmas = <&dmac0 0x69>, <&dmac0 0x6a>,
567 <&dmac1 0x69>, <&dmac1 0x6a>;
568 dma-names = "tx", "rx", "tx", "rx";
569 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
570 status = "disabled";
571 };
572
573 iic3: i2c@e60b0000 {
574 #address-cells = <1>;
575 #size-cells = <0>;
576 compatible = "renesas,iic-r8a7790", "renesas,rcar-gen2-iic",
577 "renesas,rmobile-iic";
578 reg = <0 0xe60b0000 0 0x425>;
579 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
580 clocks = <&mstp9_clks R8A7790_CLK_IICDVFS>;
581 dmas = <&dmac0 0x77>, <&dmac0 0x78>,
582 <&dmac1 0x77>, <&dmac1 0x78>;
583 dma-names = "tx", "rx", "tx", "rx";
584 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
585 status = "disabled";
586 };
587
588 mmcif0: mmc@ee200000 {
589 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
590 reg = <0 0xee200000 0 0x80>;
591 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
592 clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>;
593 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
594 <&dmac1 0xd1>, <&dmac1 0xd2>;
595 dma-names = "tx", "rx", "tx", "rx";
596 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
597 reg-io-width = <4>;
598 status = "disabled";
599 max-frequency = <97500000>;
600 };
601
602 mmcif1: mmc@ee220000 {
603 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
604 reg = <0 0xee220000 0 0x80>;
605 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
606 clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>;
607 dmas = <&dmac0 0xe1>, <&dmac0 0xe2>,
608 <&dmac1 0xe1>, <&dmac1 0xe2>;
609 dma-names = "tx", "rx", "tx", "rx";
610 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
611 reg-io-width = <4>;
612 status = "disabled";
613 max-frequency = <97500000>;
614 };
615
616 pfc: pfc@e6060000 {
617 compatible = "renesas,pfc-r8a7790";
618 reg = <0 0xe6060000 0 0x250>;
619 };
620
621 sdhi0: sd@ee100000 {
622 compatible = "renesas,sdhi-r8a7790";
623 reg = <0 0xee100000 0 0x328>;
624 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
625 clocks = <&mstp3_clks R8A7790_CLK_SDHI0>;
626 dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
627 <&dmac1 0xcd>, <&dmac1 0xce>;
628 dma-names = "tx", "rx", "tx", "rx";
629 max-frequency = <195000000>;
630 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
631 status = "disabled";
632 };
633
634 sdhi1: sd@ee120000 {
635 compatible = "renesas,sdhi-r8a7790";
636 reg = <0 0xee120000 0 0x328>;
637 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
638 clocks = <&mstp3_clks R8A7790_CLK_SDHI1>;
639 dmas = <&dmac0 0xc9>, <&dmac0 0xca>,
640 <&dmac1 0xc9>, <&dmac1 0xca>;
641 dma-names = "tx", "rx", "tx", "rx";
642 max-frequency = <195000000>;
643 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
644 status = "disabled";
645 };
646
647 sdhi2: sd@ee140000 {
648 compatible = "renesas,sdhi-r8a7790";
649 reg = <0 0xee140000 0 0x100>;
650 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
651 clocks = <&mstp3_clks R8A7790_CLK_SDHI2>;
652 dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
653 <&dmac1 0xc1>, <&dmac1 0xc2>;
654 dma-names = "tx", "rx", "tx", "rx";
655 max-frequency = <97500000>;
656 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
657 status = "disabled";
658 };
659
660 sdhi3: sd@ee160000 {
661 compatible = "renesas,sdhi-r8a7790";
662 reg = <0 0xee160000 0 0x100>;
663 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
664 clocks = <&mstp3_clks R8A7790_CLK_SDHI3>;
665 dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
666 <&dmac1 0xd3>, <&dmac1 0xd4>;
667 dma-names = "tx", "rx", "tx", "rx";
668 max-frequency = <97500000>;
669 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
670 status = "disabled";
671 };
672
673 scifa0: serial@e6c40000 {
674 compatible = "renesas,scifa-r8a7790",
675 "renesas,rcar-gen2-scifa", "renesas,scifa";
676 reg = <0 0xe6c40000 0 64>;
677 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
678 clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>;
679 clock-names = "fck";
680 dmas = <&dmac0 0x21>, <&dmac0 0x22>,
681 <&dmac1 0x21>, <&dmac1 0x22>;
682 dma-names = "tx", "rx", "tx", "rx";
683 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
684 status = "disabled";
685 };
686
687 scifa1: serial@e6c50000 {
688 compatible = "renesas,scifa-r8a7790",
689 "renesas,rcar-gen2-scifa", "renesas,scifa";
690 reg = <0 0xe6c50000 0 64>;
691 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
692 clocks = <&mstp2_clks R8A7790_CLK_SCIFA1>;
693 clock-names = "fck";
694 dmas = <&dmac0 0x25>, <&dmac0 0x26>,
695 <&dmac1 0x25>, <&dmac1 0x26>;
696 dma-names = "tx", "rx", "tx", "rx";
697 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
698 status = "disabled";
699 };
700
701 scifa2: serial@e6c60000 {
702 compatible = "renesas,scifa-r8a7790",
703 "renesas,rcar-gen2-scifa", "renesas,scifa";
704 reg = <0 0xe6c60000 0 64>;
705 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
706 clocks = <&mstp2_clks R8A7790_CLK_SCIFA2>;
707 clock-names = "fck";
708 dmas = <&dmac0 0x27>, <&dmac0 0x28>,
709 <&dmac1 0x27>, <&dmac1 0x28>;
710 dma-names = "tx", "rx", "tx", "rx";
711 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
712 status = "disabled";
713 };
714
715 scifb0: serial@e6c20000 {
716 compatible = "renesas,scifb-r8a7790",
717 "renesas,rcar-gen2-scifb", "renesas,scifb";
718 reg = <0 0xe6c20000 0 0x100>;
719 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
720 clocks = <&mstp2_clks R8A7790_CLK_SCIFB0>;
721 clock-names = "fck";
722 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
723 <&dmac1 0x3d>, <&dmac1 0x3e>;
724 dma-names = "tx", "rx", "tx", "rx";
725 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
726 status = "disabled";
727 };
728
729 scifb1: serial@e6c30000 {
730 compatible = "renesas,scifb-r8a7790",
731 "renesas,rcar-gen2-scifb", "renesas,scifb";
732 reg = <0 0xe6c30000 0 0x100>;
733 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
734 clocks = <&mstp2_clks R8A7790_CLK_SCIFB1>;
735 clock-names = "fck";
736 dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
737 <&dmac1 0x19>, <&dmac1 0x1a>;
738 dma-names = "tx", "rx", "tx", "rx";
739 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
740 status = "disabled";
741 };
742
743 scifb2: serial@e6ce0000 {
744 compatible = "renesas,scifb-r8a7790",
745 "renesas,rcar-gen2-scifb", "renesas,scifb";
746 reg = <0 0xe6ce0000 0 0x100>;
747 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
748 clocks = <&mstp2_clks R8A7790_CLK_SCIFB2>;
749 clock-names = "fck";
750 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
751 <&dmac1 0x1d>, <&dmac1 0x1e>;
752 dma-names = "tx", "rx", "tx", "rx";
753 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
754 status = "disabled";
755 };
756
757 scif0: serial@e6e60000 {
758 compatible = "renesas,scif-r8a7790", "renesas,rcar-gen2-scif",
759 "renesas,scif";
760 reg = <0 0xe6e60000 0 64>;
761 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
762 clocks = <&mstp7_clks R8A7790_CLK_SCIF0>, <&zs_clk>,
763 <&scif_clk>;
764 clock-names = "fck", "brg_int", "scif_clk";
765 dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
766 <&dmac1 0x29>, <&dmac1 0x2a>;
767 dma-names = "tx", "rx", "tx", "rx";
768 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
769 status = "disabled";
770 };
771
772 scif1: serial@e6e68000 {
773 compatible = "renesas,scif-r8a7790", "renesas,rcar-gen2-scif",
774 "renesas,scif";
775 reg = <0 0xe6e68000 0 64>;
776 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
777 clocks = <&mstp7_clks R8A7790_CLK_SCIF1>, <&zs_clk>,
778 <&scif_clk>;
779 clock-names = "fck", "brg_int", "scif_clk";
780 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
781 <&dmac1 0x2d>, <&dmac1 0x2e>;
782 dma-names = "tx", "rx", "tx", "rx";
783 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
784 status = "disabled";
785 };
786
787 scif2: serial@e6e56000 {
788 compatible = "renesas,scif-r8a7790", "renesas,rcar-gen2-scif",
789 "renesas,scif";
790 reg = <0 0xe6e56000 0 64>;
791 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
792 clocks = <&mstp3_clks R8A7790_CLK_SCIF2>, <&zs_clk>,
793 <&scif_clk>;
794 clock-names = "fck", "brg_int", "scif_clk";
795 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
796 <&dmac1 0x2b>, <&dmac1 0x2c>;
797 dma-names = "tx", "rx", "tx", "rx";
798 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
799 status = "disabled";
800 };
801
802 hscif0: serial@e62c0000 {
803 compatible = "renesas,hscif-r8a7790",
804 "renesas,rcar-gen2-hscif", "renesas,hscif";
805 reg = <0 0xe62c0000 0 96>;
806 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
807 clocks = <&mstp7_clks R8A7790_CLK_HSCIF0>, <&zs_clk>,
808 <&scif_clk>;
809 clock-names = "fck", "brg_int", "scif_clk";
810 dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
811 <&dmac1 0x39>, <&dmac1 0x3a>;
812 dma-names = "tx", "rx", "tx", "rx";
813 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
814 status = "disabled";
815 };
816
817 hscif1: serial@e62c8000 {
818 compatible = "renesas,hscif-r8a7790",
819 "renesas,rcar-gen2-hscif", "renesas,hscif";
820 reg = <0 0xe62c8000 0 96>;
821 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
822 clocks = <&mstp7_clks R8A7790_CLK_HSCIF1>, <&zs_clk>,
823 <&scif_clk>;
824 clock-names = "fck", "brg_int", "scif_clk";
825 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
826 <&dmac1 0x4d>, <&dmac1 0x4e>;
827 dma-names = "tx", "rx", "tx", "rx";
828 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
829 status = "disabled";
830 };
831
832 ether: ethernet@ee700000 {
833 compatible = "renesas,ether-r8a7790";
834 reg = <0 0xee700000 0 0x400>;
835 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
836 clocks = <&mstp8_clks R8A7790_CLK_ETHER>;
837 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
838 phy-mode = "rmii";
839 #address-cells = <1>;
840 #size-cells = <0>;
841 status = "disabled";
842 };
843
844 avb: ethernet@e6800000 {
845 compatible = "renesas,etheravb-r8a7790",
846 "renesas,etheravb-rcar-gen2";
847 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
848 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
849 clocks = <&mstp8_clks R8A7790_CLK_ETHERAVB>;
850 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
851 #address-cells = <1>;
852 #size-cells = <0>;
853 status = "disabled";
854 };
855
856 sata0: sata@ee300000 {
857 compatible = "renesas,sata-r8a7790";
858 reg = <0 0xee300000 0 0x2000>;
859 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
860 clocks = <&mstp8_clks R8A7790_CLK_SATA0>;
861 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
862 status = "disabled";
863 };
864
865 sata1: sata@ee500000 {
866 compatible = "renesas,sata-r8a7790";
867 reg = <0 0xee500000 0 0x2000>;
868 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
869 clocks = <&mstp8_clks R8A7790_CLK_SATA1>;
870 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
871 status = "disabled";
872 };
873
874 hsusb: usb@e6590000 {
875 compatible = "renesas,usbhs-r8a7790", "renesas,rcar-gen2-usbhs";
876 reg = <0 0xe6590000 0 0x100>;
877 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
878 clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
879 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
880 <&usb_dmac1 0>, <&usb_dmac1 1>;
881 dma-names = "ch0", "ch1", "ch2", "ch3";
882 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
883 renesas,buswait = <4>;
884 phys = <&usb0 1>;
885 phy-names = "usb";
886 status = "disabled";
887 };
888
889 usbphy: usb-phy@e6590100 {
890 compatible = "renesas,usb-phy-r8a7790",
891 "renesas,rcar-gen2-usb-phy";
892 reg = <0 0xe6590100 0 0x100>;
893 #address-cells = <1>;
894 #size-cells = <0>;
895 clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
896 clock-names = "usbhs";
897 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
898 status = "disabled";
899
900 usb0: usb-channel@0 {
901 reg = <0>;
902 #phy-cells = <1>;
903 };
904 usb2: usb-channel@2 {
905 reg = <2>;
906 #phy-cells = <1>;
907 };
908 };
909
910 vin0: video@e6ef0000 {
911 compatible = "renesas,vin-r8a7790";
912 reg = <0 0xe6ef0000 0 0x1000>;
913 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
914 clocks = <&mstp8_clks R8A7790_CLK_VIN0>;
915 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
916 status = "disabled";
917 };
918
919 vin1: video@e6ef1000 {
920 compatible = "renesas,vin-r8a7790";
921 reg = <0 0xe6ef1000 0 0x1000>;
922 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
923 clocks = <&mstp8_clks R8A7790_CLK_VIN1>;
924 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
925 status = "disabled";
926 };
927
928 vin2: video@e6ef2000 {
929 compatible = "renesas,vin-r8a7790";
930 reg = <0 0xe6ef2000 0 0x1000>;
931 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
932 clocks = <&mstp8_clks R8A7790_CLK_VIN2>;
933 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
934 status = "disabled";
935 };
936
937 vin3: video@e6ef3000 {
938 compatible = "renesas,vin-r8a7790";
939 reg = <0 0xe6ef3000 0 0x1000>;
940 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
941 clocks = <&mstp8_clks R8A7790_CLK_VIN3>;
942 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
943 status = "disabled";
944 };
945
946 vsp1@fe920000 {
947 compatible = "renesas,vsp1";
948 reg = <0 0xfe920000 0 0x8000>;
949 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
950 clocks = <&mstp1_clks R8A7790_CLK_VSP1_R>;
951 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
952 };
953
954 vsp1@fe928000 {
955 compatible = "renesas,vsp1";
956 reg = <0 0xfe928000 0 0x8000>;
957 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
958 clocks = <&mstp1_clks R8A7790_CLK_VSP1_S>;
959 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
960 };
961
962 vsp1@fe930000 {
963 compatible = "renesas,vsp1";
964 reg = <0 0xfe930000 0 0x8000>;
965 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
966 clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU0>;
967 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
968 };
969
970 vsp1@fe938000 {
971 compatible = "renesas,vsp1";
972 reg = <0 0xfe938000 0 0x8000>;
973 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
974 clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU1>;
975 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
976 };
977
978 du: display@feb00000 {
979 compatible = "renesas,du-r8a7790";
980 reg = <0 0xfeb00000 0 0x70000>,
981 <0 0xfeb90000 0 0x1c>,
982 <0 0xfeb94000 0 0x1c>;
983 reg-names = "du", "lvds.0", "lvds.1";
984 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
985 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
986 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
987 clocks = <&mstp7_clks R8A7790_CLK_DU0>,
988 <&mstp7_clks R8A7790_CLK_DU1>,
989 <&mstp7_clks R8A7790_CLK_DU2>,
990 <&mstp7_clks R8A7790_CLK_LVDS0>,
991 <&mstp7_clks R8A7790_CLK_LVDS1>;
992 clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1";
993 status = "disabled";
994
995 ports {
996 #address-cells = <1>;
997 #size-cells = <0>;
998
999 port@0 {
1000 reg = <0>;
1001 du_out_rgb: endpoint {
1002 };
1003 };
1004 port@1 {
1005 reg = <1>;
1006 du_out_lvds0: endpoint {
1007 };
1008 };
1009 port@2 {
1010 reg = <2>;
1011 du_out_lvds1: endpoint {
1012 };
1013 };
1014 };
1015 };
1016
1017 can0: can@e6e80000 {
1018 compatible = "renesas,can-r8a7790", "renesas,rcar-gen2-can";
1019 reg = <0 0xe6e80000 0 0x1000>;
1020 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
1021 clocks = <&mstp9_clks R8A7790_CLK_RCAN0>,
1022 <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>;
1023 clock-names = "clkp1", "clkp2", "can_clk";
1024 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1025 status = "disabled";
1026 };
1027
1028 can1: can@e6e88000 {
1029 compatible = "renesas,can-r8a7790", "renesas,rcar-gen2-can";
1030 reg = <0 0xe6e88000 0 0x1000>;
1031 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
1032 clocks = <&mstp9_clks R8A7790_CLK_RCAN1>,
1033 <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>;
1034 clock-names = "clkp1", "clkp2", "can_clk";
1035 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1036 status = "disabled";
1037 };
1038
1039 jpu: jpeg-codec@fe980000 {
1040 compatible = "renesas,jpu-r8a7790", "renesas,rcar-gen2-jpu";
1041 reg = <0 0xfe980000 0 0x10300>;
1042 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
1043 clocks = <&mstp1_clks R8A7790_CLK_JPU>;
1044 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1045 };
1046
1047 clocks {
1048 #address-cells = <2>;
1049 #size-cells = <2>;
1050 ranges;
1051
1052 /* External root clock */
1053 extal_clk: extal {
1054 compatible = "fixed-clock";
1055 #clock-cells = <0>;
1056 /* This value must be overriden by the board. */
1057 clock-frequency = <0>;
1058 };
1059
1060 /* External PCIe clock - can be overridden by the board */
1061 pcie_bus_clk: pcie_bus {
1062 compatible = "fixed-clock";
1063 #clock-cells = <0>;
1064 clock-frequency = <0>;
1065 };
1066
1067 /*
1068 * The external audio clocks are configured as 0 Hz fixed frequency clocks by
1069 * default. Boards that provide audio clocks should override them.
1070 */
1071 audio_clk_a: audio_clk_a {
1072 compatible = "fixed-clock";
1073 #clock-cells = <0>;
1074 clock-frequency = <0>;
1075 };
1076 audio_clk_b: audio_clk_b {
1077 compatible = "fixed-clock";
1078 #clock-cells = <0>;
1079 clock-frequency = <0>;
1080 };
1081 audio_clk_c: audio_clk_c {
1082 compatible = "fixed-clock";
1083 #clock-cells = <0>;
1084 clock-frequency = <0>;
1085 };
1086
1087 /* External SCIF clock */
1088 scif_clk: scif {
1089 compatible = "fixed-clock";
1090 #clock-cells = <0>;
1091 /* This value must be overridden by the board. */
1092 clock-frequency = <0>;
1093 };
1094
1095 /* External USB clock - can be overridden by the board */
1096 usb_extal_clk: usb_extal {
1097 compatible = "fixed-clock";
1098 #clock-cells = <0>;
1099 clock-frequency = <48000000>;
1100 };
1101
1102 /* External CAN clock */
1103 can_clk: can_clk {
1104 compatible = "fixed-clock";
1105 #clock-cells = <0>;
1106 /* This value must be overridden by the board. */
1107 clock-frequency = <0>;
1108 };
1109
1110 /* Special CPG clocks */
1111 cpg_clocks: cpg_clocks@e6150000 {
1112 compatible = "renesas,r8a7790-cpg-clocks",
1113 "renesas,rcar-gen2-cpg-clocks";
1114 reg = <0 0xe6150000 0 0x1000>;
1115 clocks = <&extal_clk &usb_extal_clk>;
1116 #clock-cells = <1>;
1117 clock-output-names = "main", "pll0", "pll1", "pll3",
1118 "lb", "qspi", "sdh", "sd0", "sd1",
1119 "z", "rcan", "adsp";
1120 #power-domain-cells = <0>;
1121 };
1122
1123 /* Variable factor clocks */
1124 sd2_clk: sd2@e6150078 {
1125 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1126 reg = <0 0xe6150078 0 4>;
1127 clocks = <&pll1_div2_clk>;
1128 #clock-cells = <0>;
1129 };
1130 sd3_clk: sd3@e615026c {
1131 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1132 reg = <0 0xe615026c 0 4>;
1133 clocks = <&pll1_div2_clk>;
1134 #clock-cells = <0>;
1135 };
1136 mmc0_clk: mmc0@e6150240 {
1137 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1138 reg = <0 0xe6150240 0 4>;
1139 clocks = <&pll1_div2_clk>;
1140 #clock-cells = <0>;
1141 };
1142 mmc1_clk: mmc1@e6150244 {
1143 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1144 reg = <0 0xe6150244 0 4>;
1145 clocks = <&pll1_div2_clk>;
1146 #clock-cells = <0>;
1147 };
1148 ssp_clk: ssp@e6150248 {
1149 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1150 reg = <0 0xe6150248 0 4>;
1151 clocks = <&pll1_div2_clk>;
1152 #clock-cells = <0>;
1153 };
1154 ssprs_clk: ssprs@e615024c {
1155 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1156 reg = <0 0xe615024c 0 4>;
1157 clocks = <&pll1_div2_clk>;
1158 #clock-cells = <0>;
1159 };
1160
1161 /* Fixed factor clocks */
1162 pll1_div2_clk: pll1_div2 {
1163 compatible = "fixed-factor-clock";
1164 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1165 #clock-cells = <0>;
1166 clock-div = <2>;
1167 clock-mult = <1>;
1168 };
1169 z2_clk: z2 {
1170 compatible = "fixed-factor-clock";
1171 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1172 #clock-cells = <0>;
1173 clock-div = <2>;
1174 clock-mult = <1>;
1175 };
1176 zg_clk: zg {
1177 compatible = "fixed-factor-clock";
1178 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1179 #clock-cells = <0>;
1180 clock-div = <3>;
1181 clock-mult = <1>;
1182 };
1183 zx_clk: zx {
1184 compatible = "fixed-factor-clock";
1185 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1186 #clock-cells = <0>;
1187 clock-div = <3>;
1188 clock-mult = <1>;
1189 };
1190 zs_clk: zs {
1191 compatible = "fixed-factor-clock";
1192 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1193 #clock-cells = <0>;
1194 clock-div = <6>;
1195 clock-mult = <1>;
1196 };
1197 hp_clk: hp {
1198 compatible = "fixed-factor-clock";
1199 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1200 #clock-cells = <0>;
1201 clock-div = <12>;
1202 clock-mult = <1>;
1203 };
1204 i_clk: i {
1205 compatible = "fixed-factor-clock";
1206 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1207 #clock-cells = <0>;
1208 clock-div = <2>;
1209 clock-mult = <1>;
1210 };
1211 b_clk: b {
1212 compatible = "fixed-factor-clock";
1213 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1214 #clock-cells = <0>;
1215 clock-div = <12>;
1216 clock-mult = <1>;
1217 };
1218 p_clk: p {
1219 compatible = "fixed-factor-clock";
1220 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1221 #clock-cells = <0>;
1222 clock-div = <24>;
1223 clock-mult = <1>;
1224 };
1225 cl_clk: cl {
1226 compatible = "fixed-factor-clock";
1227 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1228 #clock-cells = <0>;
1229 clock-div = <48>;
1230 clock-mult = <1>;
1231 };
1232 m2_clk: m2 {
1233 compatible = "fixed-factor-clock";
1234 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1235 #clock-cells = <0>;
1236 clock-div = <8>;
1237 clock-mult = <1>;
1238 };
1239 imp_clk: imp {
1240 compatible = "fixed-factor-clock";
1241 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1242 #clock-cells = <0>;
1243 clock-div = <4>;
1244 clock-mult = <1>;
1245 };
1246 rclk_clk: rclk {
1247 compatible = "fixed-factor-clock";
1248 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1249 #clock-cells = <0>;
1250 clock-div = <(48 * 1024)>;
1251 clock-mult = <1>;
1252 };
1253 oscclk_clk: oscclk {
1254 compatible = "fixed-factor-clock";
1255 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1256 #clock-cells = <0>;
1257 clock-div = <(12 * 1024)>;
1258 clock-mult = <1>;
1259 };
1260 zb3_clk: zb3 {
1261 compatible = "fixed-factor-clock";
1262 clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
1263 #clock-cells = <0>;
1264 clock-div = <4>;
1265 clock-mult = <1>;
1266 };
1267 zb3d2_clk: zb3d2 {
1268 compatible = "fixed-factor-clock";
1269 clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
1270 #clock-cells = <0>;
1271 clock-div = <8>;
1272 clock-mult = <1>;
1273 };
1274 ddr_clk: ddr {
1275 compatible = "fixed-factor-clock";
1276 clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
1277 #clock-cells = <0>;
1278 clock-div = <8>;
1279 clock-mult = <1>;
1280 };
1281 mp_clk: mp {
1282 compatible = "fixed-factor-clock";
1283 clocks = <&pll1_div2_clk>;
1284 #clock-cells = <0>;
1285 clock-div = <15>;
1286 clock-mult = <1>;
1287 };
1288 cp_clk: cp {
1289 compatible = "fixed-factor-clock";
1290 clocks = <&extal_clk>;
1291 #clock-cells = <0>;
1292 clock-div = <2>;
1293 clock-mult = <1>;
1294 };
1295
1296 /* Gate clocks */
1297 mstp0_clks: mstp0_clks@e6150130 {
1298 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1299 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
1300 clocks = <&mp_clk>;
1301 #clock-cells = <1>;
1302 clock-indices = <R8A7790_CLK_MSIOF0>;
1303 clock-output-names = "msiof0";
1304 };
1305 mstp1_clks: mstp1_clks@e6150134 {
1306 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1307 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
1308 clocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&m2_clk>,
1309 <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>, <&zs_clk>,
1310 <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
1311 <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
1312 #clock-cells = <1>;
1313 clock-indices = <
1314 R8A7790_CLK_VCP1 R8A7790_CLK_VCP0 R8A7790_CLK_VPC1
1315 R8A7790_CLK_VPC0 R8A7790_CLK_JPU R8A7790_CLK_SSP1
1316 R8A7790_CLK_TMU1 R8A7790_CLK_3DG R8A7790_CLK_2DDMAC
1317 R8A7790_CLK_FDP1_2 R8A7790_CLK_FDP1_1 R8A7790_CLK_FDP1_0
1318 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2 R8A7790_CLK_CMT0
1319 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1 R8A7790_CLK_VSP1_DU0
1320 R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S
1321 >;
1322 clock-output-names =
1323 "vcp1", "vcp0", "vpc1", "vpc0", "jpu", "ssp1",
1324 "tmu1", "3dg", "2ddmac", "fdp1-2", "fdp1-1",
1325 "fdp1-0", "tmu3", "tmu2", "cmt0", "tmu0",
1326 "vsp1-du1", "vsp1-du0", "vsp1-rt", "vsp1-sy";
1327 };
1328 mstp2_clks: mstp2_clks@e6150138 {
1329 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1330 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
1331 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
1332 <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&zs_clk>,
1333 <&zs_clk>;
1334 #clock-cells = <1>;
1335 clock-indices = <
1336 R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0
1337 R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1
1338 R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2
1339 R8A7790_CLK_SYS_DMAC1 R8A7790_CLK_SYS_DMAC0
1340 >;
1341 clock-output-names =
1342 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
1343 "scifb1", "msiof1", "msiof3", "scifb2",
1344 "sys-dmac1", "sys-dmac0";
1345 };
1346 mstp3_clks: mstp3_clks@e615013c {
1347 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1348 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
1349 clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&p_clk>, <&sd3_clk>,
1350 <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>,
1351 <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>,
1352 <&hp_clk>, <&hp_clk>;
1353 #clock-cells = <1>;
1354 clock-indices = <
1355 R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SCIF2 R8A7790_CLK_SDHI3
1356 R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0
1357 R8A7790_CLK_IIC0 R8A7790_CLK_PCIEC R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1
1358 R8A7790_CLK_USBDMAC0 R8A7790_CLK_USBDMAC1
1359 >;
1360 clock-output-names =
1361 "iic2", "tpu0", "mmcif1", "scif2", "sdhi3",
1362 "sdhi2", "sdhi1", "sdhi0", "mmcif0",
1363 "iic0", "pciec", "iic1", "ssusb", "cmt1",
1364 "usbdmac0", "usbdmac1";
1365 };
1366 mstp4_clks: mstp4_clks@e6150140 {
1367 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1368 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
1369 clocks = <&cp_clk>;
1370 #clock-cells = <1>;
1371 clock-indices = <R8A7790_CLK_IRQC>;
1372 clock-output-names = "irqc";
1373 };
1374 mstp5_clks: mstp5_clks@e6150144 {
1375 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1376 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
1377 clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7790_CLK_ADSP>,
1378 <&extal_clk>, <&p_clk>;
1379 #clock-cells = <1>;
1380 clock-indices = <
1381 R8A7790_CLK_AUDIO_DMAC0 R8A7790_CLK_AUDIO_DMAC1
1382 R8A7790_CLK_ADSP_MOD R8A7790_CLK_THERMAL
1383 R8A7790_CLK_PWM
1384 >;
1385 clock-output-names = "audmac0", "audmac1", "adsp_mod",
1386 "thermal", "pwm";
1387 };
1388 mstp7_clks: mstp7_clks@e615014c {
1389 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1390 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
1391 clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
1392 <&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>,
1393 <&zx_clk>;
1394 #clock-cells = <1>;
1395 clock-indices = <
1396 R8A7790_CLK_EHCI R8A7790_CLK_HSUSB R8A7790_CLK_HSCIF1
1397 R8A7790_CLK_HSCIF0 R8A7790_CLK_SCIF1 R8A7790_CLK_SCIF0
1398 R8A7790_CLK_DU2 R8A7790_CLK_DU1 R8A7790_CLK_DU0
1399 R8A7790_CLK_LVDS1 R8A7790_CLK_LVDS0
1400 >;
1401 clock-output-names =
1402 "ehci", "hsusb", "hscif1", "hscif0", "scif1",
1403 "scif0", "du2", "du1", "du0", "lvds1", "lvds0";
1404 };
1405 mstp8_clks: mstp8_clks@e6150990 {
1406 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1407 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
1408 clocks = <&hp_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
1409 <&zg_clk>, <&hp_clk>, <&p_clk>, <&zs_clk>,
1410 <&zs_clk>;
1411 #clock-cells = <1>;
1412 clock-indices = <
1413 R8A7790_CLK_MLB R8A7790_CLK_VIN3 R8A7790_CLK_VIN2
1414 R8A7790_CLK_VIN1 R8A7790_CLK_VIN0
1415 R8A7790_CLK_ETHERAVB R8A7790_CLK_ETHER
1416 R8A7790_CLK_SATA1 R8A7790_CLK_SATA0
1417 >;
1418 clock-output-names =
1419 "mlb", "vin3", "vin2", "vin1", "vin0",
1420 "etheravb", "ether", "sata1", "sata0";
1421 };
1422 mstp9_clks: mstp9_clks@e6150994 {
1423 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1424 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
1425 clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>,
1426 <&cp_clk>, <&cp_clk>, <&cp_clk>,
1427 <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>, <&cp_clk>,
1428 <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
1429 #clock-cells = <1>;
1430 clock-indices = <
1431 R8A7790_CLK_GPIO5 R8A7790_CLK_GPIO4 R8A7790_CLK_GPIO3
1432 R8A7790_CLK_GPIO2 R8A7790_CLK_GPIO1 R8A7790_CLK_GPIO0
1433 R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD R8A7790_CLK_IICDVFS
1434 R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1 R8A7790_CLK_I2C0
1435 >;
1436 clock-output-names =
1437 "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0",
1438 "rcan1", "rcan0", "qspi_mod", "iic3",
1439 "i2c3", "i2c2", "i2c1", "i2c0";
1440 };
1441 mstp10_clks: mstp10_clks@e6150998 {
1442 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1443 reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
1444 clocks = <&p_clk>,
1445 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1446 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1447 <&p_clk>,
1448 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1449 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1450 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1451 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1452 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1453 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1454 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>;
1455
1456 #clock-cells = <1>;
1457 clock-indices = <
1458 R8A7790_CLK_SSI_ALL
1459 R8A7790_CLK_SSI9 R8A7790_CLK_SSI8 R8A7790_CLK_SSI7 R8A7790_CLK_SSI6 R8A7790_CLK_SSI5
1460 R8A7790_CLK_SSI4 R8A7790_CLK_SSI3 R8A7790_CLK_SSI2 R8A7790_CLK_SSI1 R8A7790_CLK_SSI0
1461 R8A7790_CLK_SCU_ALL
1462 R8A7790_CLK_SCU_DVC1 R8A7790_CLK_SCU_DVC0
1463 R8A7790_CLK_SCU_CTU1_MIX1 R8A7790_CLK_SCU_CTU0_MIX0
1464 R8A7790_CLK_SCU_SRC9 R8A7790_CLK_SCU_SRC8 R8A7790_CLK_SCU_SRC7 R8A7790_CLK_SCU_SRC6 R8A7790_CLK_SCU_SRC5
1465 R8A7790_CLK_SCU_SRC4 R8A7790_CLK_SCU_SRC3 R8A7790_CLK_SCU_SRC2 R8A7790_CLK_SCU_SRC1 R8A7790_CLK_SCU_SRC0
1466 >;
1467 clock-output-names =
1468 "ssi-all",
1469 "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
1470 "ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
1471 "scu-all",
1472 "scu-dvc1", "scu-dvc0",
1473 "scu-ctu1-mix1", "scu-ctu0-mix0",
1474 "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
1475 "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
1476 };
1477 };
1478
1479 prr: chipid@ff000044 {
1480 compatible = "renesas,prr";
1481 reg = <0 0xff000044 0 4>;
1482 };
1483
1484 rst: reset-controller@e6160000 {
1485 compatible = "renesas,r8a7790-rst";
1486 reg = <0 0xe6160000 0 0x0100>;
1487 };
1488
1489 sysc: system-controller@e6180000 {
1490 compatible = "renesas,r8a7790-sysc";
1491 reg = <0 0xe6180000 0 0x0200>;
1492 #power-domain-cells = <1>;
1493 };
1494
1495 qspi: spi@e6b10000 {
1496 compatible = "renesas,qspi-r8a7790", "renesas,qspi";
1497 reg = <0 0xe6b10000 0 0x2c>;
1498 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
1499 clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>;
1500 dmas = <&dmac0 0x17>, <&dmac0 0x18>,
1501 <&dmac1 0x17>, <&dmac1 0x18>;
1502 dma-names = "tx", "rx", "tx", "rx";
1503 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1504 num-cs = <1>;
1505 #address-cells = <1>;
1506 #size-cells = <0>;
1507 status = "disabled";
1508 };
1509
1510 msiof0: spi@e6e20000 {
1511 compatible = "renesas,msiof-r8a7790",
1512 "renesas,rcar-gen2-msiof";
1513 reg = <0 0xe6e20000 0 0x0064>;
1514 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1515 clocks = <&mstp0_clks R8A7790_CLK_MSIOF0>;
1516 dmas = <&dmac0 0x51>, <&dmac0 0x52>,
1517 <&dmac1 0x51>, <&dmac1 0x52>;
1518 dma-names = "tx", "rx", "tx", "rx";
1519 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1520 #address-cells = <1>;
1521 #size-cells = <0>;
1522 status = "disabled";
1523 };
1524
1525 msiof1: spi@e6e10000 {
1526 compatible = "renesas,msiof-r8a7790",
1527 "renesas,rcar-gen2-msiof";
1528 reg = <0 0xe6e10000 0 0x0064>;
1529 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1530 clocks = <&mstp2_clks R8A7790_CLK_MSIOF1>;
1531 dmas = <&dmac0 0x55>, <&dmac0 0x56>,
1532 <&dmac1 0x55>, <&dmac1 0x56>;
1533 dma-names = "tx", "rx", "tx", "rx";
1534 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1535 #address-cells = <1>;
1536 #size-cells = <0>;
1537 status = "disabled";
1538 };
1539
1540 msiof2: spi@e6e00000 {
1541 compatible = "renesas,msiof-r8a7790",
1542 "renesas,rcar-gen2-msiof";
1543 reg = <0 0xe6e00000 0 0x0064>;
1544 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1545 clocks = <&mstp2_clks R8A7790_CLK_MSIOF2>;
1546 dmas = <&dmac0 0x41>, <&dmac0 0x42>,
1547 <&dmac1 0x41>, <&dmac1 0x42>;
1548 dma-names = "tx", "rx", "tx", "rx";
1549 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1550 #address-cells = <1>;
1551 #size-cells = <0>;
1552 status = "disabled";
1553 };
1554
1555 msiof3: spi@e6c90000 {
1556 compatible = "renesas,msiof-r8a7790",
1557 "renesas,rcar-gen2-msiof";
1558 reg = <0 0xe6c90000 0 0x0064>;
1559 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1560 clocks = <&mstp2_clks R8A7790_CLK_MSIOF3>;
1561 dmas = <&dmac0 0x45>, <&dmac0 0x46>,
1562 <&dmac1 0x45>, <&dmac1 0x46>;
1563 dma-names = "tx", "rx", "tx", "rx";
1564 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1565 #address-cells = <1>;
1566 #size-cells = <0>;
1567 status = "disabled";
1568 };
1569
1570 xhci: usb@ee000000 {
1571 compatible = "renesas,xhci-r8a7790", "renesas,rcar-gen2-xhci";
1572 reg = <0 0xee000000 0 0xc00>;
1573 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1574 clocks = <&mstp3_clks R8A7790_CLK_SSUSB>;
1575 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1576 phys = <&usb2 1>;
1577 phy-names = "usb";
1578 status = "disabled";
1579 };
1580
1581 pci0: pci@ee090000 {
1582 compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
1583 device_type = "pci";
1584 reg = <0 0xee090000 0 0xc00>,
1585 <0 0xee080000 0 0x1100>;
1586 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1587 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1588 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1589 status = "disabled";
1590
1591 bus-range = <0 0>;
1592 #address-cells = <3>;
1593 #size-cells = <2>;
1594 #interrupt-cells = <1>;
1595 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
1596 interrupt-map-mask = <0xff00 0 0 0x7>;
1597 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
1598 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
1599 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1600
1601 usb@0,1 {
1602 reg = <0x800 0 0 0 0>;
1603 device_type = "pci";
1604 phys = <&usb0 0>;
1605 phy-names = "usb";
1606 };
1607
1608 usb@0,2 {
1609 reg = <0x1000 0 0 0 0>;
1610 device_type = "pci";
1611 phys = <&usb0 0>;
1612 phy-names = "usb";
1613 };
1614 };
1615
1616 pci1: pci@ee0b0000 {
1617 compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
1618 device_type = "pci";
1619 reg = <0 0xee0b0000 0 0xc00>,
1620 <0 0xee0a0000 0 0x1100>;
1621 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1622 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1623 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1624 status = "disabled";
1625
1626 bus-range = <1 1>;
1627 #address-cells = <3>;
1628 #size-cells = <2>;
1629 #interrupt-cells = <1>;
1630 ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>;
1631 interrupt-map-mask = <0xff00 0 0 0x7>;
1632 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH
1633 0x0800 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH
1634 0x1000 0 0 2 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1635 };
1636
1637 pci2: pci@ee0d0000 {
1638 compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
1639 device_type = "pci";
1640 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1641 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1642 reg = <0 0xee0d0000 0 0xc00>,
1643 <0 0xee0c0000 0 0x1100>;
1644 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1645 status = "disabled";
1646
1647 bus-range = <2 2>;
1648 #address-cells = <3>;
1649 #size-cells = <2>;
1650 #interrupt-cells = <1>;
1651 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
1652 interrupt-map-mask = <0xff00 0 0 0x7>;
1653 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
1654 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
1655 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1656
1657 usb@0,1 {
1658 reg = <0x800 0 0 0 0>;
1659 device_type = "pci";
1660 phys = <&usb2 0>;
1661 phy-names = "usb";
1662 };
1663
1664 usb@0,2 {
1665 reg = <0x1000 0 0 0 0>;
1666 device_type = "pci";
1667 phys = <&usb2 0>;
1668 phy-names = "usb";
1669 };
1670 };
1671
1672 pciec: pcie@fe000000 {
1673 compatible = "renesas,pcie-r8a7790", "renesas,pcie-rcar-gen2";
1674 reg = <0 0xfe000000 0 0x80000>;
1675 #address-cells = <3>;
1676 #size-cells = <2>;
1677 bus-range = <0x00 0xff>;
1678 device_type = "pci";
1679 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
1680 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
1681 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
1682 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1683 /* Map all possible DDR as inbound ranges */
1684 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
1685 0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>;
1686 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1687 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1688 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1689 #interrupt-cells = <1>;
1690 interrupt-map-mask = <0 0 0 0>;
1691 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1692 clocks = <&mstp3_clks R8A7790_CLK_PCIEC>, <&pcie_bus_clk>;
1693 clock-names = "pcie", "pcie_bus";
1694 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1695 status = "disabled";
1696 };
1697
1698 rcar_sound: sound@ec500000 {
1699 /*
1700 * #sound-dai-cells is required
1701 *
1702 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1703 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1704 */
1705 compatible = "renesas,rcar_sound-r8a7790", "renesas,rcar_sound-gen2";
1706 reg = <0 0xec500000 0 0x1000>, /* SCU */
1707 <0 0xec5a0000 0 0x100>, /* ADG */
1708 <0 0xec540000 0 0x1000>, /* SSIU */
1709 <0 0xec541000 0 0x280>, /* SSI */
1710 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
1711 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1712
1713 clocks = <&mstp10_clks R8A7790_CLK_SSI_ALL>,
1714 <&mstp10_clks R8A7790_CLK_SSI9>, <&mstp10_clks R8A7790_CLK_SSI8>,
1715 <&mstp10_clks R8A7790_CLK_SSI7>, <&mstp10_clks R8A7790_CLK_SSI6>,
1716 <&mstp10_clks R8A7790_CLK_SSI5>, <&mstp10_clks R8A7790_CLK_SSI4>,
1717 <&mstp10_clks R8A7790_CLK_SSI3>, <&mstp10_clks R8A7790_CLK_SSI2>,
1718 <&mstp10_clks R8A7790_CLK_SSI1>, <&mstp10_clks R8A7790_CLK_SSI0>,
1719 <&mstp10_clks R8A7790_CLK_SCU_SRC9>, <&mstp10_clks R8A7790_CLK_SCU_SRC8>,
1720 <&mstp10_clks R8A7790_CLK_SCU_SRC7>, <&mstp10_clks R8A7790_CLK_SCU_SRC6>,
1721 <&mstp10_clks R8A7790_CLK_SCU_SRC5>, <&mstp10_clks R8A7790_CLK_SCU_SRC4>,
1722 <&mstp10_clks R8A7790_CLK_SCU_SRC3>, <&mstp10_clks R8A7790_CLK_SCU_SRC2>,
1723 <&mstp10_clks R8A7790_CLK_SCU_SRC1>, <&mstp10_clks R8A7790_CLK_SCU_SRC0>,
1724 <&mstp10_clks R8A7790_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7790_CLK_SCU_CTU1_MIX1>,
1725 <&mstp10_clks R8A7790_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7790_CLK_SCU_CTU1_MIX1>,
1726 <&mstp10_clks R8A7790_CLK_SCU_DVC0>, <&mstp10_clks R8A7790_CLK_SCU_DVC1>,
1727 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
1728 clock-names = "ssi-all",
1729 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
1730 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
1731 "src.9", "src.8", "src.7", "src.6", "src.5",
1732 "src.4", "src.3", "src.2", "src.1", "src.0",
1733 "ctu.0", "ctu.1",
1734 "mix.0", "mix.1",
1735 "dvc.0", "dvc.1",
1736 "clk_a", "clk_b", "clk_c", "clk_i";
1737 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1738
1739 status = "disabled";
1740
1741 rcar_sound,dvc {
1742 dvc0: dvc-0 {
1743 dmas = <&audma0 0xbc>;
1744 dma-names = "tx";
1745 };
1746 dvc1: dvc-1 {
1747 dmas = <&audma0 0xbe>;
1748 dma-names = "tx";
1749 };
1750 };
1751
1752 rcar_sound,mix {
1753 mix0: mix-0 { };
1754 mix1: mix-1 { };
1755 };
1756
1757 rcar_sound,ctu {
1758 ctu00: ctu-0 { };
1759 ctu01: ctu-1 { };
1760 ctu02: ctu-2 { };
1761 ctu03: ctu-3 { };
1762 ctu10: ctu-4 { };
1763 ctu11: ctu-5 { };
1764 ctu12: ctu-6 { };
1765 ctu13: ctu-7 { };
1766 };
1767
1768 rcar_sound,src {
1769 src0: src-0 {
1770 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1771 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1772 dma-names = "rx", "tx";
1773 };
1774 src1: src-1 {
1775 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1776 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1777 dma-names = "rx", "tx";
1778 };
1779 src2: src-2 {
1780 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1781 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1782 dma-names = "rx", "tx";
1783 };
1784 src3: src-3 {
1785 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1786 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1787 dma-names = "rx", "tx";
1788 };
1789 src4: src-4 {
1790 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1791 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1792 dma-names = "rx", "tx";
1793 };
1794 src5: src-5 {
1795 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1796 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1797 dma-names = "rx", "tx";
1798 };
1799 src6: src-6 {
1800 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1801 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1802 dma-names = "rx", "tx";
1803 };
1804 src7: src-7 {
1805 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1806 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1807 dma-names = "rx", "tx";
1808 };
1809 src8: src-8 {
1810 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1811 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1812 dma-names = "rx", "tx";
1813 };
1814 src9: src-9 {
1815 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
1816 dmas = <&audma0 0x97>, <&audma1 0xba>;
1817 dma-names = "rx", "tx";
1818 };
1819 };
1820
1821 rcar_sound,ssi {
1822 ssi0: ssi-0 {
1823 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
1824 dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
1825 dma-names = "rx", "tx", "rxu", "txu";
1826 };
1827 ssi1: ssi-1 {
1828 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1829 dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
1830 dma-names = "rx", "tx", "rxu", "txu";
1831 };
1832 ssi2: ssi-2 {
1833 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
1834 dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
1835 dma-names = "rx", "tx", "rxu", "txu";
1836 };
1837 ssi3: ssi-3 {
1838 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1839 dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
1840 dma-names = "rx", "tx", "rxu", "txu";
1841 };
1842 ssi4: ssi-4 {
1843 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1844 dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
1845 dma-names = "rx", "tx", "rxu", "txu";
1846 };
1847 ssi5: ssi-5 {
1848 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1849 dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
1850 dma-names = "rx", "tx", "rxu", "txu";
1851 };
1852 ssi6: ssi-6 {
1853 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
1854 dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
1855 dma-names = "rx", "tx", "rxu", "txu";
1856 };
1857 ssi7: ssi-7 {
1858 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
1859 dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
1860 dma-names = "rx", "tx", "rxu", "txu";
1861 };
1862 ssi8: ssi-8 {
1863 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
1864 dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
1865 dma-names = "rx", "tx", "rxu", "txu";
1866 };
1867 ssi9: ssi-9 {
1868 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
1869 dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
1870 dma-names = "rx", "tx", "rxu", "txu";
1871 };
1872 };
1873 };
1874
1875 ipmmu_sy0: mmu@e6280000 {
1876 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
1877 reg = <0 0xe6280000 0 0x1000>;
1878 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
1879 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
1880 #iommu-cells = <1>;
1881 status = "disabled";
1882 };
1883
1884 ipmmu_sy1: mmu@e6290000 {
1885 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
1886 reg = <0 0xe6290000 0 0x1000>;
1887 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1888 #iommu-cells = <1>;
1889 status = "disabled";
1890 };
1891
1892 ipmmu_ds: mmu@e6740000 {
1893 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
1894 reg = <0 0xe6740000 0 0x1000>;
1895 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
1896 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
1897 #iommu-cells = <1>;
1898 status = "disabled";
1899 };
1900
1901 ipmmu_mp: mmu@ec680000 {
1902 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
1903 reg = <0 0xec680000 0 0x1000>;
1904 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1905 #iommu-cells = <1>;
1906 status = "disabled";
1907 };
1908
1909 ipmmu_mx: mmu@fe951000 {
1910 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
1911 reg = <0 0xfe951000 0 0x1000>;
1912 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
1913 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1914 #iommu-cells = <1>;
1915 status = "disabled";
1916 };
1917
1918 ipmmu_rt: mmu@ffc80000 {
1919 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
1920 reg = <0 0xffc80000 0 0x1000>;
1921 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
1922 #iommu-cells = <1>;
1923 status = "disabled";
1924 };
1925 };
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