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ARM: dts: sunxi: Add address- and size-cells properties to the mmc ctrl nodes
[mirror_ubuntu-artful-kernel.git] / arch / arm / boot / dts / r8a7791.dtsi
1 /*
2 * Device Tree Source for the r8a7791 SoC
3 *
4 * Copyright (C) 2013-2015 Renesas Electronics Corporation
5 * Copyright (C) 2013-2014 Renesas Solutions Corp.
6 * Copyright (C) 2014 Cogent Embedded Inc.
7 *
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
11 */
12
13 #include <dt-bindings/clock/r8a7791-clock.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/interrupt-controller/irq.h>
16
17 / {
18 compatible = "renesas,r8a7791";
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
22
23 aliases {
24 i2c0 = &i2c0;
25 i2c1 = &i2c1;
26 i2c2 = &i2c2;
27 i2c3 = &i2c3;
28 i2c4 = &i2c4;
29 i2c5 = &i2c5;
30 i2c6 = &i2c6;
31 i2c7 = &i2c7;
32 i2c8 = &i2c8;
33 spi0 = &qspi;
34 spi1 = &msiof0;
35 spi2 = &msiof1;
36 spi3 = &msiof2;
37 vin0 = &vin0;
38 vin1 = &vin1;
39 vin2 = &vin2;
40 };
41
42 cpus {
43 #address-cells = <1>;
44 #size-cells = <0>;
45
46 cpu0: cpu@0 {
47 device_type = "cpu";
48 compatible = "arm,cortex-a15";
49 reg = <0>;
50 clock-frequency = <1500000000>;
51 voltage-tolerance = <1>; /* 1% */
52 clocks = <&cpg_clocks R8A7791_CLK_Z>;
53 clock-latency = <300000>; /* 300 us */
54
55 /* kHz - uV - OPPs unknown yet */
56 operating-points = <1500000 1000000>,
57 <1312500 1000000>,
58 <1125000 1000000>,
59 < 937500 1000000>,
60 < 750000 1000000>,
61 < 375000 1000000>;
62 };
63
64 cpu1: cpu@1 {
65 device_type = "cpu";
66 compatible = "arm,cortex-a15";
67 reg = <1>;
68 clock-frequency = <1500000000>;
69 };
70 };
71
72 gic: interrupt-controller@f1001000 {
73 compatible = "arm,cortex-a15-gic";
74 #interrupt-cells = <3>;
75 #address-cells = <0>;
76 interrupt-controller;
77 reg = <0 0xf1001000 0 0x1000>,
78 <0 0xf1002000 0 0x1000>,
79 <0 0xf1004000 0 0x2000>,
80 <0 0xf1006000 0 0x2000>;
81 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
82 };
83
84 gpio0: gpio@e6050000 {
85 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
86 reg = <0 0xe6050000 0 0x50>;
87 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
88 #gpio-cells = <2>;
89 gpio-controller;
90 gpio-ranges = <&pfc 0 0 32>;
91 #interrupt-cells = <2>;
92 interrupt-controller;
93 clocks = <&mstp9_clks R8A7791_CLK_GPIO0>;
94 };
95
96 gpio1: gpio@e6051000 {
97 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
98 reg = <0 0xe6051000 0 0x50>;
99 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
100 #gpio-cells = <2>;
101 gpio-controller;
102 gpio-ranges = <&pfc 0 32 32>;
103 #interrupt-cells = <2>;
104 interrupt-controller;
105 clocks = <&mstp9_clks R8A7791_CLK_GPIO1>;
106 };
107
108 gpio2: gpio@e6052000 {
109 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
110 reg = <0 0xe6052000 0 0x50>;
111 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
112 #gpio-cells = <2>;
113 gpio-controller;
114 gpio-ranges = <&pfc 0 64 32>;
115 #interrupt-cells = <2>;
116 interrupt-controller;
117 clocks = <&mstp9_clks R8A7791_CLK_GPIO2>;
118 };
119
120 gpio3: gpio@e6053000 {
121 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
122 reg = <0 0xe6053000 0 0x50>;
123 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
124 #gpio-cells = <2>;
125 gpio-controller;
126 gpio-ranges = <&pfc 0 96 32>;
127 #interrupt-cells = <2>;
128 interrupt-controller;
129 clocks = <&mstp9_clks R8A7791_CLK_GPIO3>;
130 };
131
132 gpio4: gpio@e6054000 {
133 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
134 reg = <0 0xe6054000 0 0x50>;
135 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
136 #gpio-cells = <2>;
137 gpio-controller;
138 gpio-ranges = <&pfc 0 128 32>;
139 #interrupt-cells = <2>;
140 interrupt-controller;
141 clocks = <&mstp9_clks R8A7791_CLK_GPIO4>;
142 };
143
144 gpio5: gpio@e6055000 {
145 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
146 reg = <0 0xe6055000 0 0x50>;
147 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
148 #gpio-cells = <2>;
149 gpio-controller;
150 gpio-ranges = <&pfc 0 160 32>;
151 #interrupt-cells = <2>;
152 interrupt-controller;
153 clocks = <&mstp9_clks R8A7791_CLK_GPIO5>;
154 };
155
156 gpio6: gpio@e6055400 {
157 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
158 reg = <0 0xe6055400 0 0x50>;
159 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
160 #gpio-cells = <2>;
161 gpio-controller;
162 gpio-ranges = <&pfc 0 192 32>;
163 #interrupt-cells = <2>;
164 interrupt-controller;
165 clocks = <&mstp9_clks R8A7791_CLK_GPIO6>;
166 };
167
168 gpio7: gpio@e6055800 {
169 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
170 reg = <0 0xe6055800 0 0x50>;
171 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
172 #gpio-cells = <2>;
173 gpio-controller;
174 gpio-ranges = <&pfc 0 224 26>;
175 #interrupt-cells = <2>;
176 interrupt-controller;
177 clocks = <&mstp9_clks R8A7791_CLK_GPIO7>;
178 };
179
180 thermal@e61f0000 {
181 compatible = "renesas,thermal-r8a7791", "renesas,rcar-thermal";
182 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
183 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
184 clocks = <&mstp5_clks R8A7791_CLK_THERMAL>;
185 };
186
187 timer {
188 compatible = "arm,armv7-timer";
189 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
190 <1 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
191 <1 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
192 <1 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
193 };
194
195 cmt0: timer@ffca0000 {
196 compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2";
197 reg = <0 0xffca0000 0 0x1004>;
198 interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
199 <0 143 IRQ_TYPE_LEVEL_HIGH>;
200 clocks = <&mstp1_clks R8A7791_CLK_CMT0>;
201 clock-names = "fck";
202
203 renesas,channels-mask = <0x60>;
204
205 status = "disabled";
206 };
207
208 cmt1: timer@e6130000 {
209 compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2";
210 reg = <0 0xe6130000 0 0x1004>;
211 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
212 <0 121 IRQ_TYPE_LEVEL_HIGH>,
213 <0 122 IRQ_TYPE_LEVEL_HIGH>,
214 <0 123 IRQ_TYPE_LEVEL_HIGH>,
215 <0 124 IRQ_TYPE_LEVEL_HIGH>,
216 <0 125 IRQ_TYPE_LEVEL_HIGH>,
217 <0 126 IRQ_TYPE_LEVEL_HIGH>,
218 <0 127 IRQ_TYPE_LEVEL_HIGH>;
219 clocks = <&mstp3_clks R8A7791_CLK_CMT1>;
220 clock-names = "fck";
221
222 renesas,channels-mask = <0xff>;
223
224 status = "disabled";
225 };
226
227 irqc0: interrupt-controller@e61c0000 {
228 compatible = "renesas,irqc-r8a7791", "renesas,irqc";
229 #interrupt-cells = <2>;
230 interrupt-controller;
231 reg = <0 0xe61c0000 0 0x200>;
232 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
233 <0 1 IRQ_TYPE_LEVEL_HIGH>,
234 <0 2 IRQ_TYPE_LEVEL_HIGH>,
235 <0 3 IRQ_TYPE_LEVEL_HIGH>,
236 <0 12 IRQ_TYPE_LEVEL_HIGH>,
237 <0 13 IRQ_TYPE_LEVEL_HIGH>,
238 <0 14 IRQ_TYPE_LEVEL_HIGH>,
239 <0 15 IRQ_TYPE_LEVEL_HIGH>,
240 <0 16 IRQ_TYPE_LEVEL_HIGH>,
241 <0 17 IRQ_TYPE_LEVEL_HIGH>;
242 };
243
244 dmac0: dma-controller@e6700000 {
245 compatible = "renesas,rcar-dmac";
246 reg = <0 0xe6700000 0 0x20000>;
247 interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
248 0 200 IRQ_TYPE_LEVEL_HIGH
249 0 201 IRQ_TYPE_LEVEL_HIGH
250 0 202 IRQ_TYPE_LEVEL_HIGH
251 0 203 IRQ_TYPE_LEVEL_HIGH
252 0 204 IRQ_TYPE_LEVEL_HIGH
253 0 205 IRQ_TYPE_LEVEL_HIGH
254 0 206 IRQ_TYPE_LEVEL_HIGH
255 0 207 IRQ_TYPE_LEVEL_HIGH
256 0 208 IRQ_TYPE_LEVEL_HIGH
257 0 209 IRQ_TYPE_LEVEL_HIGH
258 0 210 IRQ_TYPE_LEVEL_HIGH
259 0 211 IRQ_TYPE_LEVEL_HIGH
260 0 212 IRQ_TYPE_LEVEL_HIGH
261 0 213 IRQ_TYPE_LEVEL_HIGH
262 0 214 IRQ_TYPE_LEVEL_HIGH>;
263 interrupt-names = "error",
264 "ch0", "ch1", "ch2", "ch3",
265 "ch4", "ch5", "ch6", "ch7",
266 "ch8", "ch9", "ch10", "ch11",
267 "ch12", "ch13", "ch14";
268 clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC0>;
269 clock-names = "fck";
270 #dma-cells = <1>;
271 dma-channels = <15>;
272 };
273
274 dmac1: dma-controller@e6720000 {
275 compatible = "renesas,rcar-dmac";
276 reg = <0 0xe6720000 0 0x20000>;
277 interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
278 0 216 IRQ_TYPE_LEVEL_HIGH
279 0 217 IRQ_TYPE_LEVEL_HIGH
280 0 218 IRQ_TYPE_LEVEL_HIGH
281 0 219 IRQ_TYPE_LEVEL_HIGH
282 0 308 IRQ_TYPE_LEVEL_HIGH
283 0 309 IRQ_TYPE_LEVEL_HIGH
284 0 310 IRQ_TYPE_LEVEL_HIGH
285 0 311 IRQ_TYPE_LEVEL_HIGH
286 0 312 IRQ_TYPE_LEVEL_HIGH
287 0 313 IRQ_TYPE_LEVEL_HIGH
288 0 314 IRQ_TYPE_LEVEL_HIGH
289 0 315 IRQ_TYPE_LEVEL_HIGH
290 0 316 IRQ_TYPE_LEVEL_HIGH
291 0 317 IRQ_TYPE_LEVEL_HIGH
292 0 318 IRQ_TYPE_LEVEL_HIGH>;
293 interrupt-names = "error",
294 "ch0", "ch1", "ch2", "ch3",
295 "ch4", "ch5", "ch6", "ch7",
296 "ch8", "ch9", "ch10", "ch11",
297 "ch12", "ch13", "ch14";
298 clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC1>;
299 clock-names = "fck";
300 #dma-cells = <1>;
301 dma-channels = <15>;
302 };
303
304 audma0: dma-controller@ec700000 {
305 compatible = "renesas,rcar-dmac";
306 reg = <0 0xec700000 0 0x10000>;
307 interrupts = <0 346 IRQ_TYPE_LEVEL_HIGH
308 0 320 IRQ_TYPE_LEVEL_HIGH
309 0 321 IRQ_TYPE_LEVEL_HIGH
310 0 322 IRQ_TYPE_LEVEL_HIGH
311 0 323 IRQ_TYPE_LEVEL_HIGH
312 0 324 IRQ_TYPE_LEVEL_HIGH
313 0 325 IRQ_TYPE_LEVEL_HIGH
314 0 326 IRQ_TYPE_LEVEL_HIGH
315 0 327 IRQ_TYPE_LEVEL_HIGH
316 0 328 IRQ_TYPE_LEVEL_HIGH
317 0 329 IRQ_TYPE_LEVEL_HIGH
318 0 330 IRQ_TYPE_LEVEL_HIGH
319 0 331 IRQ_TYPE_LEVEL_HIGH
320 0 332 IRQ_TYPE_LEVEL_HIGH>;
321 interrupt-names = "error",
322 "ch0", "ch1", "ch2", "ch3",
323 "ch4", "ch5", "ch6", "ch7",
324 "ch8", "ch9", "ch10", "ch11",
325 "ch12";
326 clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC0>;
327 clock-names = "fck";
328 #dma-cells = <1>;
329 dma-channels = <13>;
330 };
331
332 audma1: dma-controller@ec720000 {
333 compatible = "renesas,rcar-dmac";
334 reg = <0 0xec720000 0 0x10000>;
335 interrupts = <0 347 IRQ_TYPE_LEVEL_HIGH
336 0 333 IRQ_TYPE_LEVEL_HIGH
337 0 334 IRQ_TYPE_LEVEL_HIGH
338 0 335 IRQ_TYPE_LEVEL_HIGH
339 0 336 IRQ_TYPE_LEVEL_HIGH
340 0 337 IRQ_TYPE_LEVEL_HIGH
341 0 338 IRQ_TYPE_LEVEL_HIGH
342 0 339 IRQ_TYPE_LEVEL_HIGH
343 0 340 IRQ_TYPE_LEVEL_HIGH
344 0 341 IRQ_TYPE_LEVEL_HIGH
345 0 342 IRQ_TYPE_LEVEL_HIGH
346 0 343 IRQ_TYPE_LEVEL_HIGH
347 0 344 IRQ_TYPE_LEVEL_HIGH
348 0 345 IRQ_TYPE_LEVEL_HIGH>;
349 interrupt-names = "error",
350 "ch0", "ch1", "ch2", "ch3",
351 "ch4", "ch5", "ch6", "ch7",
352 "ch8", "ch9", "ch10", "ch11",
353 "ch12";
354 clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC1>;
355 clock-names = "fck";
356 #dma-cells = <1>;
357 dma-channels = <13>;
358 };
359
360 /* The memory map in the User's Manual maps the cores to bus numbers */
361 i2c0: i2c@e6508000 {
362 #address-cells = <1>;
363 #size-cells = <0>;
364 compatible = "renesas,i2c-r8a7791";
365 reg = <0 0xe6508000 0 0x40>;
366 interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
367 clocks = <&mstp9_clks R8A7791_CLK_I2C0>;
368 status = "disabled";
369 };
370
371 i2c1: i2c@e6518000 {
372 #address-cells = <1>;
373 #size-cells = <0>;
374 compatible = "renesas,i2c-r8a7791";
375 reg = <0 0xe6518000 0 0x40>;
376 interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
377 clocks = <&mstp9_clks R8A7791_CLK_I2C1>;
378 status = "disabled";
379 };
380
381 i2c2: i2c@e6530000 {
382 #address-cells = <1>;
383 #size-cells = <0>;
384 compatible = "renesas,i2c-r8a7791";
385 reg = <0 0xe6530000 0 0x40>;
386 interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
387 clocks = <&mstp9_clks R8A7791_CLK_I2C2>;
388 status = "disabled";
389 };
390
391 i2c3: i2c@e6540000 {
392 #address-cells = <1>;
393 #size-cells = <0>;
394 compatible = "renesas,i2c-r8a7791";
395 reg = <0 0xe6540000 0 0x40>;
396 interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
397 clocks = <&mstp9_clks R8A7791_CLK_I2C3>;
398 status = "disabled";
399 };
400
401 i2c4: i2c@e6520000 {
402 #address-cells = <1>;
403 #size-cells = <0>;
404 compatible = "renesas,i2c-r8a7791";
405 reg = <0 0xe6520000 0 0x40>;
406 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
407 clocks = <&mstp9_clks R8A7791_CLK_I2C4>;
408 status = "disabled";
409 };
410
411 i2c5: i2c@e6528000 {
412 /* doesn't need pinmux */
413 #address-cells = <1>;
414 #size-cells = <0>;
415 compatible = "renesas,i2c-r8a7791";
416 reg = <0 0xe6528000 0 0x40>;
417 interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
418 clocks = <&mstp9_clks R8A7791_CLK_I2C5>;
419 status = "disabled";
420 };
421
422 i2c6: i2c@e60b0000 {
423 /* doesn't need pinmux */
424 #address-cells = <1>;
425 #size-cells = <0>;
426 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
427 reg = <0 0xe60b0000 0 0x425>;
428 interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>;
429 clocks = <&mstp9_clks R8A7791_CLK_IICDVFS>;
430 dmas = <&dmac0 0x77>, <&dmac0 0x78>;
431 dma-names = "tx", "rx";
432 status = "disabled";
433 };
434
435 i2c7: i2c@e6500000 {
436 #address-cells = <1>;
437 #size-cells = <0>;
438 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
439 reg = <0 0xe6500000 0 0x425>;
440 interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
441 clocks = <&mstp3_clks R8A7791_CLK_IIC0>;
442 dmas = <&dmac0 0x61>, <&dmac0 0x62>;
443 dma-names = "tx", "rx";
444 status = "disabled";
445 };
446
447 i2c8: i2c@e6510000 {
448 #address-cells = <1>;
449 #size-cells = <0>;
450 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
451 reg = <0 0xe6510000 0 0x425>;
452 interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>;
453 clocks = <&mstp3_clks R8A7791_CLK_IIC1>;
454 dmas = <&dmac0 0x65>, <&dmac0 0x66>;
455 dma-names = "tx", "rx";
456 status = "disabled";
457 };
458
459 pfc: pfc@e6060000 {
460 compatible = "renesas,pfc-r8a7791";
461 reg = <0 0xe6060000 0 0x250>;
462 #gpio-range-cells = <3>;
463 };
464
465 mmcif0: mmc@ee200000 {
466 compatible = "renesas,mmcif-r8a7791", "renesas,sh-mmcif";
467 reg = <0 0xee200000 0 0x80>;
468 interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
469 clocks = <&mstp3_clks R8A7791_CLK_MMCIF0>;
470 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
471 dma-names = "tx", "rx";
472 reg-io-width = <4>;
473 status = "disabled";
474 };
475
476 sdhi0: sd@ee100000 {
477 compatible = "renesas,sdhi-r8a7791";
478 reg = <0 0xee100000 0 0x328>;
479 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
480 clocks = <&mstp3_clks R8A7791_CLK_SDHI0>;
481 dmas = <&dmac1 0xcd>, <&dmac1 0xce>;
482 dma-names = "tx", "rx";
483 status = "disabled";
484 };
485
486 sdhi1: sd@ee140000 {
487 compatible = "renesas,sdhi-r8a7791";
488 reg = <0 0xee140000 0 0x100>;
489 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
490 clocks = <&mstp3_clks R8A7791_CLK_SDHI1>;
491 dmas = <&dmac1 0xc1>, <&dmac1 0xc2>;
492 dma-names = "tx", "rx";
493 status = "disabled";
494 };
495
496 sdhi2: sd@ee160000 {
497 compatible = "renesas,sdhi-r8a7791";
498 reg = <0 0xee160000 0 0x100>;
499 interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
500 clocks = <&mstp3_clks R8A7791_CLK_SDHI2>;
501 dmas = <&dmac1 0xd3>, <&dmac1 0xd4>;
502 dma-names = "tx", "rx";
503 status = "disabled";
504 };
505
506 scifa0: serial@e6c40000 {
507 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
508 reg = <0 0xe6c40000 0 64>;
509 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
510 clocks = <&mstp2_clks R8A7791_CLK_SCIFA0>;
511 clock-names = "sci_ick";
512 status = "disabled";
513 };
514
515 scifa1: serial@e6c50000 {
516 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
517 reg = <0 0xe6c50000 0 64>;
518 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
519 clocks = <&mstp2_clks R8A7791_CLK_SCIFA1>;
520 clock-names = "sci_ick";
521 status = "disabled";
522 };
523
524 scifa2: serial@e6c60000 {
525 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
526 reg = <0 0xe6c60000 0 64>;
527 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
528 clocks = <&mstp2_clks R8A7791_CLK_SCIFA2>;
529 clock-names = "sci_ick";
530 status = "disabled";
531 };
532
533 scifa3: serial@e6c70000 {
534 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
535 reg = <0 0xe6c70000 0 64>;
536 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
537 clocks = <&mstp11_clks R8A7791_CLK_SCIFA3>;
538 clock-names = "sci_ick";
539 status = "disabled";
540 };
541
542 scifa4: serial@e6c78000 {
543 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
544 reg = <0 0xe6c78000 0 64>;
545 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
546 clocks = <&mstp11_clks R8A7791_CLK_SCIFA4>;
547 clock-names = "sci_ick";
548 status = "disabled";
549 };
550
551 scifa5: serial@e6c80000 {
552 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
553 reg = <0 0xe6c80000 0 64>;
554 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
555 clocks = <&mstp11_clks R8A7791_CLK_SCIFA5>;
556 clock-names = "sci_ick";
557 status = "disabled";
558 };
559
560 scifb0: serial@e6c20000 {
561 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
562 reg = <0 0xe6c20000 0 64>;
563 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
564 clocks = <&mstp2_clks R8A7791_CLK_SCIFB0>;
565 clock-names = "sci_ick";
566 status = "disabled";
567 };
568
569 scifb1: serial@e6c30000 {
570 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
571 reg = <0 0xe6c30000 0 64>;
572 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
573 clocks = <&mstp2_clks R8A7791_CLK_SCIFB1>;
574 clock-names = "sci_ick";
575 status = "disabled";
576 };
577
578 scifb2: serial@e6ce0000 {
579 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
580 reg = <0 0xe6ce0000 0 64>;
581 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
582 clocks = <&mstp2_clks R8A7791_CLK_SCIFB2>;
583 clock-names = "sci_ick";
584 status = "disabled";
585 };
586
587 scif0: serial@e6e60000 {
588 compatible = "renesas,scif-r8a7791", "renesas,scif";
589 reg = <0 0xe6e60000 0 64>;
590 interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
591 clocks = <&mstp7_clks R8A7791_CLK_SCIF0>;
592 clock-names = "sci_ick";
593 status = "disabled";
594 };
595
596 scif1: serial@e6e68000 {
597 compatible = "renesas,scif-r8a7791", "renesas,scif";
598 reg = <0 0xe6e68000 0 64>;
599 interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
600 clocks = <&mstp7_clks R8A7791_CLK_SCIF1>;
601 clock-names = "sci_ick";
602 status = "disabled";
603 };
604
605 scif2: serial@e6e58000 {
606 compatible = "renesas,scif-r8a7791", "renesas,scif";
607 reg = <0 0xe6e58000 0 64>;
608 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
609 clocks = <&mstp7_clks R8A7791_CLK_SCIF2>;
610 clock-names = "sci_ick";
611 status = "disabled";
612 };
613
614 scif3: serial@e6ea8000 {
615 compatible = "renesas,scif-r8a7791", "renesas,scif";
616 reg = <0 0xe6ea8000 0 64>;
617 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
618 clocks = <&mstp7_clks R8A7791_CLK_SCIF3>;
619 clock-names = "sci_ick";
620 status = "disabled";
621 };
622
623 scif4: serial@e6ee0000 {
624 compatible = "renesas,scif-r8a7791", "renesas,scif";
625 reg = <0 0xe6ee0000 0 64>;
626 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
627 clocks = <&mstp7_clks R8A7791_CLK_SCIF4>;
628 clock-names = "sci_ick";
629 status = "disabled";
630 };
631
632 scif5: serial@e6ee8000 {
633 compatible = "renesas,scif-r8a7791", "renesas,scif";
634 reg = <0 0xe6ee8000 0 64>;
635 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
636 clocks = <&mstp7_clks R8A7791_CLK_SCIF5>;
637 clock-names = "sci_ick";
638 status = "disabled";
639 };
640
641 hscif0: serial@e62c0000 {
642 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
643 reg = <0 0xe62c0000 0 96>;
644 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
645 clocks = <&mstp7_clks R8A7791_CLK_HSCIF0>;
646 clock-names = "sci_ick";
647 status = "disabled";
648 };
649
650 hscif1: serial@e62c8000 {
651 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
652 reg = <0 0xe62c8000 0 96>;
653 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
654 clocks = <&mstp7_clks R8A7791_CLK_HSCIF1>;
655 clock-names = "sci_ick";
656 status = "disabled";
657 };
658
659 hscif2: serial@e62d0000 {
660 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
661 reg = <0 0xe62d0000 0 96>;
662 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
663 clocks = <&mstp7_clks R8A7791_CLK_HSCIF2>;
664 clock-names = "sci_ick";
665 status = "disabled";
666 };
667
668 ether: ethernet@ee700000 {
669 compatible = "renesas,ether-r8a7791";
670 reg = <0 0xee700000 0 0x400>;
671 interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
672 clocks = <&mstp8_clks R8A7791_CLK_ETHER>;
673 phy-mode = "rmii";
674 #address-cells = <1>;
675 #size-cells = <0>;
676 status = "disabled";
677 };
678
679 sata0: sata@ee300000 {
680 compatible = "renesas,sata-r8a7791";
681 reg = <0 0xee300000 0 0x2000>;
682 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
683 clocks = <&mstp8_clks R8A7791_CLK_SATA0>;
684 status = "disabled";
685 };
686
687 sata1: sata@ee500000 {
688 compatible = "renesas,sata-r8a7791";
689 reg = <0 0xee500000 0 0x2000>;
690 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
691 clocks = <&mstp8_clks R8A7791_CLK_SATA1>;
692 status = "disabled";
693 };
694
695 hsusb: usb@e6590000 {
696 compatible = "renesas,usbhs-r8a7791";
697 reg = <0 0xe6590000 0 0x100>;
698 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
699 clocks = <&mstp7_clks R8A7791_CLK_HSUSB>;
700 renesas,buswait = <4>;
701 phys = <&usb0 1>;
702 phy-names = "usb";
703 status = "disabled";
704 };
705
706 usbphy: usb-phy@e6590100 {
707 compatible = "renesas,usb-phy-r8a7791";
708 reg = <0 0xe6590100 0 0x100>;
709 #address-cells = <1>;
710 #size-cells = <0>;
711 clocks = <&mstp7_clks R8A7791_CLK_HSUSB>;
712 clock-names = "usbhs";
713 status = "disabled";
714
715 usb0: usb-channel@0 {
716 reg = <0>;
717 #phy-cells = <1>;
718 };
719 usb2: usb-channel@2 {
720 reg = <2>;
721 #phy-cells = <1>;
722 };
723 };
724
725 vin0: video@e6ef0000 {
726 compatible = "renesas,vin-r8a7791";
727 clocks = <&mstp8_clks R8A7791_CLK_VIN0>;
728 reg = <0 0xe6ef0000 0 0x1000>;
729 interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>;
730 status = "disabled";
731 };
732
733 vin1: video@e6ef1000 {
734 compatible = "renesas,vin-r8a7791";
735 clocks = <&mstp8_clks R8A7791_CLK_VIN1>;
736 reg = <0 0xe6ef1000 0 0x1000>;
737 interrupts = <0 189 IRQ_TYPE_LEVEL_HIGH>;
738 status = "disabled";
739 };
740
741 vin2: video@e6ef2000 {
742 compatible = "renesas,vin-r8a7791";
743 clocks = <&mstp8_clks R8A7791_CLK_VIN2>;
744 reg = <0 0xe6ef2000 0 0x1000>;
745 interrupts = <0 190 IRQ_TYPE_LEVEL_HIGH>;
746 status = "disabled";
747 };
748
749 vsp1@fe928000 {
750 compatible = "renesas,vsp1";
751 reg = <0 0xfe928000 0 0x8000>;
752 interrupts = <0 267 IRQ_TYPE_LEVEL_HIGH>;
753 clocks = <&mstp1_clks R8A7791_CLK_VSP1_S>;
754
755 renesas,has-lut;
756 renesas,has-sru;
757 renesas,#rpf = <5>;
758 renesas,#uds = <3>;
759 renesas,#wpf = <4>;
760 };
761
762 vsp1@fe930000 {
763 compatible = "renesas,vsp1";
764 reg = <0 0xfe930000 0 0x8000>;
765 interrupts = <0 246 IRQ_TYPE_LEVEL_HIGH>;
766 clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU0>;
767
768 renesas,has-lif;
769 renesas,has-lut;
770 renesas,#rpf = <4>;
771 renesas,#uds = <1>;
772 renesas,#wpf = <4>;
773 };
774
775 vsp1@fe938000 {
776 compatible = "renesas,vsp1";
777 reg = <0 0xfe938000 0 0x8000>;
778 interrupts = <0 247 IRQ_TYPE_LEVEL_HIGH>;
779 clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU1>;
780
781 renesas,has-lif;
782 renesas,has-lut;
783 renesas,#rpf = <4>;
784 renesas,#uds = <1>;
785 renesas,#wpf = <4>;
786 };
787
788 du: display@feb00000 {
789 compatible = "renesas,du-r8a7791";
790 reg = <0 0xfeb00000 0 0x40000>,
791 <0 0xfeb90000 0 0x1c>;
792 reg-names = "du", "lvds.0";
793 interrupts = <0 256 IRQ_TYPE_LEVEL_HIGH>,
794 <0 268 IRQ_TYPE_LEVEL_HIGH>;
795 clocks = <&mstp7_clks R8A7791_CLK_DU0>,
796 <&mstp7_clks R8A7791_CLK_DU1>,
797 <&mstp7_clks R8A7791_CLK_LVDS0>;
798 clock-names = "du.0", "du.1", "lvds.0";
799 status = "disabled";
800
801 ports {
802 #address-cells = <1>;
803 #size-cells = <0>;
804
805 port@0 {
806 reg = <0>;
807 du_out_rgb: endpoint {
808 };
809 };
810 port@1 {
811 reg = <1>;
812 du_out_lvds0: endpoint {
813 };
814 };
815 };
816 };
817
818 can0: can@e6e80000 {
819 compatible = "renesas,can-r8a7791";
820 reg = <0 0xe6e80000 0 0x1000>;
821 interrupts = <0 186 IRQ_TYPE_LEVEL_HIGH>;
822 clocks = <&mstp9_clks R8A7791_CLK_RCAN0>,
823 <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>;
824 clock-names = "clkp1", "clkp2", "can_clk";
825 status = "disabled";
826 };
827
828 can1: can@e6e88000 {
829 compatible = "renesas,can-r8a7791";
830 reg = <0 0xe6e88000 0 0x1000>;
831 interrupts = <0 187 IRQ_TYPE_LEVEL_HIGH>;
832 clocks = <&mstp9_clks R8A7791_CLK_RCAN1>,
833 <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>;
834 clock-names = "clkp1", "clkp2", "can_clk";
835 status = "disabled";
836 };
837
838 clocks {
839 #address-cells = <2>;
840 #size-cells = <2>;
841 ranges;
842
843 /* External root clock */
844 extal_clk: extal_clk {
845 compatible = "fixed-clock";
846 #clock-cells = <0>;
847 /* This value must be overriden by the board. */
848 clock-frequency = <0>;
849 clock-output-names = "extal";
850 };
851
852 /*
853 * The external audio clocks are configured as 0 Hz fixed frequency clocks by
854 * default. Boards that provide audio clocks should override them.
855 */
856 audio_clk_a: audio_clk_a {
857 compatible = "fixed-clock";
858 #clock-cells = <0>;
859 clock-frequency = <0>;
860 clock-output-names = "audio_clk_a";
861 };
862 audio_clk_b: audio_clk_b {
863 compatible = "fixed-clock";
864 #clock-cells = <0>;
865 clock-frequency = <0>;
866 clock-output-names = "audio_clk_b";
867 };
868 audio_clk_c: audio_clk_c {
869 compatible = "fixed-clock";
870 #clock-cells = <0>;
871 clock-frequency = <0>;
872 clock-output-names = "audio_clk_c";
873 };
874
875 /* External PCIe clock - can be overridden by the board */
876 pcie_bus_clk: pcie_bus_clk {
877 compatible = "fixed-clock";
878 #clock-cells = <0>;
879 clock-frequency = <100000000>;
880 clock-output-names = "pcie_bus";
881 status = "disabled";
882 };
883
884 /* External USB clock - can be overridden by the board */
885 usb_extal_clk: usb_extal_clk {
886 compatible = "fixed-clock";
887 #clock-cells = <0>;
888 clock-frequency = <48000000>;
889 clock-output-names = "usb_extal";
890 };
891
892 /* External CAN clock */
893 can_clk: can_clk {
894 compatible = "fixed-clock";
895 #clock-cells = <0>;
896 /* This value must be overridden by the board. */
897 clock-frequency = <0>;
898 clock-output-names = "can_clk";
899 status = "disabled";
900 };
901
902 /* Special CPG clocks */
903 cpg_clocks: cpg_clocks@e6150000 {
904 compatible = "renesas,r8a7791-cpg-clocks",
905 "renesas,rcar-gen2-cpg-clocks";
906 reg = <0 0xe6150000 0 0x1000>;
907 clocks = <&extal_clk &usb_extal_clk>;
908 #clock-cells = <1>;
909 clock-output-names = "main", "pll0", "pll1", "pll3",
910 "lb", "qspi", "sdh", "sd0", "z",
911 "rcan", "adsp";
912 };
913
914 /* Variable factor clocks */
915 sd2_clk: sd2_clk@e6150078 {
916 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
917 reg = <0 0xe6150078 0 4>;
918 clocks = <&pll1_div2_clk>;
919 #clock-cells = <0>;
920 clock-output-names = "sd2";
921 };
922 sd3_clk: sd3_clk@e615026c {
923 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
924 reg = <0 0xe615026c 0 4>;
925 clocks = <&pll1_div2_clk>;
926 #clock-cells = <0>;
927 clock-output-names = "sd3";
928 };
929 mmc0_clk: mmc0_clk@e6150240 {
930 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
931 reg = <0 0xe6150240 0 4>;
932 clocks = <&pll1_div2_clk>;
933 #clock-cells = <0>;
934 clock-output-names = "mmc0";
935 };
936 ssp_clk: ssp_clk@e6150248 {
937 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
938 reg = <0 0xe6150248 0 4>;
939 clocks = <&pll1_div2_clk>;
940 #clock-cells = <0>;
941 clock-output-names = "ssp";
942 };
943 ssprs_clk: ssprs_clk@e615024c {
944 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
945 reg = <0 0xe615024c 0 4>;
946 clocks = <&pll1_div2_clk>;
947 #clock-cells = <0>;
948 clock-output-names = "ssprs";
949 };
950
951 /* Fixed factor clocks */
952 pll1_div2_clk: pll1_div2_clk {
953 compatible = "fixed-factor-clock";
954 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
955 #clock-cells = <0>;
956 clock-div = <2>;
957 clock-mult = <1>;
958 clock-output-names = "pll1_div2";
959 };
960 zg_clk: zg_clk {
961 compatible = "fixed-factor-clock";
962 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
963 #clock-cells = <0>;
964 clock-div = <3>;
965 clock-mult = <1>;
966 clock-output-names = "zg";
967 };
968 zx_clk: zx_clk {
969 compatible = "fixed-factor-clock";
970 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
971 #clock-cells = <0>;
972 clock-div = <3>;
973 clock-mult = <1>;
974 clock-output-names = "zx";
975 };
976 zs_clk: zs_clk {
977 compatible = "fixed-factor-clock";
978 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
979 #clock-cells = <0>;
980 clock-div = <6>;
981 clock-mult = <1>;
982 clock-output-names = "zs";
983 };
984 hp_clk: hp_clk {
985 compatible = "fixed-factor-clock";
986 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
987 #clock-cells = <0>;
988 clock-div = <12>;
989 clock-mult = <1>;
990 clock-output-names = "hp";
991 };
992 i_clk: i_clk {
993 compatible = "fixed-factor-clock";
994 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
995 #clock-cells = <0>;
996 clock-div = <2>;
997 clock-mult = <1>;
998 clock-output-names = "i";
999 };
1000 b_clk: b_clk {
1001 compatible = "fixed-factor-clock";
1002 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1003 #clock-cells = <0>;
1004 clock-div = <12>;
1005 clock-mult = <1>;
1006 clock-output-names = "b";
1007 };
1008 p_clk: p_clk {
1009 compatible = "fixed-factor-clock";
1010 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1011 #clock-cells = <0>;
1012 clock-div = <24>;
1013 clock-mult = <1>;
1014 clock-output-names = "p";
1015 };
1016 cl_clk: cl_clk {
1017 compatible = "fixed-factor-clock";
1018 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1019 #clock-cells = <0>;
1020 clock-div = <48>;
1021 clock-mult = <1>;
1022 clock-output-names = "cl";
1023 };
1024 m2_clk: m2_clk {
1025 compatible = "fixed-factor-clock";
1026 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1027 #clock-cells = <0>;
1028 clock-div = <8>;
1029 clock-mult = <1>;
1030 clock-output-names = "m2";
1031 };
1032 imp_clk: imp_clk {
1033 compatible = "fixed-factor-clock";
1034 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1035 #clock-cells = <0>;
1036 clock-div = <4>;
1037 clock-mult = <1>;
1038 clock-output-names = "imp";
1039 };
1040 rclk_clk: rclk_clk {
1041 compatible = "fixed-factor-clock";
1042 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1043 #clock-cells = <0>;
1044 clock-div = <(48 * 1024)>;
1045 clock-mult = <1>;
1046 clock-output-names = "rclk";
1047 };
1048 oscclk_clk: oscclk_clk {
1049 compatible = "fixed-factor-clock";
1050 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1051 #clock-cells = <0>;
1052 clock-div = <(12 * 1024)>;
1053 clock-mult = <1>;
1054 clock-output-names = "oscclk";
1055 };
1056 zb3_clk: zb3_clk {
1057 compatible = "fixed-factor-clock";
1058 clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
1059 #clock-cells = <0>;
1060 clock-div = <4>;
1061 clock-mult = <1>;
1062 clock-output-names = "zb3";
1063 };
1064 zb3d2_clk: zb3d2_clk {
1065 compatible = "fixed-factor-clock";
1066 clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
1067 #clock-cells = <0>;
1068 clock-div = <8>;
1069 clock-mult = <1>;
1070 clock-output-names = "zb3d2";
1071 };
1072 ddr_clk: ddr_clk {
1073 compatible = "fixed-factor-clock";
1074 clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
1075 #clock-cells = <0>;
1076 clock-div = <8>;
1077 clock-mult = <1>;
1078 clock-output-names = "ddr";
1079 };
1080 mp_clk: mp_clk {
1081 compatible = "fixed-factor-clock";
1082 clocks = <&pll1_div2_clk>;
1083 #clock-cells = <0>;
1084 clock-div = <15>;
1085 clock-mult = <1>;
1086 clock-output-names = "mp";
1087 };
1088 cp_clk: cp_clk {
1089 compatible = "fixed-factor-clock";
1090 clocks = <&extal_clk>;
1091 #clock-cells = <0>;
1092 clock-div = <2>;
1093 clock-mult = <1>;
1094 clock-output-names = "cp";
1095 };
1096
1097 /* Gate clocks */
1098 mstp0_clks: mstp0_clks@e6150130 {
1099 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1100 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
1101 clocks = <&mp_clk>;
1102 #clock-cells = <1>;
1103 clock-indices = <R8A7791_CLK_MSIOF0>;
1104 clock-output-names = "msiof0";
1105 };
1106 mstp1_clks: mstp1_clks@e6150134 {
1107 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1108 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
1109 clocks = <&zs_clk>, <&zs_clk>, <&m2_clk>, <&zs_clk>, <&p_clk>,
1110 <&zg_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
1111 <&p_clk>, <&rclk_clk>, <&cp_clk>, <&zs_clk>, <&zs_clk>,
1112 <&zs_clk>;
1113 #clock-cells = <1>;
1114 clock-indices = <
1115 R8A7791_CLK_VCP0 R8A7791_CLK_VPC0 R8A7791_CLK_JPU
1116 R8A7791_CLK_SSP1 R8A7791_CLK_TMU1 R8A7791_CLK_3DG
1117 R8A7791_CLK_2DDMAC R8A7791_CLK_FDP1_1 R8A7791_CLK_FDP1_0
1118 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2 R8A7791_CLK_CMT0
1119 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1 R8A7791_CLK_VSP1_DU0
1120 R8A7791_CLK_VSP1_S
1121 >;
1122 clock-output-names =
1123 "vcp0", "vpc0", "jpu", "ssp1", "tmu1", "3dg",
1124 "2ddmac", "fdp1-1", "fdp1-0", "tmu3", "tmu2", "cmt0",
1125 "tmu0", "vsp1-du1", "vsp1-du0", "vsp1-sy";
1126 };
1127 mstp2_clks: mstp2_clks@e6150138 {
1128 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1129 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
1130 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
1131 <&mp_clk>, <&mp_clk>, <&mp_clk>,
1132 <&zs_clk>, <&zs_clk>;
1133 #clock-cells = <1>;
1134 clock-indices = <
1135 R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0
1136 R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1
1137 R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2
1138 R8A7791_CLK_SYS_DMAC1 R8A7791_CLK_SYS_DMAC0
1139 >;
1140 clock-output-names =
1141 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
1142 "scifb1", "msiof1", "scifb2",
1143 "sys-dmac1", "sys-dmac0";
1144 };
1145 mstp3_clks: mstp3_clks@e615013c {
1146 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1147 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
1148 clocks = <&cp_clk>, <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7791_CLK_SD0>,
1149 <&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>,
1150 <&hp_clk>, <&hp_clk>;
1151 #clock-cells = <1>;
1152 clock-indices = <
1153 R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0
1154 R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_PCIEC R8A7791_CLK_IIC1
1155 R8A7791_CLK_SSUSB R8A7791_CLK_CMT1
1156 R8A7791_CLK_USBDMAC0 R8A7791_CLK_USBDMAC1
1157 >;
1158 clock-output-names =
1159 "tpu0", "sdhi2", "sdhi1", "sdhi0",
1160 "mmcif0", "i2c7", "pciec", "i2c8", "ssusb", "cmt1",
1161 "usbdmac0", "usbdmac1";
1162 };
1163 mstp5_clks: mstp5_clks@e6150144 {
1164 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1165 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
1166 clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7791_CLK_ADSP>,
1167 <&extal_clk>, <&p_clk>;
1168 #clock-cells = <1>;
1169 clock-indices = <
1170 R8A7791_CLK_AUDIO_DMAC0 R8A7791_CLK_AUDIO_DMAC1
1171 R8A7791_CLK_ADSP_MOD R8A7791_CLK_THERMAL
1172 R8A7791_CLK_PWM
1173 >;
1174 clock-output-names = "audmac0", "audmac1", "adsp_mod",
1175 "thermal", "pwm";
1176 };
1177 mstp7_clks: mstp7_clks@e615014c {
1178 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1179 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
1180 clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
1181 <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1182 <&zx_clk>, <&zx_clk>, <&zx_clk>;
1183 #clock-cells = <1>;
1184 clock-indices = <
1185 R8A7791_CLK_EHCI R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5
1186 R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0
1187 R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1
1188 R8A7791_CLK_SCIF0 R8A7791_CLK_DU1 R8A7791_CLK_DU0
1189 R8A7791_CLK_LVDS0
1190 >;
1191 clock-output-names =
1192 "ehci", "hsusb", "hscif2", "scif5", "scif4", "hscif1", "hscif0",
1193 "scif3", "scif2", "scif1", "scif0", "du1", "du0", "lvds0";
1194 };
1195 mstp8_clks: mstp8_clks@e6150990 {
1196 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1197 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
1198 clocks = <&zx_clk>, <&hp_clk>, <&zg_clk>, <&zg_clk>,
1199 <&zg_clk>, <&p_clk>, <&zs_clk>, <&zs_clk>;
1200 #clock-cells = <1>;
1201 clock-indices = <
1202 R8A7791_CLK_IPMMU_SGX R8A7791_CLK_MLB
1203 R8A7791_CLK_VIN2 R8A7791_CLK_VIN1 R8A7791_CLK_VIN0
1204 R8A7791_CLK_ETHER R8A7791_CLK_SATA1 R8A7791_CLK_SATA0
1205 >;
1206 clock-output-names =
1207 "ipmmu_sgx", "mlb", "vin2", "vin1", "vin0", "ether",
1208 "sata1", "sata0";
1209 };
1210 mstp9_clks: mstp9_clks@e6150994 {
1211 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1212 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
1213 clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1214 <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1215 <&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>, <&hp_clk>,
1216 <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
1217 <&hp_clk>, <&hp_clk>;
1218 #clock-cells = <1>;
1219 clock-indices = <
1220 R8A7791_CLK_GPIO7 R8A7791_CLK_GPIO6 R8A7791_CLK_GPIO5 R8A7791_CLK_GPIO4
1221 R8A7791_CLK_GPIO3 R8A7791_CLK_GPIO2 R8A7791_CLK_GPIO1 R8A7791_CLK_GPIO0
1222 R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD R8A7791_CLK_I2C5
1223 R8A7791_CLK_IICDVFS R8A7791_CLK_I2C4 R8A7791_CLK_I2C3 R8A7791_CLK_I2C2
1224 R8A7791_CLK_I2C1 R8A7791_CLK_I2C0
1225 >;
1226 clock-output-names =
1227 "gpio7", "gpio6", "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0",
1228 "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c6", "i2c4", "i2c3", "i2c2",
1229 "i2c1", "i2c0";
1230 };
1231 mstp10_clks: mstp10_clks@e6150998 {
1232 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1233 reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
1234 clocks = <&p_clk>,
1235 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1236 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1237 <&p_clk>,
1238 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1239 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1240 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1241 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1242 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1243 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>;
1244
1245 #clock-cells = <1>;
1246 clock-indices = <
1247 R8A7791_CLK_SSI_ALL
1248 R8A7791_CLK_SSI9 R8A7791_CLK_SSI8 R8A7791_CLK_SSI7 R8A7791_CLK_SSI6 R8A7791_CLK_SSI5
1249 R8A7791_CLK_SSI4 R8A7791_CLK_SSI3 R8A7791_CLK_SSI2 R8A7791_CLK_SSI1 R8A7791_CLK_SSI0
1250 R8A7791_CLK_SCU_ALL
1251 R8A7791_CLK_SCU_DVC1 R8A7791_CLK_SCU_DVC0
1252 R8A7791_CLK_SCU_SRC9 R8A7791_CLK_SCU_SRC8 R8A7791_CLK_SCU_SRC7 R8A7791_CLK_SCU_SRC6 R8A7791_CLK_SCU_SRC5
1253 R8A7791_CLK_SCU_SRC4 R8A7791_CLK_SCU_SRC3 R8A7791_CLK_SCU_SRC2 R8A7791_CLK_SCU_SRC1 R8A7791_CLK_SCU_SRC0
1254 >;
1255 clock-output-names =
1256 "ssi-all",
1257 "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
1258 "ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
1259 "scu-all",
1260 "scu-dvc1", "scu-dvc0",
1261 "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
1262 "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
1263 };
1264 mstp11_clks: mstp11_clks@e615099c {
1265 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1266 reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
1267 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
1268 #clock-cells = <1>;
1269 clock-indices = <
1270 R8A7791_CLK_SCIFA3 R8A7791_CLK_SCIFA4 R8A7791_CLK_SCIFA5
1271 >;
1272 clock-output-names = "scifa3", "scifa4", "scifa5";
1273 };
1274 };
1275
1276 qspi: spi@e6b10000 {
1277 compatible = "renesas,qspi-r8a7791", "renesas,qspi";
1278 reg = <0 0xe6b10000 0 0x2c>;
1279 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
1280 clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>;
1281 dmas = <&dmac0 0x17>, <&dmac0 0x18>;
1282 dma-names = "tx", "rx";
1283 num-cs = <1>;
1284 #address-cells = <1>;
1285 #size-cells = <0>;
1286 status = "disabled";
1287 };
1288
1289 msiof0: spi@e6e20000 {
1290 compatible = "renesas,msiof-r8a7791";
1291 reg = <0 0xe6e20000 0 0x0064>, <0 0xe7e20000 0 0x0064>;
1292 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
1293 clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;
1294 dmas = <&dmac0 0x51>, <&dmac0 0x52>;
1295 dma-names = "tx", "rx";
1296 #address-cells = <1>;
1297 #size-cells = <0>;
1298 status = "disabled";
1299 };
1300
1301 msiof1: spi@e6e10000 {
1302 compatible = "renesas,msiof-r8a7791";
1303 reg = <0 0xe6e10000 0 0x0064>, <0 0xe7e10000 0 0x0064>;
1304 interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>;
1305 clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>;
1306 dmas = <&dmac0 0x55>, <&dmac0 0x56>;
1307 dma-names = "tx", "rx";
1308 #address-cells = <1>;
1309 #size-cells = <0>;
1310 status = "disabled";
1311 };
1312
1313 msiof2: spi@e6e00000 {
1314 compatible = "renesas,msiof-r8a7791";
1315 reg = <0 0xe6e00000 0 0x0064>, <0 0xe7e00000 0 0x0064>;
1316 interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
1317 clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>;
1318 dmas = <&dmac0 0x41>, <&dmac0 0x42>;
1319 dma-names = "tx", "rx";
1320 #address-cells = <1>;
1321 #size-cells = <0>;
1322 status = "disabled";
1323 };
1324
1325 xhci: usb@ee000000 {
1326 compatible = "renesas,xhci-r8a7791";
1327 reg = <0 0xee000000 0 0xc00>;
1328 interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>;
1329 clocks = <&mstp3_clks R8A7791_CLK_SSUSB>;
1330 phys = <&usb2 1>;
1331 phy-names = "usb";
1332 status = "disabled";
1333 };
1334
1335 pci0: pci@ee090000 {
1336 compatible = "renesas,pci-r8a7791";
1337 device_type = "pci";
1338 clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
1339 reg = <0 0xee090000 0 0xc00>,
1340 <0 0xee080000 0 0x1100>;
1341 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
1342 status = "disabled";
1343
1344 bus-range = <0 0>;
1345 #address-cells = <3>;
1346 #size-cells = <2>;
1347 #interrupt-cells = <1>;
1348 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
1349 interrupt-map-mask = <0xff00 0 0 0x7>;
1350 interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
1351 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
1352 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>;
1353
1354 usb@0,1 {
1355 reg = <0x800 0 0 0 0>;
1356 device_type = "pci";
1357 phys = <&usb0 0>;
1358 phy-names = "usb";
1359 };
1360
1361 usb@0,2 {
1362 reg = <0x1000 0 0 0 0>;
1363 device_type = "pci";
1364 phys = <&usb0 0>;
1365 phy-names = "usb";
1366 };
1367 };
1368
1369 pci1: pci@ee0d0000 {
1370 compatible = "renesas,pci-r8a7791";
1371 device_type = "pci";
1372 clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
1373 reg = <0 0xee0d0000 0 0xc00>,
1374 <0 0xee0c0000 0 0x1100>;
1375 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
1376 status = "disabled";
1377
1378 bus-range = <1 1>;
1379 #address-cells = <3>;
1380 #size-cells = <2>;
1381 #interrupt-cells = <1>;
1382 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
1383 interrupt-map-mask = <0xff00 0 0 0x7>;
1384 interrupt-map = <0x0000 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
1385 0x0800 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
1386 0x1000 0 0 2 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
1387
1388 usb@0,1 {
1389 reg = <0x800 0 0 0 0>;
1390 device_type = "pci";
1391 phys = <&usb2 0>;
1392 phy-names = "usb";
1393 };
1394
1395 usb@0,2 {
1396 reg = <0x1000 0 0 0 0>;
1397 device_type = "pci";
1398 phys = <&usb2 0>;
1399 phy-names = "usb";
1400 };
1401 };
1402
1403 pciec: pcie@fe000000 {
1404 compatible = "renesas,pcie-r8a7791";
1405 reg = <0 0xfe000000 0 0x80000>;
1406 #address-cells = <3>;
1407 #size-cells = <2>;
1408 bus-range = <0x00 0xff>;
1409 device_type = "pci";
1410 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
1411 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
1412 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
1413 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1414 /* Map all possible DDR as inbound ranges */
1415 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
1416 0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>;
1417 interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>,
1418 <0 117 IRQ_TYPE_LEVEL_HIGH>,
1419 <0 118 IRQ_TYPE_LEVEL_HIGH>;
1420 #interrupt-cells = <1>;
1421 interrupt-map-mask = <0 0 0 0>;
1422 interrupt-map = <0 0 0 0 &gic 0 116 IRQ_TYPE_LEVEL_HIGH>;
1423 clocks = <&mstp3_clks R8A7791_CLK_PCIEC>, <&pcie_bus_clk>;
1424 clock-names = "pcie", "pcie_bus";
1425 status = "disabled";
1426 };
1427
1428 ipmmu_sy0: mmu@e6280000 {
1429 compatible = "renesas,ipmmu-vmsa";
1430 reg = <0 0xe6280000 0 0x1000>;
1431 interrupts = <0 223 IRQ_TYPE_LEVEL_HIGH>,
1432 <0 224 IRQ_TYPE_LEVEL_HIGH>;
1433 #iommu-cells = <1>;
1434 status = "disabled";
1435 };
1436
1437 ipmmu_sy1: mmu@e6290000 {
1438 compatible = "renesas,ipmmu-vmsa";
1439 reg = <0 0xe6290000 0 0x1000>;
1440 interrupts = <0 225 IRQ_TYPE_LEVEL_HIGH>;
1441 #iommu-cells = <1>;
1442 status = "disabled";
1443 };
1444
1445 ipmmu_ds: mmu@e6740000 {
1446 compatible = "renesas,ipmmu-vmsa";
1447 reg = <0 0xe6740000 0 0x1000>;
1448 interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>,
1449 <0 199 IRQ_TYPE_LEVEL_HIGH>;
1450 #iommu-cells = <1>;
1451 status = "disabled";
1452 };
1453
1454 ipmmu_mp: mmu@ec680000 {
1455 compatible = "renesas,ipmmu-vmsa";
1456 reg = <0 0xec680000 0 0x1000>;
1457 interrupts = <0 226 IRQ_TYPE_LEVEL_HIGH>;
1458 #iommu-cells = <1>;
1459 status = "disabled";
1460 };
1461
1462 ipmmu_mx: mmu@fe951000 {
1463 compatible = "renesas,ipmmu-vmsa";
1464 reg = <0 0xfe951000 0 0x1000>;
1465 interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
1466 <0 221 IRQ_TYPE_LEVEL_HIGH>;
1467 #iommu-cells = <1>;
1468 status = "disabled";
1469 };
1470
1471 ipmmu_rt: mmu@ffc80000 {
1472 compatible = "renesas,ipmmu-vmsa";
1473 reg = <0 0xffc80000 0 0x1000>;
1474 interrupts = <0 307 IRQ_TYPE_LEVEL_HIGH>;
1475 #iommu-cells = <1>;
1476 status = "disabled";
1477 };
1478
1479 ipmmu_gp: mmu@e62a0000 {
1480 compatible = "renesas,ipmmu-vmsa";
1481 reg = <0 0xe62a0000 0 0x1000>;
1482 interrupts = <0 260 IRQ_TYPE_LEVEL_HIGH>,
1483 <0 261 IRQ_TYPE_LEVEL_HIGH>;
1484 #iommu-cells = <1>;
1485 status = "disabled";
1486 };
1487
1488 rcar_sound: rcar_sound@ec500000 {
1489 /*
1490 * #sound-dai-cells is required
1491 *
1492 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1493 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1494 */
1495 compatible = "renesas,rcar_sound-r8a7791", "renesas,rcar_sound-gen2";
1496 reg = <0 0xec500000 0 0x1000>, /* SCU */
1497 <0 0xec5a0000 0 0x100>, /* ADG */
1498 <0 0xec540000 0 0x1000>, /* SSIU */
1499 <0 0xec541000 0 0x1280>, /* SSI */
1500 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
1501 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1502
1503 clocks = <&mstp10_clks R8A7791_CLK_SSI_ALL>,
1504 <&mstp10_clks R8A7791_CLK_SSI9>, <&mstp10_clks R8A7791_CLK_SSI8>,
1505 <&mstp10_clks R8A7791_CLK_SSI7>, <&mstp10_clks R8A7791_CLK_SSI6>,
1506 <&mstp10_clks R8A7791_CLK_SSI5>, <&mstp10_clks R8A7791_CLK_SSI4>,
1507 <&mstp10_clks R8A7791_CLK_SSI3>, <&mstp10_clks R8A7791_CLK_SSI2>,
1508 <&mstp10_clks R8A7791_CLK_SSI1>, <&mstp10_clks R8A7791_CLK_SSI0>,
1509 <&mstp10_clks R8A7791_CLK_SCU_SRC9>, <&mstp10_clks R8A7791_CLK_SCU_SRC8>,
1510 <&mstp10_clks R8A7791_CLK_SCU_SRC7>, <&mstp10_clks R8A7791_CLK_SCU_SRC6>,
1511 <&mstp10_clks R8A7791_CLK_SCU_SRC5>, <&mstp10_clks R8A7791_CLK_SCU_SRC4>,
1512 <&mstp10_clks R8A7791_CLK_SCU_SRC3>, <&mstp10_clks R8A7791_CLK_SCU_SRC2>,
1513 <&mstp10_clks R8A7791_CLK_SCU_SRC1>, <&mstp10_clks R8A7791_CLK_SCU_SRC0>,
1514 <&mstp10_clks R8A7791_CLK_SCU_DVC0>, <&mstp10_clks R8A7791_CLK_SCU_DVC1>,
1515 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
1516 clock-names = "ssi-all",
1517 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
1518 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
1519 "src.9", "src.8", "src.7", "src.6", "src.5",
1520 "src.4", "src.3", "src.2", "src.1", "src.0",
1521 "dvc.0", "dvc.1",
1522 "clk_a", "clk_b", "clk_c", "clk_i";
1523
1524 status = "disabled";
1525
1526 rcar_sound,dvc {
1527 dvc0: dvc@0 {
1528 dmas = <&audma0 0xbc>;
1529 dma-names = "tx";
1530 };
1531 dvc1: dvc@1 {
1532 dmas = <&audma0 0xbe>;
1533 dma-names = "tx";
1534 };
1535 };
1536
1537 rcar_sound,src {
1538 src0: src@0 {
1539 interrupts = <0 352 IRQ_TYPE_LEVEL_HIGH>;
1540 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1541 dma-names = "rx", "tx";
1542 };
1543 src1: src@1 {
1544 interrupts = <0 353 IRQ_TYPE_LEVEL_HIGH>;
1545 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1546 dma-names = "rx", "tx";
1547 };
1548 src2: src@2 {
1549 interrupts = <0 354 IRQ_TYPE_LEVEL_HIGH>;
1550 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1551 dma-names = "rx", "tx";
1552 };
1553 src3: src@3 {
1554 interrupts = <0 355 IRQ_TYPE_LEVEL_HIGH>;
1555 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1556 dma-names = "rx", "tx";
1557 };
1558 src4: src@4 {
1559 interrupts = <0 356 IRQ_TYPE_LEVEL_HIGH>;
1560 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1561 dma-names = "rx", "tx";
1562 };
1563 src5: src@5 {
1564 interrupts = <0 357 IRQ_TYPE_LEVEL_HIGH>;
1565 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1566 dma-names = "rx", "tx";
1567 };
1568 src6: src@6 {
1569 interrupts = <0 358 IRQ_TYPE_LEVEL_HIGH>;
1570 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1571 dma-names = "rx", "tx";
1572 };
1573 src7: src@7 {
1574 interrupts = <0 359 IRQ_TYPE_LEVEL_HIGH>;
1575 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1576 dma-names = "rx", "tx";
1577 };
1578 src8: src@8 {
1579 interrupts = <0 360 IRQ_TYPE_LEVEL_HIGH>;
1580 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1581 dma-names = "rx", "tx";
1582 };
1583 src9: src@9 {
1584 interrupts = <0 361 IRQ_TYPE_LEVEL_HIGH>;
1585 dmas = <&audma0 0x97>, <&audma1 0xba>;
1586 dma-names = "rx", "tx";
1587 };
1588 };
1589
1590 rcar_sound,ssi {
1591 ssi0: ssi@0 {
1592 interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>;
1593 dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
1594 dma-names = "rx", "tx", "rxu", "txu";
1595 };
1596 ssi1: ssi@1 {
1597 interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>;
1598 dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
1599 dma-names = "rx", "tx", "rxu", "txu";
1600 };
1601 ssi2: ssi@2 {
1602 interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>;
1603 dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
1604 dma-names = "rx", "tx", "rxu", "txu";
1605 };
1606 ssi3: ssi@3 {
1607 interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>;
1608 dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
1609 dma-names = "rx", "tx", "rxu", "txu";
1610 };
1611 ssi4: ssi@4 {
1612 interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>;
1613 dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
1614 dma-names = "rx", "tx", "rxu", "txu";
1615 };
1616 ssi5: ssi@5 {
1617 interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>;
1618 dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
1619 dma-names = "rx", "tx", "rxu", "txu";
1620 };
1621 ssi6: ssi@6 {
1622 interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>;
1623 dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
1624 dma-names = "rx", "tx", "rxu", "txu";
1625 };
1626 ssi7: ssi@7 {
1627 interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>;
1628 dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
1629 dma-names = "rx", "tx", "rxu", "txu";
1630 };
1631 ssi8: ssi@8 {
1632 interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>;
1633 dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
1634 dma-names = "rx", "tx", "rxu", "txu";
1635 };
1636 ssi9: ssi@9 {
1637 interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>;
1638 dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
1639 dma-names = "rx", "tx", "rxu", "txu";
1640 };
1641 };
1642 };
1643 };
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