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Merge branch 'for-rc' of git://git.kernel.org/pub/scm/linux/kernel/git/rzhang/linux
[mirror_ubuntu-artful-kernel.git] / arch / arm / boot / dts / r8a7791.dtsi
1 /*
2 * Device Tree Source for the r8a7791 SoC
3 *
4 * Copyright (C) 2013-2015 Renesas Electronics Corporation
5 * Copyright (C) 2013-2014 Renesas Solutions Corp.
6 * Copyright (C) 2014 Cogent Embedded Inc.
7 *
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
11 */
12
13 #include <dt-bindings/clock/r8a7791-clock.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/interrupt-controller/irq.h>
16 #include <dt-bindings/power/r8a7791-sysc.h>
17
18 / {
19 compatible = "renesas,r8a7791";
20 interrupt-parent = <&gic>;
21 #address-cells = <2>;
22 #size-cells = <2>;
23
24 aliases {
25 i2c0 = &i2c0;
26 i2c1 = &i2c1;
27 i2c2 = &i2c2;
28 i2c3 = &i2c3;
29 i2c4 = &i2c4;
30 i2c5 = &i2c5;
31 i2c6 = &i2c6;
32 i2c7 = &i2c7;
33 i2c8 = &i2c8;
34 spi0 = &qspi;
35 spi1 = &msiof0;
36 spi2 = &msiof1;
37 spi3 = &msiof2;
38 vin0 = &vin0;
39 vin1 = &vin1;
40 vin2 = &vin2;
41 };
42
43 cpus {
44 #address-cells = <1>;
45 #size-cells = <0>;
46 enable-method = "renesas,apmu";
47
48 cpu0: cpu@0 {
49 device_type = "cpu";
50 compatible = "arm,cortex-a15";
51 reg = <0>;
52 clock-frequency = <1500000000>;
53 voltage-tolerance = <1>; /* 1% */
54 clocks = <&cpg_clocks R8A7791_CLK_Z>;
55 clock-latency = <300000>; /* 300 us */
56 power-domains = <&sysc R8A7791_PD_CA15_CPU0>;
57 next-level-cache = <&L2_CA15>;
58
59 /* kHz - uV - OPPs unknown yet */
60 operating-points = <1500000 1000000>,
61 <1312500 1000000>,
62 <1125000 1000000>,
63 < 937500 1000000>,
64 < 750000 1000000>,
65 < 375000 1000000>;
66 };
67
68 cpu1: cpu@1 {
69 device_type = "cpu";
70 compatible = "arm,cortex-a15";
71 reg = <1>;
72 clock-frequency = <1500000000>;
73 power-domains = <&sysc R8A7791_PD_CA15_CPU1>;
74 next-level-cache = <&L2_CA15>;
75 };
76
77 L2_CA15: cache-controller@0 {
78 compatible = "cache";
79 reg = <0>;
80 power-domains = <&sysc R8A7791_PD_CA15_SCU>;
81 cache-unified;
82 cache-level = <2>;
83 };
84 };
85
86 thermal-zones {
87 cpu_thermal: cpu-thermal {
88 polling-delay-passive = <0>;
89 polling-delay = <0>;
90
91 thermal-sensors = <&thermal>;
92
93 trips {
94 cpu-crit {
95 temperature = <115000>;
96 hysteresis = <0>;
97 type = "critical";
98 };
99 };
100 cooling-maps {
101 };
102 };
103 };
104
105 apmu@e6152000 {
106 compatible = "renesas,r8a7791-apmu", "renesas,apmu";
107 reg = <0 0xe6152000 0 0x188>;
108 cpus = <&cpu0 &cpu1>;
109 };
110
111 gic: interrupt-controller@f1001000 {
112 compatible = "arm,gic-400";
113 #interrupt-cells = <3>;
114 #address-cells = <0>;
115 interrupt-controller;
116 reg = <0 0xf1001000 0 0x1000>,
117 <0 0xf1002000 0 0x1000>,
118 <0 0xf1004000 0 0x2000>,
119 <0 0xf1006000 0 0x2000>;
120 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
121 };
122
123 gpio0: gpio@e6050000 {
124 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
125 reg = <0 0xe6050000 0 0x50>;
126 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
127 #gpio-cells = <2>;
128 gpio-controller;
129 gpio-ranges = <&pfc 0 0 32>;
130 #interrupt-cells = <2>;
131 interrupt-controller;
132 clocks = <&mstp9_clks R8A7791_CLK_GPIO0>;
133 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
134 };
135
136 gpio1: gpio@e6051000 {
137 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
138 reg = <0 0xe6051000 0 0x50>;
139 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
140 #gpio-cells = <2>;
141 gpio-controller;
142 gpio-ranges = <&pfc 0 32 26>;
143 #interrupt-cells = <2>;
144 interrupt-controller;
145 clocks = <&mstp9_clks R8A7791_CLK_GPIO1>;
146 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
147 };
148
149 gpio2: gpio@e6052000 {
150 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
151 reg = <0 0xe6052000 0 0x50>;
152 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
153 #gpio-cells = <2>;
154 gpio-controller;
155 gpio-ranges = <&pfc 0 64 32>;
156 #interrupt-cells = <2>;
157 interrupt-controller;
158 clocks = <&mstp9_clks R8A7791_CLK_GPIO2>;
159 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
160 };
161
162 gpio3: gpio@e6053000 {
163 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
164 reg = <0 0xe6053000 0 0x50>;
165 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
166 #gpio-cells = <2>;
167 gpio-controller;
168 gpio-ranges = <&pfc 0 96 32>;
169 #interrupt-cells = <2>;
170 interrupt-controller;
171 clocks = <&mstp9_clks R8A7791_CLK_GPIO3>;
172 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
173 };
174
175 gpio4: gpio@e6054000 {
176 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
177 reg = <0 0xe6054000 0 0x50>;
178 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
179 #gpio-cells = <2>;
180 gpio-controller;
181 gpio-ranges = <&pfc 0 128 32>;
182 #interrupt-cells = <2>;
183 interrupt-controller;
184 clocks = <&mstp9_clks R8A7791_CLK_GPIO4>;
185 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
186 };
187
188 gpio5: gpio@e6055000 {
189 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
190 reg = <0 0xe6055000 0 0x50>;
191 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
192 #gpio-cells = <2>;
193 gpio-controller;
194 gpio-ranges = <&pfc 0 160 32>;
195 #interrupt-cells = <2>;
196 interrupt-controller;
197 clocks = <&mstp9_clks R8A7791_CLK_GPIO5>;
198 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
199 };
200
201 gpio6: gpio@e6055400 {
202 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
203 reg = <0 0xe6055400 0 0x50>;
204 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
205 #gpio-cells = <2>;
206 gpio-controller;
207 gpio-ranges = <&pfc 0 192 32>;
208 #interrupt-cells = <2>;
209 interrupt-controller;
210 clocks = <&mstp9_clks R8A7791_CLK_GPIO6>;
211 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
212 };
213
214 gpio7: gpio@e6055800 {
215 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
216 reg = <0 0xe6055800 0 0x50>;
217 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
218 #gpio-cells = <2>;
219 gpio-controller;
220 gpio-ranges = <&pfc 0 224 26>;
221 #interrupt-cells = <2>;
222 interrupt-controller;
223 clocks = <&mstp9_clks R8A7791_CLK_GPIO7>;
224 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
225 };
226
227 thermal: thermal@e61f0000 {
228 compatible = "renesas,thermal-r8a7791",
229 "renesas,rcar-gen2-thermal",
230 "renesas,rcar-thermal";
231 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
232 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
233 clocks = <&mstp5_clks R8A7791_CLK_THERMAL>;
234 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
235 #thermal-sensor-cells = <0>;
236 };
237
238 timer {
239 compatible = "arm,armv7-timer";
240 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
241 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
242 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
243 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
244 };
245
246 cmt0: timer@ffca0000 {
247 compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2";
248 reg = <0 0xffca0000 0 0x1004>;
249 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
250 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
251 clocks = <&mstp1_clks R8A7791_CLK_CMT0>;
252 clock-names = "fck";
253 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
254
255 renesas,channels-mask = <0x60>;
256
257 status = "disabled";
258 };
259
260 cmt1: timer@e6130000 {
261 compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2";
262 reg = <0 0xe6130000 0 0x1004>;
263 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
264 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
265 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
266 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
267 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
268 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
269 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
270 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
271 clocks = <&mstp3_clks R8A7791_CLK_CMT1>;
272 clock-names = "fck";
273 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
274
275 renesas,channels-mask = <0xff>;
276
277 status = "disabled";
278 };
279
280 irqc0: interrupt-controller@e61c0000 {
281 compatible = "renesas,irqc-r8a7791", "renesas,irqc";
282 #interrupt-cells = <2>;
283 interrupt-controller;
284 reg = <0 0xe61c0000 0 0x200>;
285 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
286 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
287 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
288 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
289 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
290 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
291 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
292 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
293 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
294 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
295 clocks = <&mstp4_clks R8A7791_CLK_IRQC>;
296 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
297 };
298
299 dmac0: dma-controller@e6700000 {
300 compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac";
301 reg = <0 0xe6700000 0 0x20000>;
302 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
303 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
304 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
305 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
306 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
307 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
308 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
309 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
310 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
311 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
312 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
313 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
314 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
315 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
316 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
317 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
318 interrupt-names = "error",
319 "ch0", "ch1", "ch2", "ch3",
320 "ch4", "ch5", "ch6", "ch7",
321 "ch8", "ch9", "ch10", "ch11",
322 "ch12", "ch13", "ch14";
323 clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC0>;
324 clock-names = "fck";
325 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
326 #dma-cells = <1>;
327 dma-channels = <15>;
328 };
329
330 dmac1: dma-controller@e6720000 {
331 compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac";
332 reg = <0 0xe6720000 0 0x20000>;
333 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
334 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
335 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
336 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
337 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
338 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
339 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
340 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
341 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
342 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
343 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
344 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
345 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
346 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
347 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
348 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
349 interrupt-names = "error",
350 "ch0", "ch1", "ch2", "ch3",
351 "ch4", "ch5", "ch6", "ch7",
352 "ch8", "ch9", "ch10", "ch11",
353 "ch12", "ch13", "ch14";
354 clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC1>;
355 clock-names = "fck";
356 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
357 #dma-cells = <1>;
358 dma-channels = <15>;
359 };
360
361 audma0: dma-controller@ec700000 {
362 compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac";
363 reg = <0 0xec700000 0 0x10000>;
364 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
365 GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
366 GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
367 GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
368 GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
369 GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
370 GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
371 GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
372 GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
373 GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
374 GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
375 GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
376 GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
377 GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
378 interrupt-names = "error",
379 "ch0", "ch1", "ch2", "ch3",
380 "ch4", "ch5", "ch6", "ch7",
381 "ch8", "ch9", "ch10", "ch11",
382 "ch12";
383 clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC0>;
384 clock-names = "fck";
385 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
386 #dma-cells = <1>;
387 dma-channels = <13>;
388 };
389
390 audma1: dma-controller@ec720000 {
391 compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac";
392 reg = <0 0xec720000 0 0x10000>;
393 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
394 GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
395 GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
396 GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
397 GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
398 GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
399 GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
400 GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
401 GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
402 GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
403 GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
404 GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
405 GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
406 GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
407 interrupt-names = "error",
408 "ch0", "ch1", "ch2", "ch3",
409 "ch4", "ch5", "ch6", "ch7",
410 "ch8", "ch9", "ch10", "ch11",
411 "ch12";
412 clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC1>;
413 clock-names = "fck";
414 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
415 #dma-cells = <1>;
416 dma-channels = <13>;
417 };
418
419 usb_dmac0: dma-controller@e65a0000 {
420 compatible = "renesas,r8a7791-usb-dmac", "renesas,usb-dmac";
421 reg = <0 0xe65a0000 0 0x100>;
422 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
423 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
424 interrupt-names = "ch0", "ch1";
425 clocks = <&mstp3_clks R8A7791_CLK_USBDMAC0>;
426 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
427 #dma-cells = <1>;
428 dma-channels = <2>;
429 };
430
431 usb_dmac1: dma-controller@e65b0000 {
432 compatible = "renesas,r8a7791-usb-dmac", "renesas,usb-dmac";
433 reg = <0 0xe65b0000 0 0x100>;
434 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
435 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
436 interrupt-names = "ch0", "ch1";
437 clocks = <&mstp3_clks R8A7791_CLK_USBDMAC1>;
438 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
439 #dma-cells = <1>;
440 dma-channels = <2>;
441 };
442
443 /* The memory map in the User's Manual maps the cores to bus numbers */
444 i2c0: i2c@e6508000 {
445 #address-cells = <1>;
446 #size-cells = <0>;
447 compatible = "renesas,i2c-r8a7791";
448 reg = <0 0xe6508000 0 0x40>;
449 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
450 clocks = <&mstp9_clks R8A7791_CLK_I2C0>;
451 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
452 i2c-scl-internal-delay-ns = <6>;
453 status = "disabled";
454 };
455
456 i2c1: i2c@e6518000 {
457 #address-cells = <1>;
458 #size-cells = <0>;
459 compatible = "renesas,i2c-r8a7791";
460 reg = <0 0xe6518000 0 0x40>;
461 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
462 clocks = <&mstp9_clks R8A7791_CLK_I2C1>;
463 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
464 i2c-scl-internal-delay-ns = <6>;
465 status = "disabled";
466 };
467
468 i2c2: i2c@e6530000 {
469 #address-cells = <1>;
470 #size-cells = <0>;
471 compatible = "renesas,i2c-r8a7791";
472 reg = <0 0xe6530000 0 0x40>;
473 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
474 clocks = <&mstp9_clks R8A7791_CLK_I2C2>;
475 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
476 i2c-scl-internal-delay-ns = <6>;
477 status = "disabled";
478 };
479
480 i2c3: i2c@e6540000 {
481 #address-cells = <1>;
482 #size-cells = <0>;
483 compatible = "renesas,i2c-r8a7791";
484 reg = <0 0xe6540000 0 0x40>;
485 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
486 clocks = <&mstp9_clks R8A7791_CLK_I2C3>;
487 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
488 i2c-scl-internal-delay-ns = <6>;
489 status = "disabled";
490 };
491
492 i2c4: i2c@e6520000 {
493 #address-cells = <1>;
494 #size-cells = <0>;
495 compatible = "renesas,i2c-r8a7791";
496 reg = <0 0xe6520000 0 0x40>;
497 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
498 clocks = <&mstp9_clks R8A7791_CLK_I2C4>;
499 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
500 i2c-scl-internal-delay-ns = <6>;
501 status = "disabled";
502 };
503
504 i2c5: i2c@e6528000 {
505 /* doesn't need pinmux */
506 #address-cells = <1>;
507 #size-cells = <0>;
508 compatible = "renesas,i2c-r8a7791";
509 reg = <0 0xe6528000 0 0x40>;
510 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
511 clocks = <&mstp9_clks R8A7791_CLK_I2C5>;
512 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
513 i2c-scl-internal-delay-ns = <110>;
514 status = "disabled";
515 };
516
517 i2c6: i2c@e60b0000 {
518 /* doesn't need pinmux */
519 #address-cells = <1>;
520 #size-cells = <0>;
521 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
522 reg = <0 0xe60b0000 0 0x425>;
523 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
524 clocks = <&mstp9_clks R8A7791_CLK_IICDVFS>;
525 dmas = <&dmac0 0x77>, <&dmac0 0x78>,
526 <&dmac1 0x77>, <&dmac1 0x78>;
527 dma-names = "tx", "rx", "tx", "rx";
528 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
529 status = "disabled";
530 };
531
532 i2c7: i2c@e6500000 {
533 #address-cells = <1>;
534 #size-cells = <0>;
535 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
536 reg = <0 0xe6500000 0 0x425>;
537 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
538 clocks = <&mstp3_clks R8A7791_CLK_IIC0>;
539 dmas = <&dmac0 0x61>, <&dmac0 0x62>,
540 <&dmac1 0x61>, <&dmac1 0x62>;
541 dma-names = "tx", "rx", "tx", "rx";
542 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
543 status = "disabled";
544 };
545
546 i2c8: i2c@e6510000 {
547 #address-cells = <1>;
548 #size-cells = <0>;
549 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
550 reg = <0 0xe6510000 0 0x425>;
551 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
552 clocks = <&mstp3_clks R8A7791_CLK_IIC1>;
553 dmas = <&dmac0 0x65>, <&dmac0 0x66>,
554 <&dmac1 0x65>, <&dmac1 0x66>;
555 dma-names = "tx", "rx", "tx", "rx";
556 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
557 status = "disabled";
558 };
559
560 pfc: pfc@e6060000 {
561 compatible = "renesas,pfc-r8a7791";
562 reg = <0 0xe6060000 0 0x250>;
563 };
564
565 mmcif0: mmc@ee200000 {
566 compatible = "renesas,mmcif-r8a7791", "renesas,sh-mmcif";
567 reg = <0 0xee200000 0 0x80>;
568 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
569 clocks = <&mstp3_clks R8A7791_CLK_MMCIF0>;
570 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
571 <&dmac1 0xd1>, <&dmac1 0xd2>;
572 dma-names = "tx", "rx", "tx", "rx";
573 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
574 reg-io-width = <4>;
575 status = "disabled";
576 max-frequency = <97500000>;
577 };
578
579 sdhi0: sd@ee100000 {
580 compatible = "renesas,sdhi-r8a7791";
581 reg = <0 0xee100000 0 0x328>;
582 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
583 clocks = <&mstp3_clks R8A7791_CLK_SDHI0>;
584 dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
585 <&dmac1 0xcd>, <&dmac1 0xce>;
586 dma-names = "tx", "rx", "tx", "rx";
587 max-frequency = <195000000>;
588 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
589 status = "disabled";
590 };
591
592 sdhi1: sd@ee140000 {
593 compatible = "renesas,sdhi-r8a7791";
594 reg = <0 0xee140000 0 0x100>;
595 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
596 clocks = <&mstp3_clks R8A7791_CLK_SDHI1>;
597 dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
598 <&dmac1 0xc1>, <&dmac1 0xc2>;
599 dma-names = "tx", "rx", "tx", "rx";
600 max-frequency = <97500000>;
601 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
602 status = "disabled";
603 };
604
605 sdhi2: sd@ee160000 {
606 compatible = "renesas,sdhi-r8a7791";
607 reg = <0 0xee160000 0 0x100>;
608 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
609 clocks = <&mstp3_clks R8A7791_CLK_SDHI2>;
610 dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
611 <&dmac1 0xd3>, <&dmac1 0xd4>;
612 dma-names = "tx", "rx", "tx", "rx";
613 max-frequency = <97500000>;
614 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
615 status = "disabled";
616 };
617
618 scifa0: serial@e6c40000 {
619 compatible = "renesas,scifa-r8a7791",
620 "renesas,rcar-gen2-scifa", "renesas,scifa";
621 reg = <0 0xe6c40000 0 64>;
622 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
623 clocks = <&mstp2_clks R8A7791_CLK_SCIFA0>;
624 clock-names = "fck";
625 dmas = <&dmac0 0x21>, <&dmac0 0x22>,
626 <&dmac1 0x21>, <&dmac1 0x22>;
627 dma-names = "tx", "rx", "tx", "rx";
628 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
629 status = "disabled";
630 };
631
632 scifa1: serial@e6c50000 {
633 compatible = "renesas,scifa-r8a7791",
634 "renesas,rcar-gen2-scifa", "renesas,scifa";
635 reg = <0 0xe6c50000 0 64>;
636 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
637 clocks = <&mstp2_clks R8A7791_CLK_SCIFA1>;
638 clock-names = "fck";
639 dmas = <&dmac0 0x25>, <&dmac0 0x26>,
640 <&dmac1 0x25>, <&dmac1 0x26>;
641 dma-names = "tx", "rx", "tx", "rx";
642 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
643 status = "disabled";
644 };
645
646 scifa2: serial@e6c60000 {
647 compatible = "renesas,scifa-r8a7791",
648 "renesas,rcar-gen2-scifa", "renesas,scifa";
649 reg = <0 0xe6c60000 0 64>;
650 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
651 clocks = <&mstp2_clks R8A7791_CLK_SCIFA2>;
652 clock-names = "fck";
653 dmas = <&dmac0 0x27>, <&dmac0 0x28>,
654 <&dmac1 0x27>, <&dmac1 0x28>;
655 dma-names = "tx", "rx", "tx", "rx";
656 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
657 status = "disabled";
658 };
659
660 scifa3: serial@e6c70000 {
661 compatible = "renesas,scifa-r8a7791",
662 "renesas,rcar-gen2-scifa", "renesas,scifa";
663 reg = <0 0xe6c70000 0 64>;
664 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
665 clocks = <&mstp11_clks R8A7791_CLK_SCIFA3>;
666 clock-names = "fck";
667 dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
668 <&dmac1 0x1b>, <&dmac1 0x1c>;
669 dma-names = "tx", "rx", "tx", "rx";
670 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
671 status = "disabled";
672 };
673
674 scifa4: serial@e6c78000 {
675 compatible = "renesas,scifa-r8a7791",
676 "renesas,rcar-gen2-scifa", "renesas,scifa";
677 reg = <0 0xe6c78000 0 64>;
678 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
679 clocks = <&mstp11_clks R8A7791_CLK_SCIFA4>;
680 clock-names = "fck";
681 dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
682 <&dmac1 0x1f>, <&dmac1 0x20>;
683 dma-names = "tx", "rx", "tx", "rx";
684 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
685 status = "disabled";
686 };
687
688 scifa5: serial@e6c80000 {
689 compatible = "renesas,scifa-r8a7791",
690 "renesas,rcar-gen2-scifa", "renesas,scifa";
691 reg = <0 0xe6c80000 0 64>;
692 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
693 clocks = <&mstp11_clks R8A7791_CLK_SCIFA5>;
694 clock-names = "fck";
695 dmas = <&dmac0 0x23>, <&dmac0 0x24>,
696 <&dmac1 0x23>, <&dmac1 0x24>;
697 dma-names = "tx", "rx", "tx", "rx";
698 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
699 status = "disabled";
700 };
701
702 scifb0: serial@e6c20000 {
703 compatible = "renesas,scifb-r8a7791",
704 "renesas,rcar-gen2-scifb", "renesas,scifb";
705 reg = <0 0xe6c20000 0 0x100>;
706 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
707 clocks = <&mstp2_clks R8A7791_CLK_SCIFB0>;
708 clock-names = "fck";
709 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
710 <&dmac1 0x3d>, <&dmac1 0x3e>;
711 dma-names = "tx", "rx", "tx", "rx";
712 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
713 status = "disabled";
714 };
715
716 scifb1: serial@e6c30000 {
717 compatible = "renesas,scifb-r8a7791",
718 "renesas,rcar-gen2-scifb", "renesas,scifb";
719 reg = <0 0xe6c30000 0 0x100>;
720 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
721 clocks = <&mstp2_clks R8A7791_CLK_SCIFB1>;
722 clock-names = "fck";
723 dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
724 <&dmac1 0x19>, <&dmac1 0x1a>;
725 dma-names = "tx", "rx", "tx", "rx";
726 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
727 status = "disabled";
728 };
729
730 scifb2: serial@e6ce0000 {
731 compatible = "renesas,scifb-r8a7791",
732 "renesas,rcar-gen2-scifb", "renesas,scifb";
733 reg = <0 0xe6ce0000 0 0x100>;
734 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
735 clocks = <&mstp2_clks R8A7791_CLK_SCIFB2>;
736 clock-names = "fck";
737 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
738 <&dmac1 0x1d>, <&dmac1 0x1e>;
739 dma-names = "tx", "rx", "tx", "rx";
740 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
741 status = "disabled";
742 };
743
744 scif0: serial@e6e60000 {
745 compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
746 "renesas,scif";
747 reg = <0 0xe6e60000 0 64>;
748 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
749 clocks = <&mstp7_clks R8A7791_CLK_SCIF0>, <&zs_clk>,
750 <&scif_clk>;
751 clock-names = "fck", "brg_int", "scif_clk";
752 dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
753 <&dmac1 0x29>, <&dmac1 0x2a>;
754 dma-names = "tx", "rx", "tx", "rx";
755 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
756 status = "disabled";
757 };
758
759 scif1: serial@e6e68000 {
760 compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
761 "renesas,scif";
762 reg = <0 0xe6e68000 0 64>;
763 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
764 clocks = <&mstp7_clks R8A7791_CLK_SCIF1>, <&zs_clk>,
765 <&scif_clk>;
766 clock-names = "fck", "brg_int", "scif_clk";
767 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
768 <&dmac1 0x2d>, <&dmac1 0x2e>;
769 dma-names = "tx", "rx", "tx", "rx";
770 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
771 status = "disabled";
772 };
773
774 scif2: serial@e6e58000 {
775 compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
776 "renesas,scif";
777 reg = <0 0xe6e58000 0 64>;
778 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
779 clocks = <&mstp7_clks R8A7791_CLK_SCIF2>, <&zs_clk>,
780 <&scif_clk>;
781 clock-names = "fck", "brg_int", "scif_clk";
782 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
783 <&dmac1 0x2b>, <&dmac1 0x2c>;
784 dma-names = "tx", "rx", "tx", "rx";
785 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
786 status = "disabled";
787 };
788
789 scif3: serial@e6ea8000 {
790 compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
791 "renesas,scif";
792 reg = <0 0xe6ea8000 0 64>;
793 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
794 clocks = <&mstp7_clks R8A7791_CLK_SCIF3>, <&zs_clk>,
795 <&scif_clk>;
796 clock-names = "fck", "brg_int", "scif_clk";
797 dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
798 <&dmac1 0x2f>, <&dmac1 0x30>;
799 dma-names = "tx", "rx", "tx", "rx";
800 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
801 status = "disabled";
802 };
803
804 scif4: serial@e6ee0000 {
805 compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
806 "renesas,scif";
807 reg = <0 0xe6ee0000 0 64>;
808 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
809 clocks = <&mstp7_clks R8A7791_CLK_SCIF4>, <&zs_clk>,
810 <&scif_clk>;
811 clock-names = "fck", "brg_int", "scif_clk";
812 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
813 <&dmac1 0xfb>, <&dmac1 0xfc>;
814 dma-names = "tx", "rx", "tx", "rx";
815 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
816 status = "disabled";
817 };
818
819 scif5: serial@e6ee8000 {
820 compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
821 "renesas,scif";
822 reg = <0 0xe6ee8000 0 64>;
823 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
824 clocks = <&mstp7_clks R8A7791_CLK_SCIF5>, <&zs_clk>,
825 <&scif_clk>;
826 clock-names = "fck", "brg_int", "scif_clk";
827 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
828 <&dmac1 0xfd>, <&dmac1 0xfe>;
829 dma-names = "tx", "rx", "tx", "rx";
830 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
831 status = "disabled";
832 };
833
834 hscif0: serial@e62c0000 {
835 compatible = "renesas,hscif-r8a7791",
836 "renesas,rcar-gen2-hscif", "renesas,hscif";
837 reg = <0 0xe62c0000 0 96>;
838 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
839 clocks = <&mstp7_clks R8A7791_CLK_HSCIF0>, <&zs_clk>,
840 <&scif_clk>;
841 clock-names = "fck", "brg_int", "scif_clk";
842 dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
843 <&dmac1 0x39>, <&dmac1 0x3a>;
844 dma-names = "tx", "rx", "tx", "rx";
845 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
846 status = "disabled";
847 };
848
849 hscif1: serial@e62c8000 {
850 compatible = "renesas,hscif-r8a7791",
851 "renesas,rcar-gen2-hscif", "renesas,hscif";
852 reg = <0 0xe62c8000 0 96>;
853 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
854 clocks = <&mstp7_clks R8A7791_CLK_HSCIF1>, <&zs_clk>,
855 <&scif_clk>;
856 clock-names = "fck", "brg_int", "scif_clk";
857 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
858 <&dmac1 0x4d>, <&dmac1 0x4e>;
859 dma-names = "tx", "rx", "tx", "rx";
860 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
861 status = "disabled";
862 };
863
864 hscif2: serial@e62d0000 {
865 compatible = "renesas,hscif-r8a7791",
866 "renesas,rcar-gen2-hscif", "renesas,hscif";
867 reg = <0 0xe62d0000 0 96>;
868 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
869 clocks = <&mstp7_clks R8A7791_CLK_HSCIF2>, <&zs_clk>,
870 <&scif_clk>;
871 clock-names = "fck", "brg_int", "scif_clk";
872 dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
873 <&dmac1 0x3b>, <&dmac1 0x3c>;
874 dma-names = "tx", "rx", "tx", "rx";
875 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
876 status = "disabled";
877 };
878
879 ether: ethernet@ee700000 {
880 compatible = "renesas,ether-r8a7791";
881 reg = <0 0xee700000 0 0x400>;
882 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
883 clocks = <&mstp8_clks R8A7791_CLK_ETHER>;
884 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
885 phy-mode = "rmii";
886 #address-cells = <1>;
887 #size-cells = <0>;
888 status = "disabled";
889 };
890
891 avb: ethernet@e6800000 {
892 compatible = "renesas,etheravb-r8a7791",
893 "renesas,etheravb-rcar-gen2";
894 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
895 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
896 clocks = <&mstp8_clks R8A7791_CLK_ETHERAVB>;
897 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
898 #address-cells = <1>;
899 #size-cells = <0>;
900 status = "disabled";
901 };
902
903 sata0: sata@ee300000 {
904 compatible = "renesas,sata-r8a7791";
905 reg = <0 0xee300000 0 0x2000>;
906 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
907 clocks = <&mstp8_clks R8A7791_CLK_SATA0>;
908 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
909 status = "disabled";
910 };
911
912 sata1: sata@ee500000 {
913 compatible = "renesas,sata-r8a7791";
914 reg = <0 0xee500000 0 0x2000>;
915 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
916 clocks = <&mstp8_clks R8A7791_CLK_SATA1>;
917 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
918 status = "disabled";
919 };
920
921 hsusb: usb@e6590000 {
922 compatible = "renesas,usbhs-r8a7791", "renesas,rcar-gen2-usbhs";
923 reg = <0 0xe6590000 0 0x100>;
924 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
925 clocks = <&mstp7_clks R8A7791_CLK_HSUSB>;
926 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
927 <&usb_dmac1 0>, <&usb_dmac1 1>;
928 dma-names = "ch0", "ch1", "ch2", "ch3";
929 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
930 renesas,buswait = <4>;
931 phys = <&usb0 1>;
932 phy-names = "usb";
933 status = "disabled";
934 };
935
936 usbphy: usb-phy@e6590100 {
937 compatible = "renesas,usb-phy-r8a7791";
938 reg = <0 0xe6590100 0 0x100>;
939 #address-cells = <1>;
940 #size-cells = <0>;
941 clocks = <&mstp7_clks R8A7791_CLK_HSUSB>;
942 clock-names = "usbhs";
943 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
944 status = "disabled";
945
946 usb0: usb-channel@0 {
947 reg = <0>;
948 #phy-cells = <1>;
949 };
950 usb2: usb-channel@2 {
951 reg = <2>;
952 #phy-cells = <1>;
953 };
954 };
955
956 vin0: video@e6ef0000 {
957 compatible = "renesas,vin-r8a7791";
958 reg = <0 0xe6ef0000 0 0x1000>;
959 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
960 clocks = <&mstp8_clks R8A7791_CLK_VIN0>;
961 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
962 status = "disabled";
963 };
964
965 vin1: video@e6ef1000 {
966 compatible = "renesas,vin-r8a7791";
967 reg = <0 0xe6ef1000 0 0x1000>;
968 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
969 clocks = <&mstp8_clks R8A7791_CLK_VIN1>;
970 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
971 status = "disabled";
972 };
973
974 vin2: video@e6ef2000 {
975 compatible = "renesas,vin-r8a7791";
976 reg = <0 0xe6ef2000 0 0x1000>;
977 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
978 clocks = <&mstp8_clks R8A7791_CLK_VIN2>;
979 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
980 status = "disabled";
981 };
982
983 vsp1@fe928000 {
984 compatible = "renesas,vsp1";
985 reg = <0 0xfe928000 0 0x8000>;
986 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
987 clocks = <&mstp1_clks R8A7791_CLK_VSP1_S>;
988 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
989 };
990
991 vsp1@fe930000 {
992 compatible = "renesas,vsp1";
993 reg = <0 0xfe930000 0 0x8000>;
994 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
995 clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU0>;
996 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
997 };
998
999 vsp1@fe938000 {
1000 compatible = "renesas,vsp1";
1001 reg = <0 0xfe938000 0 0x8000>;
1002 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
1003 clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU1>;
1004 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1005 };
1006
1007 du: display@feb00000 {
1008 compatible = "renesas,du-r8a7791";
1009 reg = <0 0xfeb00000 0 0x40000>,
1010 <0 0xfeb90000 0 0x1c>;
1011 reg-names = "du", "lvds.0";
1012 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
1013 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
1014 clocks = <&mstp7_clks R8A7791_CLK_DU0>,
1015 <&mstp7_clks R8A7791_CLK_DU1>,
1016 <&mstp7_clks R8A7791_CLK_LVDS0>;
1017 clock-names = "du.0", "du.1", "lvds.0";
1018 status = "disabled";
1019
1020 ports {
1021 #address-cells = <1>;
1022 #size-cells = <0>;
1023
1024 port@0 {
1025 reg = <0>;
1026 du_out_rgb: endpoint {
1027 };
1028 };
1029 port@1 {
1030 reg = <1>;
1031 du_out_lvds0: endpoint {
1032 };
1033 };
1034 };
1035 };
1036
1037 can0: can@e6e80000 {
1038 compatible = "renesas,can-r8a7791", "renesas,rcar-gen2-can";
1039 reg = <0 0xe6e80000 0 0x1000>;
1040 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
1041 clocks = <&mstp9_clks R8A7791_CLK_RCAN0>,
1042 <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>;
1043 clock-names = "clkp1", "clkp2", "can_clk";
1044 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1045 status = "disabled";
1046 };
1047
1048 can1: can@e6e88000 {
1049 compatible = "renesas,can-r8a7791", "renesas,rcar-gen2-can";
1050 reg = <0 0xe6e88000 0 0x1000>;
1051 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
1052 clocks = <&mstp9_clks R8A7791_CLK_RCAN1>,
1053 <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>;
1054 clock-names = "clkp1", "clkp2", "can_clk";
1055 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1056 status = "disabled";
1057 };
1058
1059 jpu: jpeg-codec@fe980000 {
1060 compatible = "renesas,jpu-r8a7791", "renesas,rcar-gen2-jpu";
1061 reg = <0 0xfe980000 0 0x10300>;
1062 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
1063 clocks = <&mstp1_clks R8A7791_CLK_JPU>;
1064 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1065 };
1066
1067 clocks {
1068 #address-cells = <2>;
1069 #size-cells = <2>;
1070 ranges;
1071
1072 /* External root clock */
1073 extal_clk: extal {
1074 compatible = "fixed-clock";
1075 #clock-cells = <0>;
1076 /* This value must be overriden by the board. */
1077 clock-frequency = <0>;
1078 };
1079
1080 /*
1081 * The external audio clocks are configured as 0 Hz fixed frequency clocks by
1082 * default. Boards that provide audio clocks should override them.
1083 */
1084 audio_clk_a: audio_clk_a {
1085 compatible = "fixed-clock";
1086 #clock-cells = <0>;
1087 clock-frequency = <0>;
1088 };
1089 audio_clk_b: audio_clk_b {
1090 compatible = "fixed-clock";
1091 #clock-cells = <0>;
1092 clock-frequency = <0>;
1093 };
1094 audio_clk_c: audio_clk_c {
1095 compatible = "fixed-clock";
1096 #clock-cells = <0>;
1097 clock-frequency = <0>;
1098 };
1099
1100 /* External PCIe clock - can be overridden by the board */
1101 pcie_bus_clk: pcie_bus {
1102 compatible = "fixed-clock";
1103 #clock-cells = <0>;
1104 clock-frequency = <0>;
1105 };
1106
1107 /* External SCIF clock */
1108 scif_clk: scif {
1109 compatible = "fixed-clock";
1110 #clock-cells = <0>;
1111 /* This value must be overridden by the board. */
1112 clock-frequency = <0>;
1113 };
1114
1115 /* External USB clock - can be overridden by the board */
1116 usb_extal_clk: usb_extal {
1117 compatible = "fixed-clock";
1118 #clock-cells = <0>;
1119 clock-frequency = <48000000>;
1120 };
1121
1122 /* External CAN clock */
1123 can_clk: can_clk {
1124 compatible = "fixed-clock";
1125 #clock-cells = <0>;
1126 /* This value must be overridden by the board. */
1127 clock-frequency = <0>;
1128 };
1129
1130 /* Special CPG clocks */
1131 cpg_clocks: cpg_clocks@e6150000 {
1132 compatible = "renesas,r8a7791-cpg-clocks",
1133 "renesas,rcar-gen2-cpg-clocks";
1134 reg = <0 0xe6150000 0 0x1000>;
1135 clocks = <&extal_clk &usb_extal_clk>;
1136 #clock-cells = <1>;
1137 clock-output-names = "main", "pll0", "pll1", "pll3",
1138 "lb", "qspi", "sdh", "sd0", "z",
1139 "rcan", "adsp";
1140 #power-domain-cells = <0>;
1141 };
1142
1143 /* Variable factor clocks */
1144 sd2_clk: sd2@e6150078 {
1145 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
1146 reg = <0 0xe6150078 0 4>;
1147 clocks = <&pll1_div2_clk>;
1148 #clock-cells = <0>;
1149 };
1150 sd3_clk: sd3@e615026c {
1151 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
1152 reg = <0 0xe615026c 0 4>;
1153 clocks = <&pll1_div2_clk>;
1154 #clock-cells = <0>;
1155 };
1156 mmc0_clk: mmc0@e6150240 {
1157 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
1158 reg = <0 0xe6150240 0 4>;
1159 clocks = <&pll1_div2_clk>;
1160 #clock-cells = <0>;
1161 };
1162 ssp_clk: ssp@e6150248 {
1163 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
1164 reg = <0 0xe6150248 0 4>;
1165 clocks = <&pll1_div2_clk>;
1166 #clock-cells = <0>;
1167 };
1168 ssprs_clk: ssprs@e615024c {
1169 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
1170 reg = <0 0xe615024c 0 4>;
1171 clocks = <&pll1_div2_clk>;
1172 #clock-cells = <0>;
1173 };
1174
1175 /* Fixed factor clocks */
1176 pll1_div2_clk: pll1_div2 {
1177 compatible = "fixed-factor-clock";
1178 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1179 #clock-cells = <0>;
1180 clock-div = <2>;
1181 clock-mult = <1>;
1182 };
1183 zg_clk: zg {
1184 compatible = "fixed-factor-clock";
1185 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1186 #clock-cells = <0>;
1187 clock-div = <3>;
1188 clock-mult = <1>;
1189 };
1190 zx_clk: zx {
1191 compatible = "fixed-factor-clock";
1192 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1193 #clock-cells = <0>;
1194 clock-div = <3>;
1195 clock-mult = <1>;
1196 };
1197 zs_clk: zs {
1198 compatible = "fixed-factor-clock";
1199 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1200 #clock-cells = <0>;
1201 clock-div = <6>;
1202 clock-mult = <1>;
1203 };
1204 hp_clk: hp {
1205 compatible = "fixed-factor-clock";
1206 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1207 #clock-cells = <0>;
1208 clock-div = <12>;
1209 clock-mult = <1>;
1210 };
1211 i_clk: i {
1212 compatible = "fixed-factor-clock";
1213 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1214 #clock-cells = <0>;
1215 clock-div = <2>;
1216 clock-mult = <1>;
1217 };
1218 b_clk: b {
1219 compatible = "fixed-factor-clock";
1220 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1221 #clock-cells = <0>;
1222 clock-div = <12>;
1223 clock-mult = <1>;
1224 };
1225 p_clk: p {
1226 compatible = "fixed-factor-clock";
1227 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1228 #clock-cells = <0>;
1229 clock-div = <24>;
1230 clock-mult = <1>;
1231 };
1232 cl_clk: cl {
1233 compatible = "fixed-factor-clock";
1234 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1235 #clock-cells = <0>;
1236 clock-div = <48>;
1237 clock-mult = <1>;
1238 };
1239 m2_clk: m2 {
1240 compatible = "fixed-factor-clock";
1241 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1242 #clock-cells = <0>;
1243 clock-div = <8>;
1244 clock-mult = <1>;
1245 };
1246 rclk_clk: rclk {
1247 compatible = "fixed-factor-clock";
1248 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1249 #clock-cells = <0>;
1250 clock-div = <(48 * 1024)>;
1251 clock-mult = <1>;
1252 };
1253 oscclk_clk: oscclk {
1254 compatible = "fixed-factor-clock";
1255 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1256 #clock-cells = <0>;
1257 clock-div = <(12 * 1024)>;
1258 clock-mult = <1>;
1259 };
1260 zb3_clk: zb3 {
1261 compatible = "fixed-factor-clock";
1262 clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
1263 #clock-cells = <0>;
1264 clock-div = <4>;
1265 clock-mult = <1>;
1266 };
1267 zb3d2_clk: zb3d2 {
1268 compatible = "fixed-factor-clock";
1269 clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
1270 #clock-cells = <0>;
1271 clock-div = <8>;
1272 clock-mult = <1>;
1273 };
1274 ddr_clk: ddr {
1275 compatible = "fixed-factor-clock";
1276 clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
1277 #clock-cells = <0>;
1278 clock-div = <8>;
1279 clock-mult = <1>;
1280 };
1281 mp_clk: mp {
1282 compatible = "fixed-factor-clock";
1283 clocks = <&pll1_div2_clk>;
1284 #clock-cells = <0>;
1285 clock-div = <15>;
1286 clock-mult = <1>;
1287 };
1288 cp_clk: cp {
1289 compatible = "fixed-factor-clock";
1290 clocks = <&extal_clk>;
1291 #clock-cells = <0>;
1292 clock-div = <2>;
1293 clock-mult = <1>;
1294 };
1295
1296 /* Gate clocks */
1297 mstp0_clks: mstp0_clks@e6150130 {
1298 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1299 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
1300 clocks = <&mp_clk>;
1301 #clock-cells = <1>;
1302 clock-indices = <R8A7791_CLK_MSIOF0>;
1303 clock-output-names = "msiof0";
1304 };
1305 mstp1_clks: mstp1_clks@e6150134 {
1306 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1307 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
1308 clocks = <&zs_clk>, <&zs_clk>, <&m2_clk>, <&zs_clk>, <&p_clk>,
1309 <&zg_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
1310 <&p_clk>, <&rclk_clk>, <&cp_clk>, <&zs_clk>, <&zs_clk>,
1311 <&zs_clk>;
1312 #clock-cells = <1>;
1313 clock-indices = <
1314 R8A7791_CLK_VCP0 R8A7791_CLK_VPC0 R8A7791_CLK_JPU
1315 R8A7791_CLK_SSP1 R8A7791_CLK_TMU1 R8A7791_CLK_3DG
1316 R8A7791_CLK_2DDMAC R8A7791_CLK_FDP1_1 R8A7791_CLK_FDP1_0
1317 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2 R8A7791_CLK_CMT0
1318 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1 R8A7791_CLK_VSP1_DU0
1319 R8A7791_CLK_VSP1_S
1320 >;
1321 clock-output-names =
1322 "vcp0", "vpc0", "jpu", "ssp1", "tmu1", "3dg",
1323 "2ddmac", "fdp1-1", "fdp1-0", "tmu3", "tmu2", "cmt0",
1324 "tmu0", "vsp1-du1", "vsp1-du0", "vsp1-sy";
1325 };
1326 mstp2_clks: mstp2_clks@e6150138 {
1327 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1328 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
1329 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
1330 <&mp_clk>, <&mp_clk>, <&mp_clk>,
1331 <&zs_clk>, <&zs_clk>;
1332 #clock-cells = <1>;
1333 clock-indices = <
1334 R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0
1335 R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1
1336 R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2
1337 R8A7791_CLK_SYS_DMAC1 R8A7791_CLK_SYS_DMAC0
1338 >;
1339 clock-output-names =
1340 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
1341 "scifb1", "msiof1", "scifb2",
1342 "sys-dmac1", "sys-dmac0";
1343 };
1344 mstp3_clks: mstp3_clks@e615013c {
1345 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1346 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
1347 clocks = <&cp_clk>, <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7791_CLK_SD0>,
1348 <&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>,
1349 <&hp_clk>, <&hp_clk>;
1350 #clock-cells = <1>;
1351 clock-indices = <
1352 R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0
1353 R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_PCIEC R8A7791_CLK_IIC1
1354 R8A7791_CLK_SSUSB R8A7791_CLK_CMT1
1355 R8A7791_CLK_USBDMAC0 R8A7791_CLK_USBDMAC1
1356 >;
1357 clock-output-names =
1358 "tpu0", "sdhi2", "sdhi1", "sdhi0",
1359 "mmcif0", "i2c7", "pciec", "i2c8", "ssusb", "cmt1",
1360 "usbdmac0", "usbdmac1";
1361 };
1362 mstp4_clks: mstp4_clks@e6150140 {
1363 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1364 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
1365 clocks = <&cp_clk>;
1366 #clock-cells = <1>;
1367 clock-indices = <R8A7791_CLK_IRQC>;
1368 clock-output-names = "irqc";
1369 };
1370 mstp5_clks: mstp5_clks@e6150144 {
1371 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1372 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
1373 clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7791_CLK_ADSP>,
1374 <&extal_clk>, <&p_clk>;
1375 #clock-cells = <1>;
1376 clock-indices = <
1377 R8A7791_CLK_AUDIO_DMAC0 R8A7791_CLK_AUDIO_DMAC1
1378 R8A7791_CLK_ADSP_MOD R8A7791_CLK_THERMAL
1379 R8A7791_CLK_PWM
1380 >;
1381 clock-output-names = "audmac0", "audmac1", "adsp_mod",
1382 "thermal", "pwm";
1383 };
1384 mstp7_clks: mstp7_clks@e615014c {
1385 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1386 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
1387 clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
1388 <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1389 <&zx_clk>, <&zx_clk>, <&zx_clk>;
1390 #clock-cells = <1>;
1391 clock-indices = <
1392 R8A7791_CLK_EHCI R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5
1393 R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0
1394 R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1
1395 R8A7791_CLK_SCIF0 R8A7791_CLK_DU1 R8A7791_CLK_DU0
1396 R8A7791_CLK_LVDS0
1397 >;
1398 clock-output-names =
1399 "ehci", "hsusb", "hscif2", "scif5", "scif4", "hscif1", "hscif0",
1400 "scif3", "scif2", "scif1", "scif0", "du1", "du0", "lvds0";
1401 };
1402 mstp8_clks: mstp8_clks@e6150990 {
1403 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1404 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
1405 clocks = <&zx_clk>, <&hp_clk>, <&zg_clk>, <&zg_clk>,
1406 <&zg_clk>, <&hp_clk>, <&p_clk>, <&zs_clk>,
1407 <&zs_clk>;
1408 #clock-cells = <1>;
1409 clock-indices = <
1410 R8A7791_CLK_IPMMU_SGX R8A7791_CLK_MLB
1411 R8A7791_CLK_VIN2 R8A7791_CLK_VIN1 R8A7791_CLK_VIN0
1412 R8A7791_CLK_ETHERAVB R8A7791_CLK_ETHER
1413 R8A7791_CLK_SATA1 R8A7791_CLK_SATA0
1414 >;
1415 clock-output-names =
1416 "ipmmu_sgx", "mlb", "vin2", "vin1", "vin0",
1417 "etheravb", "ether", "sata1", "sata0";
1418 };
1419 mstp9_clks: mstp9_clks@e6150994 {
1420 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1421 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
1422 clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1423 <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1424 <&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>, <&hp_clk>,
1425 <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
1426 <&hp_clk>, <&hp_clk>;
1427 #clock-cells = <1>;
1428 clock-indices = <
1429 R8A7791_CLK_GPIO7 R8A7791_CLK_GPIO6 R8A7791_CLK_GPIO5 R8A7791_CLK_GPIO4
1430 R8A7791_CLK_GPIO3 R8A7791_CLK_GPIO2 R8A7791_CLK_GPIO1 R8A7791_CLK_GPIO0
1431 R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD R8A7791_CLK_I2C5
1432 R8A7791_CLK_IICDVFS R8A7791_CLK_I2C4 R8A7791_CLK_I2C3 R8A7791_CLK_I2C2
1433 R8A7791_CLK_I2C1 R8A7791_CLK_I2C0
1434 >;
1435 clock-output-names =
1436 "gpio7", "gpio6", "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0",
1437 "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c6", "i2c4", "i2c3", "i2c2",
1438 "i2c1", "i2c0";
1439 };
1440 mstp10_clks: mstp10_clks@e6150998 {
1441 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1442 reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
1443 clocks = <&p_clk>,
1444 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1445 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1446 <&p_clk>,
1447 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1448 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1449 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1450 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1451 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1452 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1453 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>;
1454
1455 #clock-cells = <1>;
1456 clock-indices = <
1457 R8A7791_CLK_SSI_ALL
1458 R8A7791_CLK_SSI9 R8A7791_CLK_SSI8 R8A7791_CLK_SSI7 R8A7791_CLK_SSI6 R8A7791_CLK_SSI5
1459 R8A7791_CLK_SSI4 R8A7791_CLK_SSI3 R8A7791_CLK_SSI2 R8A7791_CLK_SSI1 R8A7791_CLK_SSI0
1460 R8A7791_CLK_SCU_ALL
1461 R8A7791_CLK_SCU_DVC1 R8A7791_CLK_SCU_DVC0
1462 R8A7791_CLK_SCU_CTU1_MIX1 R8A7791_CLK_SCU_CTU0_MIX0
1463 R8A7791_CLK_SCU_SRC9 R8A7791_CLK_SCU_SRC8 R8A7791_CLK_SCU_SRC7 R8A7791_CLK_SCU_SRC6 R8A7791_CLK_SCU_SRC5
1464 R8A7791_CLK_SCU_SRC4 R8A7791_CLK_SCU_SRC3 R8A7791_CLK_SCU_SRC2 R8A7791_CLK_SCU_SRC1 R8A7791_CLK_SCU_SRC0
1465 >;
1466 clock-output-names =
1467 "ssi-all",
1468 "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
1469 "ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
1470 "scu-all",
1471 "scu-dvc1", "scu-dvc0",
1472 "scu-ctu1-mix1", "scu-ctu0-mix0",
1473 "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
1474 "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
1475 };
1476 mstp11_clks: mstp11_clks@e615099c {
1477 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1478 reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
1479 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
1480 #clock-cells = <1>;
1481 clock-indices = <
1482 R8A7791_CLK_SCIFA3 R8A7791_CLK_SCIFA4 R8A7791_CLK_SCIFA5
1483 >;
1484 clock-output-names = "scifa3", "scifa4", "scifa5";
1485 };
1486 };
1487
1488 rst: reset-controller@e6160000 {
1489 compatible = "renesas,r8a7791-rst";
1490 reg = <0 0xe6160000 0 0x0100>;
1491 };
1492
1493 prr: chipid@ff000044 {
1494 compatible = "renesas,prr";
1495 reg = <0 0xff000044 0 4>;
1496 };
1497
1498 sysc: system-controller@e6180000 {
1499 compatible = "renesas,r8a7791-sysc";
1500 reg = <0 0xe6180000 0 0x0200>;
1501 #power-domain-cells = <1>;
1502 };
1503
1504 qspi: spi@e6b10000 {
1505 compatible = "renesas,qspi-r8a7791", "renesas,qspi";
1506 reg = <0 0xe6b10000 0 0x2c>;
1507 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
1508 clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>;
1509 dmas = <&dmac0 0x17>, <&dmac0 0x18>,
1510 <&dmac1 0x17>, <&dmac1 0x18>;
1511 dma-names = "tx", "rx", "tx", "rx";
1512 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1513 num-cs = <1>;
1514 #address-cells = <1>;
1515 #size-cells = <0>;
1516 status = "disabled";
1517 };
1518
1519 msiof0: spi@e6e20000 {
1520 compatible = "renesas,msiof-r8a7791";
1521 reg = <0 0xe6e20000 0 0x0064>;
1522 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1523 clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;
1524 dmas = <&dmac0 0x51>, <&dmac0 0x52>,
1525 <&dmac1 0x51>, <&dmac1 0x52>;
1526 dma-names = "tx", "rx", "tx", "rx";
1527 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1528 #address-cells = <1>;
1529 #size-cells = <0>;
1530 status = "disabled";
1531 };
1532
1533 msiof1: spi@e6e10000 {
1534 compatible = "renesas,msiof-r8a7791";
1535 reg = <0 0xe6e10000 0 0x0064>;
1536 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1537 clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>;
1538 dmas = <&dmac0 0x55>, <&dmac0 0x56>,
1539 <&dmac1 0x55>, <&dmac1 0x56>;
1540 dma-names = "tx", "rx", "tx", "rx";
1541 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1542 #address-cells = <1>;
1543 #size-cells = <0>;
1544 status = "disabled";
1545 };
1546
1547 msiof2: spi@e6e00000 {
1548 compatible = "renesas,msiof-r8a7791";
1549 reg = <0 0xe6e00000 0 0x0064>;
1550 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1551 clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>;
1552 dmas = <&dmac0 0x41>, <&dmac0 0x42>,
1553 <&dmac1 0x41>, <&dmac1 0x42>;
1554 dma-names = "tx", "rx", "tx", "rx";
1555 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1556 #address-cells = <1>;
1557 #size-cells = <0>;
1558 status = "disabled";
1559 };
1560
1561 xhci: usb@ee000000 {
1562 compatible = "renesas,xhci-r8a7791", "renesas,rcar-gen2-xhci";
1563 reg = <0 0xee000000 0 0xc00>;
1564 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1565 clocks = <&mstp3_clks R8A7791_CLK_SSUSB>;
1566 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1567 phys = <&usb2 1>;
1568 phy-names = "usb";
1569 status = "disabled";
1570 };
1571
1572 pci0: pci@ee090000 {
1573 compatible = "renesas,pci-r8a7791", "renesas,pci-rcar-gen2";
1574 device_type = "pci";
1575 reg = <0 0xee090000 0 0xc00>,
1576 <0 0xee080000 0 0x1100>;
1577 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1578 clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
1579 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1580 status = "disabled";
1581
1582 bus-range = <0 0>;
1583 #address-cells = <3>;
1584 #size-cells = <2>;
1585 #interrupt-cells = <1>;
1586 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
1587 interrupt-map-mask = <0xff00 0 0 0x7>;
1588 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
1589 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
1590 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1591
1592 usb@0,1 {
1593 reg = <0x800 0 0 0 0>;
1594 device_type = "pci";
1595 phys = <&usb0 0>;
1596 phy-names = "usb";
1597 };
1598
1599 usb@0,2 {
1600 reg = <0x1000 0 0 0 0>;
1601 device_type = "pci";
1602 phys = <&usb0 0>;
1603 phy-names = "usb";
1604 };
1605 };
1606
1607 pci1: pci@ee0d0000 {
1608 compatible = "renesas,pci-r8a7791", "renesas,pci-rcar-gen2";
1609 device_type = "pci";
1610 reg = <0 0xee0d0000 0 0xc00>,
1611 <0 0xee0c0000 0 0x1100>;
1612 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1613 clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
1614 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1615 status = "disabled";
1616
1617 bus-range = <1 1>;
1618 #address-cells = <3>;
1619 #size-cells = <2>;
1620 #interrupt-cells = <1>;
1621 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
1622 interrupt-map-mask = <0xff00 0 0 0x7>;
1623 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
1624 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
1625 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1626
1627 usb@0,1 {
1628 reg = <0x800 0 0 0 0>;
1629 device_type = "pci";
1630 phys = <&usb2 0>;
1631 phy-names = "usb";
1632 };
1633
1634 usb@0,2 {
1635 reg = <0x1000 0 0 0 0>;
1636 device_type = "pci";
1637 phys = <&usb2 0>;
1638 phy-names = "usb";
1639 };
1640 };
1641
1642 pciec: pcie@fe000000 {
1643 compatible = "renesas,pcie-r8a7791", "renesas,pcie-rcar-gen2";
1644 reg = <0 0xfe000000 0 0x80000>;
1645 #address-cells = <3>;
1646 #size-cells = <2>;
1647 bus-range = <0x00 0xff>;
1648 device_type = "pci";
1649 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
1650 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
1651 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
1652 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1653 /* Map all possible DDR as inbound ranges */
1654 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
1655 0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>;
1656 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1657 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1658 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1659 #interrupt-cells = <1>;
1660 interrupt-map-mask = <0 0 0 0>;
1661 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1662 clocks = <&mstp3_clks R8A7791_CLK_PCIEC>, <&pcie_bus_clk>;
1663 clock-names = "pcie", "pcie_bus";
1664 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1665 status = "disabled";
1666 };
1667
1668 ipmmu_sy0: mmu@e6280000 {
1669 compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
1670 reg = <0 0xe6280000 0 0x1000>;
1671 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
1672 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
1673 #iommu-cells = <1>;
1674 status = "disabled";
1675 };
1676
1677 ipmmu_sy1: mmu@e6290000 {
1678 compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
1679 reg = <0 0xe6290000 0 0x1000>;
1680 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1681 #iommu-cells = <1>;
1682 status = "disabled";
1683 };
1684
1685 ipmmu_ds: mmu@e6740000 {
1686 compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
1687 reg = <0 0xe6740000 0 0x1000>;
1688 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
1689 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
1690 #iommu-cells = <1>;
1691 status = "disabled";
1692 };
1693
1694 ipmmu_mp: mmu@ec680000 {
1695 compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
1696 reg = <0 0xec680000 0 0x1000>;
1697 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1698 #iommu-cells = <1>;
1699 status = "disabled";
1700 };
1701
1702 ipmmu_mx: mmu@fe951000 {
1703 compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
1704 reg = <0 0xfe951000 0 0x1000>;
1705 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
1706 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1707 #iommu-cells = <1>;
1708 status = "disabled";
1709 };
1710
1711 ipmmu_rt: mmu@ffc80000 {
1712 compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
1713 reg = <0 0xffc80000 0 0x1000>;
1714 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
1715 #iommu-cells = <1>;
1716 status = "disabled";
1717 };
1718
1719 ipmmu_gp: mmu@e62a0000 {
1720 compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
1721 reg = <0 0xe62a0000 0 0x1000>;
1722 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
1723 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
1724 #iommu-cells = <1>;
1725 status = "disabled";
1726 };
1727
1728 rcar_sound: sound@ec500000 {
1729 /*
1730 * #sound-dai-cells is required
1731 *
1732 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1733 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1734 */
1735 compatible = "renesas,rcar_sound-r8a7791", "renesas,rcar_sound-gen2";
1736 reg = <0 0xec500000 0 0x1000>, /* SCU */
1737 <0 0xec5a0000 0 0x100>, /* ADG */
1738 <0 0xec540000 0 0x1000>, /* SSIU */
1739 <0 0xec541000 0 0x280>, /* SSI */
1740 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
1741 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1742
1743 clocks = <&mstp10_clks R8A7791_CLK_SSI_ALL>,
1744 <&mstp10_clks R8A7791_CLK_SSI9>, <&mstp10_clks R8A7791_CLK_SSI8>,
1745 <&mstp10_clks R8A7791_CLK_SSI7>, <&mstp10_clks R8A7791_CLK_SSI6>,
1746 <&mstp10_clks R8A7791_CLK_SSI5>, <&mstp10_clks R8A7791_CLK_SSI4>,
1747 <&mstp10_clks R8A7791_CLK_SSI3>, <&mstp10_clks R8A7791_CLK_SSI2>,
1748 <&mstp10_clks R8A7791_CLK_SSI1>, <&mstp10_clks R8A7791_CLK_SSI0>,
1749 <&mstp10_clks R8A7791_CLK_SCU_SRC9>, <&mstp10_clks R8A7791_CLK_SCU_SRC8>,
1750 <&mstp10_clks R8A7791_CLK_SCU_SRC7>, <&mstp10_clks R8A7791_CLK_SCU_SRC6>,
1751 <&mstp10_clks R8A7791_CLK_SCU_SRC5>, <&mstp10_clks R8A7791_CLK_SCU_SRC4>,
1752 <&mstp10_clks R8A7791_CLK_SCU_SRC3>, <&mstp10_clks R8A7791_CLK_SCU_SRC2>,
1753 <&mstp10_clks R8A7791_CLK_SCU_SRC1>, <&mstp10_clks R8A7791_CLK_SCU_SRC0>,
1754 <&mstp10_clks R8A7791_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7791_CLK_SCU_CTU1_MIX1>,
1755 <&mstp10_clks R8A7791_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7791_CLK_SCU_CTU1_MIX1>,
1756 <&mstp10_clks R8A7791_CLK_SCU_DVC0>, <&mstp10_clks R8A7791_CLK_SCU_DVC1>,
1757 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
1758 clock-names = "ssi-all",
1759 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
1760 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
1761 "src.9", "src.8", "src.7", "src.6", "src.5",
1762 "src.4", "src.3", "src.2", "src.1", "src.0",
1763 "ctu.0", "ctu.1",
1764 "mix.0", "mix.1",
1765 "dvc.0", "dvc.1",
1766 "clk_a", "clk_b", "clk_c", "clk_i";
1767 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1768
1769 status = "disabled";
1770
1771 rcar_sound,dvc {
1772 dvc0: dvc-0 {
1773 dmas = <&audma0 0xbc>;
1774 dma-names = "tx";
1775 };
1776 dvc1: dvc-1 {
1777 dmas = <&audma0 0xbe>;
1778 dma-names = "tx";
1779 };
1780 };
1781
1782 rcar_sound,mix {
1783 mix0: mix-0 { };
1784 mix1: mix-1 { };
1785 };
1786
1787 rcar_sound,ctu {
1788 ctu00: ctu-0 { };
1789 ctu01: ctu-1 { };
1790 ctu02: ctu-2 { };
1791 ctu03: ctu-3 { };
1792 ctu10: ctu-4 { };
1793 ctu11: ctu-5 { };
1794 ctu12: ctu-6 { };
1795 ctu13: ctu-7 { };
1796 };
1797
1798 rcar_sound,src {
1799 src0: src-0 {
1800 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1801 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1802 dma-names = "rx", "tx";
1803 };
1804 src1: src-1 {
1805 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1806 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1807 dma-names = "rx", "tx";
1808 };
1809 src2: src-2 {
1810 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1811 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1812 dma-names = "rx", "tx";
1813 };
1814 src3: src-3 {
1815 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1816 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1817 dma-names = "rx", "tx";
1818 };
1819 src4: src-4 {
1820 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1821 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1822 dma-names = "rx", "tx";
1823 };
1824 src5: src-5 {
1825 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1826 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1827 dma-names = "rx", "tx";
1828 };
1829 src6: src-6 {
1830 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1831 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1832 dma-names = "rx", "tx";
1833 };
1834 src7: src-7 {
1835 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1836 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1837 dma-names = "rx", "tx";
1838 };
1839 src8: src-8 {
1840 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1841 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1842 dma-names = "rx", "tx";
1843 };
1844 src9: src-9 {
1845 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
1846 dmas = <&audma0 0x97>, <&audma1 0xba>;
1847 dma-names = "rx", "tx";
1848 };
1849 };
1850
1851 rcar_sound,ssi {
1852 ssi0: ssi-0 {
1853 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
1854 dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
1855 dma-names = "rx", "tx", "rxu", "txu";
1856 };
1857 ssi1: ssi-1 {
1858 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1859 dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
1860 dma-names = "rx", "tx", "rxu", "txu";
1861 };
1862 ssi2: ssi-2 {
1863 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
1864 dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
1865 dma-names = "rx", "tx", "rxu", "txu";
1866 };
1867 ssi3: ssi-3 {
1868 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1869 dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
1870 dma-names = "rx", "tx", "rxu", "txu";
1871 };
1872 ssi4: ssi-4 {
1873 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1874 dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
1875 dma-names = "rx", "tx", "rxu", "txu";
1876 };
1877 ssi5: ssi-5 {
1878 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1879 dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
1880 dma-names = "rx", "tx", "rxu", "txu";
1881 };
1882 ssi6: ssi-6 {
1883 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
1884 dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
1885 dma-names = "rx", "tx", "rxu", "txu";
1886 };
1887 ssi7: ssi-7 {
1888 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
1889 dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
1890 dma-names = "rx", "tx", "rxu", "txu";
1891 };
1892 ssi8: ssi-8 {
1893 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
1894 dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
1895 dma-names = "rx", "tx", "rxu", "txu";
1896 };
1897 ssi9: ssi-9 {
1898 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
1899 dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
1900 dma-names = "rx", "tx", "rxu", "txu";
1901 };
1902 };
1903 };
1904 };
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