arch/arm/boot/dts/r8a7792.dtsi

   1 /*
   2  * Device Tree Source for the r8a7792 SoC
   3  *
   4  * Copyright (C) 2016 Cogent Embedded Inc.
   5  *
   6  * This file is licensed under the terms of the GNU General Public License
   7  * version 2.  This program is licensed "as is" without any warranty of any
   8  * kind, whether express or implied.
   9  */
  10
  11 #include <dt-bindings/clock/r8a7792-clock.h>
  12 #include <dt-bindings/interrupt-controller/irq.h>
  13 #include <dt-bindings/interrupt-controller/arm-gic.h>
  14 #include <dt-bindings/power/r8a7792-sysc.h>
  15
  16 / {
  17         compatible = "renesas,r8a7792";
  18         #address-cells = <2>;
  19         #size-cells = <2>;
  20
  21         aliases {
  22                 i2c0 = &i2c0;
  23                 i2c1 = &i2c1;
  24                 i2c2 = &i2c2;
  25                 i2c3 = &i2c3;
  26                 i2c4 = &i2c4;
  27                 i2c5 = &i2c5;
  28                 spi0 = &qspi;
  29                 spi1 = &msiof0;
  30                 spi2 = &msiof1;
  31                 vin0 = &vin0;
  32                 vin1 = &vin1;
  33                 vin2 = &vin2;
  34                 vin3 = &vin3;
  35                 vin4 = &vin4;
  36                 vin5 = &vin5;
  37         };
  38
  39         cpus {
  40                 #address-cells = <1>;
  41                 #size-cells = <0>;
  42                 enable-method = "renesas,apmu";
  43
  44                 cpu0: cpu@0 {
  45                         device_type = "cpu";
  46                         compatible = "arm,cortex-a15";
  47                         reg = <0>;
  48                         clock-frequency = <1000000000>;
  49                         clocks = <&cpg_clocks R8A7792_CLK_Z>;
  50                         power-domains = <&sysc R8A7792_PD_CA15_CPU0>;
  51                         next-level-cache = <&L2_CA15>;
  52                 };
  53
  54                 cpu1: cpu@1 {
  55                         device_type = "cpu";
  56                         compatible = "arm,cortex-a15";
  57                         reg = <1>;
  58                         clock-frequency = <1000000000>;
  59                         power-domains = <&sysc R8A7792_PD_CA15_CPU1>;
  60                         next-level-cache = <&L2_CA15>;
  61                 };
  62
  63                 L2_CA15: cache-controller@0 {
  64                         compatible = "cache";
  65                         reg = <0>;
  66                         cache-unified;
  67                         cache-level = <2>;
  68                         power-domains = <&sysc R8A7792_PD_CA15_SCU>;
  69                 };
  70         };
  71
  72         soc {
  73                 compatible = "simple-bus";
  74                 interrupt-parent = <&gic>;
  75
  76                 #address-cells = <2>;
  77                 #size-cells = <2>;
  78                 ranges;
  79
  80                 apmu@e6152000 {
  81                         compatible = "renesas,r8a7792-apmu", "renesas,apmu";
  82                         reg = <0 0xe6152000 0 0x188>;
  83                         cpus = <&cpu0 &cpu1>;
  84                 };
  85
  86                 gic: interrupt-controller@f1001000 {
  87                         compatible = "arm,gic-400";
  88                         #interrupt-cells = <3>;
  89                         interrupt-controller;
  90                         reg = <0 0xf1001000 0 0x1000>,
  91                               <0 0xf1002000 0 0x1000>,
  92                               <0 0xf1004000 0 0x2000>,
  93                               <0 0xf1006000 0 0x2000>;
  94                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
  95                                       IRQ_TYPE_LEVEL_HIGH)>;
  96                 };
  97
  98                 irqc: interrupt-controller@e61c0000 {
  99                         compatible = "renesas,irqc-r8a7792", "renesas,irqc";
 100                         #interrupt-cells = <2>;
 101                         interrupt-controller;
 102                         reg = <0 0xe61c0000 0 0x200>;
 103                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 104                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 105                                      <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 106                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 107                         clocks = <&mstp4_clks R8A7792_CLK_IRQC>;
 108                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 109                 };
 110
 111                 timer {
 112                         compatible = "arm,armv7-timer";
 113                         interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
 114                                       IRQ_TYPE_LEVEL_LOW)>,
 115                                      <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
 116                                       IRQ_TYPE_LEVEL_LOW)>,
 117                                      <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
 118                                       IRQ_TYPE_LEVEL_LOW)>,
 119                                      <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
 120                                       IRQ_TYPE_LEVEL_LOW)>;
 121                 };
 122
 123                 rst: reset-controller@e6160000 {
 124                         compatible = "renesas,r8a7792-rst";
 125                         reg = <0 0xe6160000 0 0x0100>;
 126                 };
 127
 128                 prr: chipid@ff000044 {
 129                         compatible = "renesas,prr";
 130                         reg = <0 0xff000044 0 4>;
 131                 };
 132
 133                 sysc: system-controller@e6180000 {
 134                         compatible = "renesas,r8a7792-sysc";
 135                         reg = <0 0xe6180000 0 0x0200>;
 136                         #power-domain-cells = <1>;
 137                 };
 138
 139                 pfc: pin-controller@e6060000 {
 140                         compatible = "renesas,pfc-r8a7792";
 141                         reg = <0 0xe6060000 0 0x144>;
 142                 };
 143
 144                 gpio0: gpio@e6050000 {
 145                         compatible = "renesas,gpio-r8a7792",
 146                                      "renesas,gpio-rcar";
 147                         reg = <0 0xe6050000 0 0x50>;
 148                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 149                         #gpio-cells = <2>;
 150                         gpio-controller;
 151                         gpio-ranges = <&pfc 0 0 29>;
 152                         #interrupt-cells = <2>;
 153                         interrupt-controller;
 154                         clocks = <&mstp9_clks R8A7792_CLK_GPIO0>;
 155                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 156                 };
 157
 158                 gpio1: gpio@e6051000 {
 159                         compatible = "renesas,gpio-r8a7792",
 160                                      "renesas,gpio-rcar";
 161                         reg = <0 0xe6051000 0 0x50>;
 162                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 163                         #gpio-cells = <2>;
 164                         gpio-controller;
 165                         gpio-ranges = <&pfc 0 32 23>;
 166                         #interrupt-cells = <2>;
 167                         interrupt-controller;
 168                         clocks = <&mstp9_clks R8A7792_CLK_GPIO1>;
 169                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 170                 };
 171
 172                 gpio2: gpio@e6052000 {
 173                         compatible = "renesas,gpio-r8a7792",
 174                                      "renesas,gpio-rcar";
 175                         reg = <0 0xe6052000 0 0x50>;
 176                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 177                         #gpio-cells = <2>;
 178                         gpio-controller;
 179                         gpio-ranges = <&pfc 0 64 32>;
 180                         #interrupt-cells = <2>;
 181                         interrupt-controller;
 182                         clocks = <&mstp9_clks R8A7792_CLK_GPIO2>;
 183                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 184                 };
 185
 186                 gpio3: gpio@e6053000 {
 187                         compatible = "renesas,gpio-r8a7792",
 188                                      "renesas,gpio-rcar";
 189                         reg = <0 0xe6053000 0 0x50>;
 190                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 191                         #gpio-cells = <2>;
 192                         gpio-controller;
 193                         gpio-ranges = <&pfc 0 96 28>;
 194                         #interrupt-cells = <2>;
 195                         interrupt-controller;
 196                         clocks = <&mstp9_clks R8A7792_CLK_GPIO3>;
 197                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 198                 };
 199
 200                 gpio4: gpio@e6054000 {
 201                         compatible = "renesas,gpio-r8a7792",
 202                                      "renesas,gpio-rcar";
 203                         reg = <0 0xe6054000 0 0x50>;
 204                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 205                         #gpio-cells = <2>;
 206                         gpio-controller;
 207                         gpio-ranges = <&pfc 0 128 17>;
 208                         #interrupt-cells = <2>;
 209                         interrupt-controller;
 210                         clocks = <&mstp9_clks R8A7792_CLK_GPIO4>;
 211                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 212                 };
 213
 214                 gpio5: gpio@e6055000 {
 215                         compatible = "renesas,gpio-r8a7792",
 216                                      "renesas,gpio-rcar";
 217                         reg = <0 0xe6055000 0 0x50>;
 218                         interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 219                         #gpio-cells = <2>;
 220                         gpio-controller;
 221                         gpio-ranges = <&pfc 0 160 17>;
 222                         #interrupt-cells = <2>;
 223                         interrupt-controller;
 224                         clocks = <&mstp9_clks R8A7792_CLK_GPIO5>;
 225                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 226                 };
 227
 228                 gpio6: gpio@e6055100 {
 229                         compatible = "renesas,gpio-r8a7792",
 230                                      "renesas,gpio-rcar";
 231                         reg = <0 0xe6055100 0 0x50>;
 232                         interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 233                         #gpio-cells = <2>;
 234                         gpio-controller;
 235                         gpio-ranges = <&pfc 0 192 17>;
 236                         #interrupt-cells = <2>;
 237                         interrupt-controller;
 238                         clocks = <&mstp9_clks R8A7792_CLK_GPIO6>;
 239                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 240                 };
 241
 242                 gpio7: gpio@e6055200 {
 243                         compatible = "renesas,gpio-r8a7792",
 244                                      "renesas,gpio-rcar";
 245                         reg = <0 0xe6055200 0 0x50>;
 246                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 247                         #gpio-cells = <2>;
 248                         gpio-controller;
 249                         gpio-ranges = <&pfc 0 224 17>;
 250                         #interrupt-cells = <2>;
 251                         interrupt-controller;
 252                         clocks = <&mstp9_clks R8A7792_CLK_GPIO7>;
 253                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 254                 };
 255
 256                 gpio8: gpio@e6055300 {
 257                         compatible = "renesas,gpio-r8a7792",
 258                                      "renesas,gpio-rcar";
 259                         reg = <0 0xe6055300 0 0x50>;
 260                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 261                         #gpio-cells = <2>;
 262                         gpio-controller;
 263                         gpio-ranges = <&pfc 0 256 17>;
 264                         #interrupt-cells = <2>;
 265                         interrupt-controller;
 266                         clocks = <&mstp9_clks R8A7792_CLK_GPIO8>;
 267                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 268                 };
 269
 270                 gpio9: gpio@e6055400 {
 271                         compatible = "renesas,gpio-r8a7792",
 272                                      "renesas,gpio-rcar";
 273                         reg = <0 0xe6055400 0 0x50>;
 274                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 275                         #gpio-cells = <2>;
 276                         gpio-controller;
 277                         gpio-ranges = <&pfc 0 288 17>;
 278                         #interrupt-cells = <2>;
 279                         interrupt-controller;
 280                         clocks = <&mstp9_clks R8A7792_CLK_GPIO9>;
 281                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 282                 };
 283
 284                 gpio10: gpio@e6055500 {
 285                         compatible = "renesas,gpio-r8a7792",
 286                                      "renesas,gpio-rcar";
 287                         reg = <0 0xe6055500 0 0x50>;
 288                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 289                         #gpio-cells = <2>;
 290                         gpio-controller;
 291                         gpio-ranges = <&pfc 0 320 32>;
 292                         #interrupt-cells = <2>;
 293                         interrupt-controller;
 294                         clocks = <&mstp9_clks R8A7792_CLK_GPIO10>;
 295                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 296                 };
 297
 298                 gpio11: gpio@e6055600 {
 299                         compatible = "renesas,gpio-r8a7792",
 300                                      "renesas,gpio-rcar";
 301                         reg = <0 0xe6055600 0 0x50>;
 302                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 303                         #gpio-cells = <2>;
 304                         gpio-controller;
 305                         gpio-ranges = <&pfc 0 352 30>;
 306                         #interrupt-cells = <2>;
 307                         interrupt-controller;
 308                         clocks = <&mstp9_clks R8A7792_CLK_GPIO11>;
 309                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 310                 };
 311
 312                 dmac0: dma-controller@e6700000 {
 313                         compatible = "renesas,dmac-r8a7792",
 314                                      "renesas,rcar-dmac";
 315                         reg = <0 0xe6700000 0 0x20000>;
 316                         interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
 317                                       GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
 318                                       GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
 319                                       GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
 320                                       GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
 321                                       GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
 322                                       GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
 323                                       GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
 324                                       GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
 325                                       GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
 326                                       GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
 327                                       GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
 328                                       GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
 329                                       GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
 330                                       GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
 331                                       GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
 332                         interrupt-names = "error",
 333                                           "ch0", "ch1", "ch2", "ch3",
 334                                           "ch4", "ch5", "ch6", "ch7",
 335                                           "ch8", "ch9", "ch10", "ch11",
 336                                           "ch12", "ch13", "ch14";
 337                         clocks = <&mstp2_clks R8A7792_CLK_SYS_DMAC0>;
 338                         clock-names = "fck";
 339                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 340                         #dma-cells = <1>;
 341                         dma-channels = <15>;
 342                 };
 343
 344                 dmac1: dma-controller@e6720000 {
 345                         compatible = "renesas,dmac-r8a7792",
 346                                      "renesas,rcar-dmac";
 347                         reg = <0 0xe6720000 0 0x20000>;
 348                         interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
 349                                       GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
 350                                       GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
 351                                       GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
 352                                       GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
 353                                       GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
 354                                       GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
 355                                       GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
 356                                       GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
 357                                       GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
 358                                       GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
 359                                       GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
 360                                       GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
 361                                       GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
 362                                       GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
 363                                       GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
 364                         interrupt-names = "error",
 365                                           "ch0", "ch1", "ch2", "ch3",
 366                                           "ch4", "ch5", "ch6", "ch7",
 367                                           "ch8", "ch9", "ch10", "ch11",
 368                                           "ch12", "ch13", "ch14";
 369                         clocks = <&mstp2_clks R8A7792_CLK_SYS_DMAC1>;
 370                         clock-names = "fck";
 371                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 372                         #dma-cells = <1>;
 373                         dma-channels = <15>;
 374                 };
 375
 376                 scif0: serial@e6e60000 {
 377                         compatible = "renesas,scif-r8a7792",
 378                                      "renesas,rcar-gen2-scif", "renesas,scif";
 379                         reg = <0 0xe6e60000 0 64>;
 380                         interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
 381                         clocks = <&mstp7_clks R8A7792_CLK_SCIF0>, <&zs_clk>,
 382                                  <&scif_clk>;
 383                         clock-names = "fck", "brg_int", "scif_clk";
 384                         dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
 385                                <&dmac1 0x29>, <&dmac1 0x2a>;
 386                         dma-names = "tx", "rx", "tx", "rx";
 387                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 388                         status = "disabled";
 389                 };
 390
 391                 scif1: serial@e6e68000 {
 392                         compatible = "renesas,scif-r8a7792",
 393                                      "renesas,rcar-gen2-scif", "renesas,scif";
 394                         reg = <0 0xe6e68000 0 64>;
 395                         interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 396                         clocks = <&mstp7_clks R8A7792_CLK_SCIF1>, <&zs_clk>,
 397                                  <&scif_clk>;
 398                         clock-names = "fck", "brg_int", "scif_clk";
 399                         dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
 400                                <&dmac1 0x2d>, <&dmac1 0x2e>;
 401                         dma-names = "tx", "rx", "tx", "rx";
 402                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 403                         status = "disabled";
 404                 };
 405
 406                 scif2: serial@e6e58000 {
 407                         compatible = "renesas,scif-r8a7792",
 408                                      "renesas,rcar-gen2-scif", "renesas,scif";
 409                         reg = <0 0xe6e58000 0 64>;
 410                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 411                         clocks = <&mstp7_clks R8A7792_CLK_SCIF2>, <&zs_clk>,
 412                                  <&scif_clk>;
 413                         clock-names = "fck", "brg_int", "scif_clk";
 414                         dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
 415                                <&dmac1 0x2b>, <&dmac1 0x2c>;
 416                         dma-names = "tx", "rx", "tx", "rx";
 417                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 418                         status = "disabled";
 419                 };
 420
 421                 scif3: serial@e6ea8000 {
 422                         compatible = "renesas,scif-r8a7792",
 423                                      "renesas,rcar-gen2-scif", "renesas,scif";
 424                         reg = <0 0xe6ea8000 0 64>;
 425                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 426                         clocks = <&mstp7_clks R8A7792_CLK_SCIF3>, <&zs_clk>,
 427                                  <&scif_clk>;
 428                         clock-names = "fck", "brg_int", "scif_clk";
 429                         dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
 430                                <&dmac1 0x2f>, <&dmac1 0x30>;
 431                         dma-names = "tx", "rx", "tx", "rx";
 432                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 433                         status = "disabled";
 434                 };
 435
 436                 hscif0: serial@e62c0000 {
 437                         compatible = "renesas,hscif-r8a7792",
 438                                      "renesas,rcar-gen2-hscif", "renesas,hscif";
 439                         reg = <0 0xe62c0000 0 96>;
 440                         interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 441                         clocks = <&mstp7_clks R8A7792_CLK_HSCIF0>, <&zs_clk>,
 442                                  <&scif_clk>;
 443                         clock-names = "fck", "brg_int", "scif_clk";
 444                         dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
 445                                <&dmac1 0x39>, <&dmac1 0x3a>;
 446                         dma-names = "tx", "rx", "tx", "rx";
 447                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 448                         status = "disabled";
 449                 };
 450
 451                 hscif1: serial@e62c8000 {
 452                         compatible = "renesas,hscif-r8a7792",
 453                                      "renesas,rcar-gen2-hscif", "renesas,hscif";
 454                         reg = <0 0xe62c8000 0 96>;
 455                         interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
 456                         clocks = <&mstp7_clks R8A7792_CLK_HSCIF1>, <&zs_clk>,
 457                                  <&scif_clk>;
 458                         clock-names = "fck", "brg_int", "scif_clk";
 459                         dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
 460                                <&dmac1 0x4d>, <&dmac1 0x4e>;
 461                         dma-names = "tx", "rx", "tx", "rx";
 462                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 463                         status = "disabled";
 464                 };
 465
 466                 sdhi0: sd@ee100000 {
 467                         compatible = "renesas,sdhi-r8a7792";
 468                         reg = <0 0xee100000 0 0x328>;
 469                         interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
 470                         dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
 471                                <&dmac1 0xcd>, <&dmac1 0xce>;
 472                         dma-names = "tx", "rx", "tx", "rx";
 473                         clocks = <&mstp3_clks R8A7792_CLK_SDHI0>;
 474                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 475                         status = "disabled";
 476                 };
 477
 478                 jpu: jpeg-codec@fe980000 {
 479                         compatible = "renesas,jpu-r8a7792",
 480                                      "renesas,rcar-gen2-jpu";
 481                         reg = <0 0xfe980000 0 0x10300>;
 482                         interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
 483                         clocks = <&mstp1_clks R8A7792_CLK_JPU>;
 484                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 485                 };
 486
 487                 avb: ethernet@e6800000 {
 488                         compatible = "renesas,etheravb-r8a7792",
 489                                      "renesas,etheravb-rcar-gen2";
 490                         reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
 491                         interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
 492                         clocks = <&mstp8_clks R8A7792_CLK_ETHERAVB>;
 493                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 494                         #address-cells = <1>;
 495                         #size-cells = <0>;
 496                         status = "disabled";
 497                 };
 498
 499                 /* I2C doesn't need pinmux */
 500                 i2c0: i2c@e6508000 {
 501                         compatible = "renesas,i2c-r8a7792";
 502                         reg = <0 0xe6508000 0 0x40>;
 503                         interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
 504                         clocks = <&mstp9_clks R8A7792_CLK_I2C0>;
 505                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 506                         i2c-scl-internal-delay-ns = <6>;
 507                         #address-cells = <1>;
 508                         #size-cells = <0>;
 509                         status = "disabled";
 510                 };
 511
 512                 i2c1: i2c@e6518000 {
 513                         compatible = "renesas,i2c-r8a7792";
 514                         reg = <0 0xe6518000 0 0x40>;
 515                         interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
 516                         clocks = <&mstp9_clks R8A7792_CLK_I2C1>;
 517                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 518                         i2c-scl-internal-delay-ns = <6>;
 519                         #address-cells = <1>;
 520                         #size-cells = <0>;
 521                         status = "disabled";
 522                 };
 523
 524                 i2c2: i2c@e6530000 {
 525                         compatible = "renesas,i2c-r8a7792";
 526                         reg = <0 0xe6530000 0 0x40>;
 527                         interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
 528                         clocks = <&mstp9_clks R8A7792_CLK_I2C2>;
 529                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 530                         i2c-scl-internal-delay-ns = <6>;
 531                         #address-cells = <1>;
 532                         #size-cells = <0>;
 533                         status = "disabled";
 534                 };
 535
 536                 i2c3: i2c@e6540000 {
 537                         compatible = "renesas,i2c-r8a7792";
 538                         reg = <0 0xe6540000 0 0x40>;
 539                         interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
 540                         clocks = <&mstp9_clks R8A7792_CLK_I2C3>;
 541                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 542                         i2c-scl-internal-delay-ns = <6>;
 543                         #address-cells = <1>;
 544                         #size-cells = <0>;
 545                         status = "disabled";
 546                 };
 547
 548                 i2c4: i2c@e6520000 {
 549                         compatible = "renesas,i2c-r8a7792";
 550                         reg = <0 0xe6520000 0 0x40>;
 551                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 552                         clocks = <&mstp9_clks R8A7792_CLK_I2C4>;
 553                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 554                         i2c-scl-internal-delay-ns = <6>;
 555                         #address-cells = <1>;
 556                         #size-cells = <0>;
 557                         status = "disabled";
 558                 };
 559
 560                 i2c5: i2c@e6528000 {
 561                         compatible = "renesas,i2c-r8a7792";
 562                         reg = <0 0xe6528000 0 0x40>;
 563                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 564                         clocks = <&mstp9_clks R8A7792_CLK_I2C5>;
 565                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 566                         i2c-scl-internal-delay-ns = <110>;
 567                         #address-cells = <1>;
 568                         #size-cells = <0>;
 569                         status = "disabled";
 570                 };
 571
 572                 qspi: spi@e6b10000 {
 573                         compatible = "renesas,qspi-r8a7792", "renesas,qspi";
 574                         reg = <0 0xe6b10000 0 0x2c>;
 575                         interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
 576                         clocks = <&mstp9_clks R8A7792_CLK_QSPI_MOD>;
 577                         dmas = <&dmac0 0x17>, <&dmac0 0x18>,
 578                                <&dmac1 0x17>, <&dmac1 0x18>;
 579                         dma-names = "tx", "rx", "tx", "rx";
 580                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 581                         num-cs = <1>;
 582                         #address-cells = <1>;
 583                         #size-cells = <0>;
 584                         status = "disabled";
 585                 };
 586
 587                 msiof0: spi@e6e20000 {
 588                         compatible = "renesas,msiof-r8a7792";
 589                         reg = <0 0xe6e20000 0 0x0064>;
 590                         interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
 591                         clocks = <&mstp0_clks R8A7792_CLK_MSIOF0>;
 592                         dmas = <&dmac0 0x51>, <&dmac0 0x52>,
 593                                <&dmac1 0x51>, <&dmac1 0x52>;
 594                         dma-names = "tx", "rx", "tx", "rx";
 595                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 596                         #address-cells = <1>;
 597                         #size-cells = <0>;
 598                         status = "disabled";
 599                 };
 600
 601                 msiof1: spi@e6e10000 {
 602                         compatible = "renesas,msiof-r8a7792";
 603                         reg = <0 0xe6e10000 0 0x0064>;
 604                         interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
 605                         clocks = <&mstp2_clks R8A7792_CLK_MSIOF1>;
 606                         dmas = <&dmac0 0x55>, <&dmac0 0x56>,
 607                                <&dmac1 0x55>, <&dmac1 0x56>;
 608                         dma-names = "tx", "rx", "tx", "rx";
 609                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 610                         #address-cells = <1>;
 611                         #size-cells = <0>;
 612                         status = "disabled";
 613                 };
 614
 615                 du: display@feb00000 {
 616                         compatible = "renesas,du-r8a7792";
 617                         reg = <0 0xfeb00000 0 0x40000>;
 618                         reg-names = "du";
 619                         interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
 620                                      <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
 621                         clocks = <&mstp7_clks R8A7792_CLK_DU0>,
 622                                  <&mstp7_clks R8A7792_CLK_DU1>;
 623                         clock-names = "du.0", "du.1";
 624                         status = "disabled";
 625
 626                         ports {
 627                                 #address-cells = <1>;
 628                                 #size-cells = <0>;
 629
 630                                 port@0 {
 631                                         reg = <0>;
 632                                         du_out_rgb0: endpoint {
 633                                         };
 634                                 };
 635                                 port@1 {
 636                                         reg = <1>;
 637                                         du_out_rgb1: endpoint {
 638                                         };
 639                                 };
 640                         };
 641                 };
 642
 643                 can0: can@e6e80000 {
 644                         compatible = "renesas,can-r8a7792",
 645                                      "renesas,rcar-gen2-can";
 646                         reg = <0 0xe6e80000 0 0x1000>;
 647                         interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
 648                         clocks = <&mstp9_clks R8A7792_CLK_CAN0>,
 649                                  <&rcan_clk>, <&can_clk>;
 650                         clock-names = "clkp1", "clkp2", "can_clk";
 651                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 652                         status = "disabled";
 653                 };
 654
 655                 can1: can@e6e88000 {
 656                         compatible = "renesas,can-r8a7792",
 657                                      "renesas,rcar-gen2-can";
 658                         reg = <0 0xe6e88000 0 0x1000>;
 659                         interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
 660                         clocks = <&mstp9_clks R8A7792_CLK_CAN1>,
 661                                  <&rcan_clk>, <&can_clk>;
 662                         clock-names = "clkp1", "clkp2", "can_clk";
 663                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 664                         status = "disabled";
 665                 };
 666
 667                 vin0: video@e6ef0000 {
 668                         compatible = "renesas,vin-r8a7792",
 669                                      "renesas,rcar-gen2-vin";
 670                         reg = <0 0xe6ef0000 0 0x1000>;
 671                         interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
 672                         clocks = <&mstp8_clks R8A7792_CLK_VIN0>;
 673                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 674                         status = "disabled";
 675                 };
 676
 677                 vin1: video@e6ef1000 {
 678                         compatible = "renesas,vin-r8a7792",
 679                                      "renesas,rcar-gen2-vin";
 680                         reg = <0 0xe6ef1000 0 0x1000>;
 681                         interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
 682                         clocks = <&mstp8_clks R8A7792_CLK_VIN1>;
 683                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 684                         status = "disabled";
 685                 };
 686
 687                 vin2: video@e6ef2000 {
 688                         compatible = "renesas,vin-r8a7792",
 689                                      "renesas,rcar-gen2-vin";
 690                         reg = <0 0xe6ef2000 0 0x1000>;
 691                         interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
 692                         clocks = <&mstp8_clks R8A7792_CLK_VIN2>;
 693                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 694                         status = "disabled";
 695                 };
 696
 697                 vin3: video@e6ef3000 {
 698                         compatible = "renesas,vin-r8a7792",
 699                                      "renesas,rcar-gen2-vin";
 700                         reg = <0 0xe6ef3000 0 0x1000>;
 701                         interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
 702                         clocks = <&mstp8_clks R8A7792_CLK_VIN3>;
 703                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 704                         status = "disabled";
 705                 };
 706
 707                 vin4: video@e6ef4000 {
 708                         compatible = "renesas,vin-r8a7792",
 709                                      "renesas,rcar-gen2-vin";
 710                         reg = <0 0xe6ef4000 0 0x1000>;
 711                         interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 712                         clocks = <&mstp8_clks R8A7792_CLK_VIN4>;
 713                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 714                         status = "disabled";
 715                 };
 716
 717                 vin5: video@e6ef5000 {
 718                         compatible = "renesas,vin-r8a7792",
 719                                      "renesas,rcar-gen2-vin";
 720                         reg = <0 0xe6ef5000 0 0x1000>;
 721                         interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
 722                         clocks = <&mstp8_clks R8A7792_CLK_VIN5>;
 723                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 724                         status = "disabled";
 725                 };
 726
 727                 vsp1@fe928000 {
 728                         compatible = "renesas,vsp1";
 729                         reg = <0 0xfe928000 0 0x8000>;
 730                         interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
 731                         clocks = <&mstp1_clks R8A7792_CLK_VSP1_SY>;
 732                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 733                 };
 734
 735                 vsp1@fe930000 {
 736                         compatible = "renesas,vsp1";
 737                         reg = <0 0xfe930000 0 0x8000>;
 738                         interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
 739                         clocks = <&mstp1_clks R8A7792_CLK_VSP1DU0>;
 740                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 741                 };
 742
 743                 vsp1@fe938000 {
 744                         compatible = "renesas,vsp1";
 745                         reg = <0 0xfe938000 0 0x8000>;
 746                         interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
 747                         clocks = <&mstp1_clks R8A7792_CLK_VSP1DU1>;
 748                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 749                 };
 750
 751                 /* Special CPG clocks */
 752                 cpg_clocks: cpg_clocks@e6150000 {
 753                         compatible = "renesas,r8a7792-cpg-clocks",
 754                                      "renesas,rcar-gen2-cpg-clocks";
 755                         reg = <0 0xe6150000 0 0x1000>;
 756                         clocks = <&extal_clk>;
 757                         #clock-cells = <1>;
 758                         clock-output-names = "main", "pll0", "pll1", "pll3",
 759                                              "lb", "qspi", "z";
 760                         #power-domain-cells = <0>;
 761                 };
 762
 763                 /* Fixed factor clocks */
 764                 pll1_div2_clk: pll1_div2 {
 765                         compatible = "fixed-factor-clock";
 766                         clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
 767                         #clock-cells = <0>;
 768                         clock-div = <2>;
 769                         clock-mult = <1>;
 770                 };
 771                 zx_clk: zx {
 772                         compatible = "fixed-factor-clock";
 773                         clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
 774                         #clock-cells = <0>;
 775                         clock-div = <3>;
 776                         clock-mult = <1>;
 777                 };
 778                 zs_clk: zs {
 779                         compatible = "fixed-factor-clock";
 780                         clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
 781                         #clock-cells = <0>;
 782                         clock-div = <6>;
 783                         clock-mult = <1>;
 784                 };
 785                 hp_clk: hp {
 786                         compatible = "fixed-factor-clock";
 787                         clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
 788                         #clock-cells = <0>;
 789                         clock-div = <12>;
 790                         clock-mult = <1>;
 791                 };
 792                 p_clk: p {
 793                         compatible = "fixed-factor-clock";
 794                         clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
 795                         #clock-cells = <0>;
 796                         clock-div = <24>;
 797                         clock-mult = <1>;
 798                 };
 799                 cp_clk: cp {
 800                         compatible = "fixed-factor-clock";
 801                         clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
 802                         #clock-cells = <0>;
 803                         clock-div = <48>;
 804                         clock-mult = <1>;
 805                 };
 806                 mp_clk: mp {
 807                         compatible = "fixed-factor-clock";
 808                         clocks = <&pll1_div2_clk>;
 809                         #clock-cells = <0>;
 810                         clock-div = <15>;
 811                         clock-mult = <1>;
 812                 };
 813                 m2_clk: m2 {
 814                         compatible = "fixed-factor-clock";
 815                         clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
 816                         #clock-cells = <0>;
 817                         clock-div = <8>;
 818                         clock-mult = <1>;
 819                 };
 820                 sd_clk: sd {
 821                         compatible = "fixed-factor-clock";
 822                         clocks = <&pll1_div2_clk>;
 823                         #clock-cells = <0>;
 824                         clock-div = <8>;
 825                         clock-mult = <1>;
 826                 };
 827                 rcan_clk: rcan {
 828                         compatible = "fixed-factor-clock";
 829                         clocks = <&pll1_div2_clk>;
 830                         #clock-cells = <0>;
 831                         clock-div = <49>;
 832                         clock-mult = <1>;
 833                 };
 834                 zg_clk: zg {
 835                         compatible = "fixed-factor-clock";
 836                         clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
 837                         #clock-cells = <0>;
 838                         clock-div = <5>;
 839                         clock-mult = <1>;
 840                 };
 841
 842                 /* Gate clocks */
 843                 mstp0_clks: mstp0_clks@e6150130 {
 844                         compatible = "renesas,r8a7792-mstp-clocks",
 845                                      "renesas,cpg-mstp-clocks";
 846                         reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
 847                         clocks = <&mp_clk>;
 848                         #clock-cells = <1>;
 849                         clock-indices = <R8A7792_CLK_MSIOF0>;
 850                         clock-output-names = "msiof0";
 851                 };
 852                 mstp1_clks: mstp1_clks@e6150134 {
 853                         compatible = "renesas,r8a7792-mstp-clocks",
 854                                      "renesas,cpg-mstp-clocks";
 855                         reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
 856                         clocks = <&m2_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
 857                         #clock-cells = <1>;
 858                         clock-indices = <
 859                                 R8A7792_CLK_JPU
 860                                 R8A7792_CLK_VSP1DU1 R8A7792_CLK_VSP1DU0
 861                                 R8A7792_CLK_VSP1_SY
 862                         >;
 863                         clock-output-names = "jpu", "vsp1du1", "vsp1du0",
 864                                              "vsp1-sy";
 865                 };
 866                 mstp2_clks: mstp2_clks@e6150138 {
 867                         compatible = "renesas,r8a7792-mstp-clocks",
 868                                      "renesas,cpg-mstp-clocks";
 869                         reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
 870                         clocks = <&mp_clk>, <&zs_clk>, <&zs_clk>;
 871                         #clock-cells = <1>;
 872                         clock-indices = <
 873                                 R8A7792_CLK_MSIOF1
 874                                 R8A7792_CLK_SYS_DMAC1 R8A7792_CLK_SYS_DMAC0
 875                         >;
 876                         clock-output-names = "msiof1", "sys-dmac1", "sys-dmac0";
 877                 };
 878                 mstp3_clks: mstp3_clks@e615013c {
 879                         compatible = "renesas,r8a7792-mstp-clocks",
 880                                      "renesas,cpg-mstp-clocks";
 881                         reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
 882                         clocks = <&sd_clk>;
 883                         #clock-cells = <1>;
 884                         renesas,clock-indices = <R8A7792_CLK_SDHI0>;
 885                         clock-output-names = "sdhi0";
 886                 };
 887                 mstp4_clks: mstp4_clks@e6150140 {
 888                         compatible = "renesas,r8a7792-mstp-clocks",
 889                                      "renesas,cpg-mstp-clocks";
 890                         reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
 891                         clocks = <&cp_clk>;
 892                         #clock-cells = <1>;
 893                         clock-indices = <R8A7792_CLK_IRQC>;
 894                         clock-output-names = "irqc";
 895                 };
 896                 mstp7_clks: mstp7_clks@e615014c {
 897                         compatible = "renesas,r8a7792-mstp-clocks",
 898                                      "renesas,cpg-mstp-clocks";
 899                         reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
 900                         clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>,
 901                                  <&p_clk>, <&p_clk>, <&zx_clk>, <&zx_clk>;
 902                         #clock-cells = <1>;
 903                         clock-indices = <
 904                                 R8A7792_CLK_HSCIF1 R8A7792_CLK_HSCIF0
 905                                 R8A7792_CLK_SCIF3 R8A7792_CLK_SCIF2
 906                                 R8A7792_CLK_SCIF1 R8A7792_CLK_SCIF0
 907                                 R8A7792_CLK_DU1 R8A7792_CLK_DU0
 908                         >;
 909                         clock-output-names = "hscif1", "hscif0", "scif3",
 910                                              "scif2", "scif1", "scif0",
 911                                              "du1", "du0";
 912                 };
 913                 mstp8_clks: mstp8_clks@e6150990 {
 914                         compatible = "renesas,r8a7792-mstp-clocks",
 915                                      "renesas,cpg-mstp-clocks";
 916                         reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
 917                         clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
 918                                  <&zg_clk>, <&zg_clk>, <&hp_clk>;
 919                         #clock-cells = <1>;
 920                         clock-indices = <
 921                                 R8A7792_CLK_VIN5 R8A7792_CLK_VIN4
 922                                 R8A7792_CLK_VIN3 R8A7792_CLK_VIN2
 923                                 R8A7792_CLK_VIN1 R8A7792_CLK_VIN0
 924                                 R8A7792_CLK_ETHERAVB
 925                         >;
 926                         clock-output-names = "vin5", "vin4", "vin3", "vin2",
 927                                              "vin1", "vin0", "etheravb";
 928                 };
 929                 mstp9_clks: mstp9_clks@e6150994 {
 930                         compatible = "renesas,r8a7792-mstp-clocks",
 931                                      "renesas,cpg-mstp-clocks";
 932                         reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
 933                         clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
 934                                  <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
 935                                  <&cp_clk>, <&cp_clk>, <&p_clk>, <&p_clk>,
 936                                  <&cpg_clocks R8A7792_CLK_QSPI>,
 937                                  <&cp_clk>, <&cp_clk>, <&hp_clk>, <&hp_clk>,
 938                                  <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
 939                         #clock-cells = <1>;
 940                         clock-indices = <
 941                                 R8A7792_CLK_GPIO7 R8A7792_CLK_GPIO6
 942                                 R8A7792_CLK_GPIO5 R8A7792_CLK_GPIO4
 943                                 R8A7792_CLK_GPIO3 R8A7792_CLK_GPIO2
 944                                 R8A7792_CLK_GPIO1 R8A7792_CLK_GPIO0
 945                                 R8A7792_CLK_GPIO11 R8A7792_CLK_GPIO10
 946                                 R8A7792_CLK_CAN1 R8A7792_CLK_CAN0
 947                                 R8A7792_CLK_QSPI_MOD
 948                                 R8A7792_CLK_GPIO9 R8A7792_CLK_GPIO8
 949                                 R8A7792_CLK_I2C5 R8A7792_CLK_I2C4
 950                                 R8A7792_CLK_I2C3 R8A7792_CLK_I2C2
 951                                 R8A7792_CLK_I2C1 R8A7792_CLK_I2C0
 952                         >;
 953                         clock-output-names =
 954                                 "gpio7", "gpio6", "gpio5", "gpio4",
 955                                 "gpio3", "gpio2", "gpio1", "gpio0",
 956                                 "gpio11", "gpio10", "can1", "can0",
 957                                 "qspi_mod", "gpio9", "gpio8",
 958                                 "i2c5", "i2c4", "i2c3", "i2c2",
 959                                 "i2c1", "i2c0";
 960                 };
 961         };
 962
 963         /* External root clock */
 964         extal_clk: extal {
 965                 compatible = "fixed-clock";
 966                 #clock-cells = <0>;
 967                 /* This value must be overridden by the board. */
 968                 clock-frequency = <0>;
 969         };
 970
 971         /* External SCIF clock */
 972         scif_clk: scif {
 973                 compatible = "fixed-clock";
 974                 #clock-cells = <0>;
 975                 /* This value must be overridden by the board. */
 976                 clock-frequency = <0>;
 977         };
 978
 979         /* External CAN clock */
 980         can_clk: can {
 981                 compatible = "fixed-clock";
 982                 #clock-cells = <0>;
 983                 /* This value must be overridden by the board. */
 984                 clock-frequency = <0>;
 985         };
 986 };