2 * This file is dual-licensed: you can use it either under the terms
3 * of the GPL or the X11 license, at your option. Note that this dual
4 * licensing only applies to this file, and not this project as a
7 * a) This file is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of the
10 * License, or (at your option) any later version.
12 * This file is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 * b) Permission is hereby granted, free of charge, to any person
20 * obtaining a copy of this software and associated documentation
21 * files (the "Software"), to deal in the Software without
22 * restriction, including without limitation the rights to use,
23 * copy, modify, merge, publish, distribute, sublicense, and/or
24 * sell copies of the Software, and to permit persons to whom the
25 * Software is furnished to do so, subject to the following
28 * The above copyright notice and this permission notice shall be
29 * included in all copies or substantial portions of the Software.
31 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
32 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
33 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
34 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
35 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
36 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
37 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
38 * OTHER DEALINGS IN THE SOFTWARE.
41 #include <dt-bindings/gpio/gpio.h>
42 #include <dt-bindings/interrupt-controller/irq.h>
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/pinctrl/rockchip.h>
45 #include <dt-bindings/clock/rk3036-cru.h>
46 #include <dt-bindings/soc/rockchip,boot-mode.h>
47 #include "skeleton.dtsi"
50 compatible = "rockchip,rk3036";
52 interrupt-parent = <&gic>;
70 enable-method = "rockchip,rk3036-smp";
74 compatible = "arm,cortex-a7";
76 resets = <&cru SRST_CORE0>;
81 clock-latency = <40000>;
82 clocks = <&cru ARMCLK>;
87 compatible = "arm,cortex-a7";
89 resets = <&cru SRST_CORE1>;
94 compatible = "simple-bus";
100 compatible = "arm,pl330", "arm,primecell";
101 reg = <0x20078000 0x4000>;
102 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
103 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
105 arm,pl330-broken-no-flushp;
106 clocks = <&cru ACLK_DMAC2>;
107 clock-names = "apb_pclk";
112 compatible = "arm,cortex-a7-pmu";
113 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
114 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
115 interrupt-affinity = <&cpu0>, <&cpu1>;
119 compatible = "rockchip,display-subsystem";
124 compatible = "arm,armv7-timer";
125 arm,cpu-registers-not-fw-configured;
126 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
127 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
128 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
129 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
130 clock-frequency = <24000000>;
134 compatible = "fixed-clock";
135 clock-frequency = <24000000>;
136 clock-output-names = "xin24m";
140 bus_intmem@10080000 {
141 compatible = "mmio-sram";
142 reg = <0x10080000 0x2000>;
143 #address-cells = <1>;
145 ranges = <0 0x10080000 0x2000>;
148 compatible = "rockchip,rk3066-smp-sram";
154 compatible = "rockchip,rk3036-vop";
155 reg = <0x10118000 0x19c>;
156 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
157 clocks = <&cru ACLK_LCDC>, <&cru SCLK_LCDC>, <&cru HCLK_LCDC>;
158 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
159 resets = <&cru SRST_LCDC1_A>, <&cru SRST_LCDC1_H>, <&cru SRST_LCDC1_D>;
160 reset-names = "axi", "ahb", "dclk";
165 #address-cells = <1>;
167 vop_out_hdmi: endpoint@0 {
169 remote-endpoint = <&hdmi_in_vop>;
174 vop_mmu: iommu@10118300 {
175 compatible = "rockchip,iommu";
176 reg = <0x10118300 0x100>;
177 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
178 interrupt-names = "vop_mmu";
183 gic: interrupt-controller@10139000 {
184 compatible = "arm,gic-400";
185 interrupt-controller;
186 #interrupt-cells = <3>;
187 #address-cells = <0>;
189 reg = <0x10139000 0x1000>,
193 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
196 usb_otg: usb@10180000 {
197 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
199 reg = <0x10180000 0x40000>;
200 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
201 clocks = <&cru HCLK_OTG0>;
204 g-np-tx-fifo-size = <16>;
205 g-rx-fifo-size = <275>;
206 g-tx-fifo-size = <256 128 128 64 64 32>;
210 usb_host: usb@101c0000 {
211 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
213 reg = <0x101c0000 0x40000>;
214 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
215 clocks = <&cru HCLK_OTG1>;
221 emac: ethernet@10200000 {
222 compatible = "rockchip,rk3036-emac", "snps,arc-emac";
223 reg = <0x10200000 0x4000>;
224 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
225 #address-cells = <1>;
227 rockchip,grf = <&grf>;
228 clocks = <&cru HCLK_MAC>, <&cru SCLK_MACREF>, <&cru SCLK_MAC>;
229 clock-names = "hclk", "macref", "macclk";
231 * Fix the emac parent clock is DPLL instead of APLL.
232 * since that will cause some unstable things if the cpufreq
233 * is working. (e.g: the accurate 50MHz what mac_ref need)
235 assigned-clocks = <&cru SCLK_MACPLL>;
236 assigned-clock-parents = <&cru PLL_DPLL>;
242 sdmmc: dwmmc@10214000 {
243 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
244 reg = <0x10214000 0x4000>;
245 clock-frequency = <37500000>;
246 clock-freq-min-max = <400000 37500000>;
247 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
248 clock-names = "biu", "ciu";
249 fifo-depth = <0x100>;
250 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
254 sdio: dwmmc@10218000 {
255 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
256 reg = <0x10218000 0x4000>;
257 clock-freq-min-max = <400000 37500000>;
258 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
259 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
260 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
261 fifo-depth = <0x100>;
262 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
266 emmc: dwmmc@1021c000 {
267 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
268 reg = <0x1021c000 0x4000>;
269 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
272 clock-frequency = <37500000>;
273 clock-freq-min-max = <400000 37500000>;
274 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
275 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
276 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
277 default-sample-phase = <158>;
281 fifo-depth = <0x100>;
285 pinctrl-names = "default";
286 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
291 compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s";
292 reg = <0x10220000 0x4000>;
293 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
294 #address-cells = <1>;
296 clock-names = "i2s_clk", "i2s_hclk";
297 clocks = <&cru SCLK_I2S>, <&cru HCLK_I2S>;
298 dmas = <&pdma 0>, <&pdma 1>;
299 dma-names = "tx", "rx";
300 pinctrl-names = "default";
301 pinctrl-0 = <&i2s_bus>;
305 cru: clock-controller@20000000 {
306 compatible = "rockchip,rk3036-cru";
307 reg = <0x20000000 0x1000>;
308 rockchip,grf = <&grf>;
311 assigned-clocks = <&cru PLL_GPLL>;
312 assigned-clock-rates = <594000000>;
315 grf: syscon@20008000 {
316 compatible = "rockchip,rk3036-grf", "syscon", "simple-mfd";
317 reg = <0x20008000 0x1000>;
320 compatible = "syscon-reboot-mode";
322 mode-normal = <BOOT_NORMAL>;
323 mode-recovery = <BOOT_RECOVERY>;
324 mode-bootloader = <BOOT_FASTBOOT>;
325 mode-loader = <BOOT_BL_DOWNLOAD>;
329 acodec: acodec-ana@20030000 {
330 compatible = "rk3036-codec";
331 reg = <0x20030000 0x4000>;
332 rockchip,grf = <&grf>;
333 clock-names = "acodec_pclk";
334 clocks = <&cru PCLK_ACODEC>;
338 hdmi: hdmi@20034000 {
339 compatible = "rockchip,rk3036-inno-hdmi";
340 reg = <0x20034000 0x4000>;
341 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
342 clocks = <&cru PCLK_HDMI>;
343 clock-names = "pclk";
344 rockchip,grf = <&grf>;
345 pinctrl-names = "default";
346 pinctrl-0 = <&hdmi_ctl>;
350 #address-cells = <1>;
352 hdmi_in_vop: endpoint@0 {
354 remote-endpoint = <&vop_out_hdmi>;
359 timer: timer@20044000 {
360 compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer";
361 reg = <0x20044000 0x20>;
362 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
363 clocks = <&xin24m>, <&cru PCLK_TIMER>;
364 clock-names = "timer", "pclk";
368 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
369 reg = <0x20050000 0x10>;
371 clocks = <&cru PCLK_PWM>;
373 pinctrl-names = "default";
374 pinctrl-0 = <&pwm0_pin>;
379 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
380 reg = <0x20050010 0x10>;
382 clocks = <&cru PCLK_PWM>;
384 pinctrl-names = "default";
385 pinctrl-0 = <&pwm1_pin>;
390 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
391 reg = <0x20050020 0x10>;
393 clocks = <&cru PCLK_PWM>;
395 pinctrl-names = "default";
396 pinctrl-0 = <&pwm2_pin>;
401 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
402 reg = <0x20050030 0x10>;
404 clocks = <&cru PCLK_PWM>;
406 pinctrl-names = "default";
407 pinctrl-0 = <&pwm3_pin>;
412 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
413 reg = <0x20056000 0x1000>;
414 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
415 #address-cells = <1>;
418 clocks = <&cru PCLK_I2C1>;
419 pinctrl-names = "default";
420 pinctrl-0 = <&i2c1_xfer>;
425 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
426 reg = <0x2005a000 0x1000>;
427 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
428 #address-cells = <1>;
431 clocks = <&cru PCLK_I2C2>;
432 pinctrl-names = "default";
433 pinctrl-0 = <&i2c2_xfer>;
437 uart0: serial@20060000 {
438 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
439 reg = <0x20060000 0x100>;
440 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
443 clock-frequency = <24000000>;
444 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
445 clock-names = "baudclk", "apb_pclk";
446 pinctrl-names = "default";
447 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
451 uart1: serial@20064000 {
452 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
453 reg = <0x20064000 0x100>;
454 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
457 clock-frequency = <24000000>;
458 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
459 clock-names = "baudclk", "apb_pclk";
460 pinctrl-names = "default";
461 pinctrl-0 = <&uart1_xfer>;
465 uart2: serial@20068000 {
466 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
467 reg = <0x20068000 0x100>;
468 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
471 clock-frequency = <24000000>;
472 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
473 clock-names = "baudclk", "apb_pclk";
474 pinctrl-names = "default";
475 pinctrl-0 = <&uart2_xfer>;
480 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
481 reg = <0x20072000 0x1000>;
482 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
483 #address-cells = <1>;
486 clocks = <&cru PCLK_I2C0>;
487 pinctrl-names = "default";
488 pinctrl-0 = <&i2c0_xfer>;
493 compatible = "rockchip,rockchip-spi";
494 reg = <0x20074000 0x1000>;
495 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
496 clocks =<&cru PCLK_SPI>, <&cru SCLK_SPI>;
497 clock-names = "apb-pclk","spi_pclk";
498 dmas = <&pdma 8>, <&pdma 9>;
499 dma-names = "tx", "rx";
500 pinctrl-names = "default";
501 pinctrl-0 = <&spi_txd &spi_rxd &spi_clk &spi_cs0>;
502 #address-cells = <1>;
508 compatible = "rockchip,rk3036-pinctrl";
509 rockchip,grf = <&grf>;
510 #address-cells = <1>;
514 gpio0: gpio0@2007c000 {
515 compatible = "rockchip,gpio-bank";
516 reg = <0x2007c000 0x100>;
517 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
518 clocks = <&cru PCLK_GPIO0>;
523 interrupt-controller;
524 #interrupt-cells = <2>;
527 gpio1: gpio1@20080000 {
528 compatible = "rockchip,gpio-bank";
529 reg = <0x20080000 0x100>;
530 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
531 clocks = <&cru PCLK_GPIO1>;
536 interrupt-controller;
537 #interrupt-cells = <2>;
540 gpio2: gpio2@20084000 {
541 compatible = "rockchip,gpio-bank";
542 reg = <0x20084000 0x100>;
543 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
544 clocks = <&cru PCLK_GPIO2>;
549 interrupt-controller;
550 #interrupt-cells = <2>;
553 pcfg_pull_default: pcfg_pull_default {
554 bias-pull-pin-default;
557 pcfg_pull_none: pcfg-pull-none {
563 rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
569 rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>;
575 rockchip,pins = <0 1 2 &pcfg_pull_none>;
581 rockchip,pins = <0 27 1 &pcfg_pull_none>;
586 sdmmc_clk: sdmmc-clk {
587 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>;
590 sdmmc_cmd: sdmmc-cmd {
591 rockchip,pins = <1 15 RK_FUNC_1 &pcfg_pull_default>;
595 rockchip,pins = <1 17 RK_FUNC_1 &pcfg_pull_default>;
598 sdmmc_bus1: sdmmc-bus1 {
599 rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_default>;
602 sdmmc_bus4: sdmmc-bus4 {
603 rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_default>,
604 <1 19 RK_FUNC_1 &pcfg_pull_default>,
605 <1 20 RK_FUNC_1 &pcfg_pull_default>,
606 <1 21 RK_FUNC_1 &pcfg_pull_default>;
611 sdio_bus1: sdio-bus1 {
612 rockchip,pins = <0 11 RK_FUNC_1 &pcfg_pull_default>;
615 sdio_bus4: sdio-bus4 {
616 rockchip,pins = <0 11 RK_FUNC_1 &pcfg_pull_default>,
617 <0 12 RK_FUNC_1 &pcfg_pull_default>,
618 <0 13 RK_FUNC_1 &pcfg_pull_default>,
619 <0 14 RK_FUNC_1 &pcfg_pull_default>;
623 rockchip,pins = <0 8 RK_FUNC_1 &pcfg_pull_default>;
627 rockchip,pins = <0 9 RK_FUNC_1 &pcfg_pull_none>;
633 * We run eMMC at max speed; bump up drive strength.
634 * We also have external pulls, so disable the internal ones.
637 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
641 rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_default>;
644 emmc_bus8: emmc-bus8 {
645 rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_default>,
646 <1 25 RK_FUNC_2 &pcfg_pull_default>,
647 <1 26 RK_FUNC_2 &pcfg_pull_default>,
648 <1 27 RK_FUNC_2 &pcfg_pull_default>,
649 <1 28 RK_FUNC_2 &pcfg_pull_default>,
650 <1 29 RK_FUNC_2 &pcfg_pull_default>,
651 <1 30 RK_FUNC_2 &pcfg_pull_default>,
652 <1 31 RK_FUNC_2 &pcfg_pull_default>;
657 emac_xfer: emac-xfer {
658 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_default>, /* crs_dvalid */
659 <2 13 RK_FUNC_1 &pcfg_pull_default>, /* tx_en */
660 <2 14 RK_FUNC_1 &pcfg_pull_default>, /* mac_clk */
661 <2 15 RK_FUNC_1 &pcfg_pull_default>, /* rx_err */
662 <2 16 RK_FUNC_1 &pcfg_pull_default>, /* rxd1 */
663 <2 17 RK_FUNC_1 &pcfg_pull_default>, /* rxd0 */
664 <2 18 RK_FUNC_1 &pcfg_pull_default>, /* txd1 */
665 <2 19 RK_FUNC_1 &pcfg_pull_default>; /* txd0 */
668 emac_mdio: emac-mdio {
669 rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_default>, /* mac_md */
670 <2 25 RK_FUNC_1 &pcfg_pull_default>; /* mac_mdclk */
675 i2c0_xfer: i2c0-xfer {
676 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>,
677 <0 1 RK_FUNC_1 &pcfg_pull_none>;
682 i2c1_xfer: i2c1-xfer {
683 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>,
684 <0 3 RK_FUNC_1 &pcfg_pull_none>;
689 i2c2_xfer: i2c2-xfer {
690 rockchip,pins = <2 20 RK_FUNC_1 &pcfg_pull_none>,
691 <2 21 RK_FUNC_1 &pcfg_pull_none>;
697 rockchip,pins = <1 0 RK_FUNC_1 &pcfg_pull_default>,
698 <1 1 RK_FUNC_1 &pcfg_pull_default>,
699 <1 2 RK_FUNC_1 &pcfg_pull_default>,
700 <1 3 RK_FUNC_1 &pcfg_pull_default>,
701 <1 4 RK_FUNC_1 &pcfg_pull_default>,
702 <1 5 RK_FUNC_1 &pcfg_pull_default>;
708 rockchip,pins = <1 8 RK_FUNC_1 &pcfg_pull_none>,
709 <1 9 RK_FUNC_1 &pcfg_pull_none>,
710 <1 10 RK_FUNC_1 &pcfg_pull_none>,
711 <1 11 RK_FUNC_1 &pcfg_pull_none>;
716 uart0_xfer: uart0-xfer {
717 rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_default>,
718 <0 17 RK_FUNC_1 &pcfg_pull_none>;
721 uart0_cts: uart0-cts {
722 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_default>;
725 uart0_rts: uart0-rts {
726 rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>;
731 uart1_xfer: uart1-xfer {
732 rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_default>,
733 <2 23 RK_FUNC_1 &pcfg_pull_none>;
735 /* no rts / cts for uart1 */
739 uart2_xfer: uart2-xfer {
740 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_default>,
741 <1 19 RK_FUNC_2 &pcfg_pull_none>;
743 /* no rts / cts for uart2 */
748 rockchip,pins = <1 29 RK_FUNC_3 &pcfg_pull_default>;
752 rockchip,pins = <1 28 RK_FUNC_3 &pcfg_pull_default>;
756 rockchip,pins = <2 0 RK_FUNC_2 &pcfg_pull_default>;
760 rockchip,pins = <1 30 RK_FUNC_3 &pcfg_pull_default>;
765 rockchip,pins = <1 31 RK_FUNC_3 &pcfg_pull_default>;