arch/arm/boot/dts/rk3188.dtsi

   1 /*
   2  * Copyright (c) 2013 MundoReader S.L.
   3  * Author: Heiko Stuebner <heiko@sntech.de>
   4  *
   5  * This file is dual-licensed: you can use it either under the terms
   6  * of the GPL or the X11 license, at your option. Note that this dual
   7  * licensing only applies to this file, and not this project as a
   8  * whole.
   9  *
  10  *  a) This file is free software; you can redistribute it and/or
  11  *     modify it under the terms of the GNU General Public License as
  12  *     published by the Free Software Foundation; either version 2 of the
  13  *     License, or (at your option) any later version.
  14  *
  15  *     This file is distributed in the hope that it will be useful,
  16  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *     GNU General Public License for more details.
  19  *
  20  * Or, alternatively,
  21  *
  22  *  b) Permission is hereby granted, free of charge, to any person
  23  *     obtaining a copy of this software and associated documentation
  24  *     files (the "Software"), to deal in the Software without
  25  *     restriction, including without limitation the rights to use,
  26  *     copy, modify, merge, publish, distribute, sublicense, and/or
  27  *     sell copies of the Software, and to permit persons to whom the
  28  *     Software is furnished to do so, subject to the following
  29  *     conditions:
  30  *
  31  *     The above copyright notice and this permission notice shall be
  32  *     included in all copies or substantial portions of the Software.
  33  *
  34  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  35  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  36  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  37  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  38  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  39  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  40  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  41  *     OTHER DEALINGS IN THE SOFTWARE.
  42  */
  43
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/pinctrl/rockchip.h>
  46 #include <dt-bindings/clock/rk3188-cru.h>
  47 #include "rk3xxx.dtsi"
  48
  49 / {
  50         compatible = "rockchip,rk3188";
  51
  52         cpus {
  53                 #address-cells = <1>;
  54                 #size-cells = <0>;
  55                 enable-method = "rockchip,rk3066-smp";
  56
  57                 cpu0: cpu@0 {
  58                         device_type = "cpu";
  59                         compatible = "arm,cortex-a9";
  60                         next-level-cache = <&L2>;
  61                         reg = <0x0>;
  62                         operating-points = <
  63                                 /* kHz    uV */
  64                                 1608000 1350000
  65                                 1416000 1250000
  66                                 1200000 1150000
  67                                 1008000 1075000
  68                                  816000  975000
  69                                  600000  950000
  70                                  504000  925000
  71                                  312000  875000
  72                         >;
  73                         clock-latency = <40000>;
  74                         clocks = <&cru ARMCLK>;
  75                 };
  76                 cpu@1 {
  77                         device_type = "cpu";
  78                         compatible = "arm,cortex-a9";
  79                         next-level-cache = <&L2>;
  80                         reg = <0x1>;
  81                 };
  82                 cpu@2 {
  83                         device_type = "cpu";
  84                         compatible = "arm,cortex-a9";
  85                         next-level-cache = <&L2>;
  86                         reg = <0x2>;
  87                 };
  88                 cpu@3 {
  89                         device_type = "cpu";
  90                         compatible = "arm,cortex-a9";
  91                         next-level-cache = <&L2>;
  92                         reg = <0x3>;
  93                 };
  94         };
  95
  96         sram: sram@10080000 {
  97                 compatible = "mmio-sram";
  98                 reg = <0x10080000 0x8000>;
  99                 #address-cells = <1>;
 100                 #size-cells = <1>;
 101                 ranges = <0 0x10080000 0x8000>;
 102
 103                 smp-sram@0 {
 104                         compatible = "rockchip,rk3066-smp-sram";
 105                         reg = <0x0 0x50>;
 106                 };
 107         };
 108
 109         i2s0: i2s@1011a000 {
 110                 compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s";
 111                 reg = <0x1011a000 0x2000>;
 112                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 113                 #address-cells = <1>;
 114                 #size-cells = <0>;
 115                 pinctrl-names = "default";
 116                 pinctrl-0 = <&i2s0_bus>;
 117                 dmas = <&dmac1_s 6>, <&dmac1_s 7>;
 118                 dma-names = "tx", "rx";
 119                 clock-names = "i2s_hclk", "i2s_clk";
 120                 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
 121                 rockchip,playback-channels = <2>;
 122                 rockchip,capture-channels = <2>;
 123                 status = "disabled";
 124         };
 125
 126         spdif: sound@1011e000 {
 127                 compatible = "rockchip,rk3188-spdif", "rockchip,rk3066-spdif";
 128                 reg = <0x1011e000 0x2000>;
 129                 #sound-dai-cells = <0>;
 130                 clock-names = "hclk", "mclk";
 131                 clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF>;
 132                 dmas = <&dmac1_s 8>;
 133                 dma-names = "tx";
 134                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 135                 pinctrl-names = "default";
 136                 pinctrl-0 = <&spdif_tx>;
 137                 status = "disabled";
 138         };
 139
 140         cru: clock-controller@20000000 {
 141                 compatible = "rockchip,rk3188-cru";
 142                 reg = <0x20000000 0x1000>;
 143                 rockchip,grf = <&grf>;
 144
 145                 #clock-cells = <1>;
 146                 #reset-cells = <1>;
 147         };
 148
 149         efuse: efuse@20010000 {
 150                 compatible = "rockchip,rockchip-efuse";
 151                 reg = <0x20010000 0x4000>;
 152                 #address-cells = <1>;
 153                 #size-cells = <1>;
 154                 clocks = <&cru PCLK_EFUSE>;
 155                 clock-names = "pclk_efuse";
 156
 157                 cpu_leakage: cpu_leakage {
 158                         reg = <0x17 0x1>;
 159                 };
 160         };
 161
 162         usbphy: phy {
 163                 compatible = "rockchip,rk3188-usb-phy", "rockchip,rk3288-usb-phy";
 164                 rockchip,grf = <&grf>;
 165                 #address-cells = <1>;
 166                 #size-cells = <0>;
 167                 status = "disabled";
 168
 169                 usbphy0: usb-phy0 {
 170                         #phy-cells = <0>;
 171                         reg = <0x10c>;
 172                         clocks = <&cru SCLK_OTGPHY0>;
 173                         clock-names = "phyclk";
 174                 };
 175
 176                 usbphy1: usb-phy1 {
 177                         #phy-cells = <0>;
 178                         reg = <0x11c>;
 179                         clocks = <&cru SCLK_OTGPHY1>;
 180                         clock-names = "phyclk";
 181                 };
 182         };
 183
 184         pinctrl: pinctrl {
 185                 compatible = "rockchip,rk3188-pinctrl";
 186                 rockchip,grf = <&grf>;
 187                 rockchip,pmu = <&pmu>;
 188
 189                 #address-cells = <1>;
 190                 #size-cells = <1>;
 191                 ranges;
 192
 193                 gpio0: gpio0@2000a000 {
 194                         compatible = "rockchip,rk3188-gpio-bank0";
 195                         reg = <0x2000a000 0x100>;
 196                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 197                         clocks = <&cru PCLK_GPIO0>;
 198
 199                         gpio-controller;
 200                         #gpio-cells = <2>;
 201
 202                         interrupt-controller;
 203                         #interrupt-cells = <2>;
 204                 };
 205
 206                 gpio1: gpio1@2003c000 {
 207                         compatible = "rockchip,gpio-bank";
 208                         reg = <0x2003c000 0x100>;
 209                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 210                         clocks = <&cru PCLK_GPIO1>;
 211
 212                         gpio-controller;
 213                         #gpio-cells = <2>;
 214
 215                         interrupt-controller;
 216                         #interrupt-cells = <2>;
 217                 };
 218
 219                 gpio2: gpio2@2003e000 {
 220                         compatible = "rockchip,gpio-bank";
 221                         reg = <0x2003e000 0x100>;
 222                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 223                         clocks = <&cru PCLK_GPIO2>;
 224
 225                         gpio-controller;
 226                         #gpio-cells = <2>;
 227
 228                         interrupt-controller;
 229                         #interrupt-cells = <2>;
 230                 };
 231
 232                 gpio3: gpio3@20080000 {
 233                         compatible = "rockchip,gpio-bank";
 234                         reg = <0x20080000 0x100>;
 235                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 236                         clocks = <&cru PCLK_GPIO3>;
 237
 238                         gpio-controller;
 239                         #gpio-cells = <2>;
 240
 241                         interrupt-controller;
 242                         #interrupt-cells = <2>;
 243                 };
 244
 245                 pcfg_pull_up: pcfg_pull_up {
 246                         bias-pull-up;
 247                 };
 248
 249                 pcfg_pull_down: pcfg_pull_down {
 250                         bias-pull-down;
 251                 };
 252
 253                 pcfg_pull_none: pcfg_pull_none {
 254                         bias-disable;
 255                 };
 256
 257                 emmc {
 258                         emmc_clk: emmc-clk {
 259                                 rockchip,pins = <RK_GPIO0 24 RK_FUNC_2 &pcfg_pull_none>;
 260                         };
 261
 262                         emmc_cmd: emmc-cmd {
 263                                 rockchip,pins = <RK_GPIO0 26 RK_FUNC_2 &pcfg_pull_up>;
 264                         };
 265
 266                         emmc_rst: emmc-rst {
 267                                 rockchip,pins = <RK_GPIO0 27 RK_FUNC_2 &pcfg_pull_none>;
 268                         };
 269
 270                         /*
 271                          * The data pins are shared between nandc and emmc and
 272                          * not accessible through pinctrl. Also they should've
 273                          * been already set correctly by firmware, as
 274                          * flash/emmc is the boot-device.
 275                          */
 276                 };
 277
 278                 emac {
 279                         emac_xfer: emac-xfer {
 280                                 rockchip,pins = <RK_GPIO3 16 RK_FUNC_2 &pcfg_pull_none>, /* tx_en */
 281                                                 <RK_GPIO3 17 RK_FUNC_2 &pcfg_pull_none>, /* txd1 */
 282                                                 <RK_GPIO3 18 RK_FUNC_2 &pcfg_pull_none>, /* txd0 */
 283                                                 <RK_GPIO3 19 RK_FUNC_2 &pcfg_pull_none>, /* rxd0 */
 284                                                 <RK_GPIO3 20 RK_FUNC_2 &pcfg_pull_none>, /* rxd1 */
 285                                                 <RK_GPIO3 21 RK_FUNC_2 &pcfg_pull_none>, /* mac_clk */
 286                                                 <RK_GPIO3 22 RK_FUNC_2 &pcfg_pull_none>, /* rx_err */
 287                                                 <RK_GPIO3 23 RK_FUNC_2 &pcfg_pull_none>; /* crs_dvalid */
 288                         };
 289
 290                         emac_mdio: emac-mdio {
 291                                 rockchip,pins = <RK_GPIO3 24 RK_FUNC_2 &pcfg_pull_none>,
 292                                                 <RK_GPIO3 25 RK_FUNC_2 &pcfg_pull_none>;
 293                         };
 294                 };
 295
 296                 i2c0 {
 297                         i2c0_xfer: i2c0-xfer {
 298                                 rockchip,pins = <RK_GPIO1 24 RK_FUNC_1 &pcfg_pull_none>,
 299                                                 <RK_GPIO1 25 RK_FUNC_1 &pcfg_pull_none>;
 300                         };
 301                 };
 302
 303                 i2c1 {
 304                         i2c1_xfer: i2c1-xfer {
 305                                 rockchip,pins = <RK_GPIO1 26 RK_FUNC_1 &pcfg_pull_none>,
 306                                                 <RK_GPIO1 27 RK_FUNC_1 &pcfg_pull_none>;
 307                         };
 308                 };
 309
 310                 i2c2 {
 311                         i2c2_xfer: i2c2-xfer {
 312                                 rockchip,pins = <RK_GPIO1 28 RK_FUNC_1 &pcfg_pull_none>,
 313                                                 <RK_GPIO1 29 RK_FUNC_1 &pcfg_pull_none>;
 314                         };
 315                 };
 316
 317                 i2c3 {
 318                         i2c3_xfer: i2c3-xfer {
 319                                 rockchip,pins = <RK_GPIO3 14 RK_FUNC_2 &pcfg_pull_none>,
 320                                                 <RK_GPIO3 15 RK_FUNC_2 &pcfg_pull_none>;
 321                         };
 322                 };
 323
 324                 i2c4 {
 325                         i2c4_xfer: i2c4-xfer {
 326                                 rockchip,pins = <RK_GPIO1 30 RK_FUNC_1 &pcfg_pull_none>,
 327                                                 <RK_GPIO1 31 RK_FUNC_1 &pcfg_pull_none>;
 328                         };
 329                 };
 330
 331                 pwm0 {
 332                         pwm0_out: pwm0-out {
 333                                 rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_none>;
 334                         };
 335                 };
 336
 337                 pwm1 {
 338                         pwm1_out: pwm1-out {
 339                                 rockchip,pins = <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_none>;
 340                         };
 341                 };
 342
 343                 pwm2 {
 344                         pwm2_out: pwm2-out {
 345                                 rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_none>;
 346                         };
 347                 };
 348
 349                 pwm3 {
 350                         pwm3_out: pwm3-out {
 351                                 rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_none>;
 352                         };
 353                 };
 354
 355                 spi0 {
 356                         spi0_clk: spi0-clk {
 357                                 rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_up>;
 358                         };
 359                         spi0_cs0: spi0-cs0 {
 360                                 rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_up>;
 361                         };
 362                         spi0_tx: spi0-tx {
 363                                 rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_up>;
 364                         };
 365                         spi0_rx: spi0-rx {
 366                                 rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_up>;
 367                         };
 368                         spi0_cs1: spi0-cs1 {
 369                                 rockchip,pins = <RK_GPIO1 15 RK_FUNC_1 &pcfg_pull_up>;
 370                         };
 371                 };
 372
 373                 spi1 {
 374                         spi1_clk: spi1-clk {
 375                                 rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_up>;
 376                         };
 377                         spi1_cs0: spi1-cs0 {
 378                                 rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_up>;
 379                         };
 380                         spi1_rx: spi1-rx {
 381                                 rockchip,pins = <RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_up>;
 382                         };
 383                         spi1_tx: spi1-tx {
 384                                 rockchip,pins = <RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_up>;
 385                         };
 386                         spi1_cs1: spi1-cs1 {
 387                                 rockchip,pins = <RK_GPIO1 14 RK_FUNC_2 &pcfg_pull_up>;
 388                         };
 389                 };
 390
 391                 uart0 {
 392                         uart0_xfer: uart0-xfer {
 393                                 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>,
 394                                                 <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>;
 395                         };
 396
 397                         uart0_cts: uart0-cts {
 398                                 rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_none>;
 399                         };
 400
 401                         uart0_rts: uart0-rts {
 402                                 rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_none>;
 403                         };
 404                 };
 405
 406                 uart1 {
 407                         uart1_xfer: uart1-xfer {
 408                                 rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_up>,
 409                                                 <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>;
 410                         };
 411
 412                         uart1_cts: uart1-cts {
 413                                 rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_none>;
 414                         };
 415
 416                         uart1_rts: uart1-rts {
 417                                 rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_none>;
 418                         };
 419                 };
 420
 421                 uart2 {
 422                         uart2_xfer: uart2-xfer {
 423                                 rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_up>,
 424                                                 <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>;
 425                         };
 426                         /* no rts / cts for uart2 */
 427                 };
 428
 429                 uart3 {
 430                         uart3_xfer: uart3-xfer {
 431                                 rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_up>,
 432                                                 <RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>;
 433                         };
 434
 435                         uart3_cts: uart3-cts {
 436                                 rockchip,pins = <RK_GPIO1 12 RK_FUNC_1 &pcfg_pull_none>;
 437                         };
 438
 439                         uart3_rts: uart3-rts {
 440                                 rockchip,pins = <RK_GPIO1 13 RK_FUNC_1 &pcfg_pull_none>;
 441                         };
 442                 };
 443
 444                 sd0 {
 445                         sd0_clk: sd0-clk {
 446                                 rockchip,pins = <RK_GPIO3 2 RK_FUNC_1 &pcfg_pull_none>;
 447                         };
 448
 449                         sd0_cmd: sd0-cmd {
 450                                 rockchip,pins = <RK_GPIO3 3 RK_FUNC_1 &pcfg_pull_none>;
 451                         };
 452
 453                         sd0_cd: sd0-cd {
 454                                 rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_none>;
 455                         };
 456
 457                         sd0_wp: sd0-wp {
 458                                 rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_none>;
 459                         };
 460
 461                         sd0_pwr: sd0-pwr {
 462                                 rockchip,pins = <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
 463                         };
 464
 465                         sd0_bus1: sd0-bus-width1 {
 466                                 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>;
 467                         };
 468
 469                         sd0_bus4: sd0-bus-width4 {
 470                                 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
 471                                                 <RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>,
 472                                                 <RK_GPIO3 6 RK_FUNC_1 &pcfg_pull_none>,
 473                                                 <RK_GPIO3 7 RK_FUNC_1 &pcfg_pull_none>;
 474                         };
 475                 };
 476
 477                 sd1 {
 478                         sd1_clk: sd1-clk {
 479                                 rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_none>;
 480                         };
 481
 482                         sd1_cmd: sd1-cmd {
 483                                 rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_none>;
 484                         };
 485
 486                         sd1_cd: sd1-cd {
 487                                 rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_none>;
 488                         };
 489
 490                         sd1_wp: sd1-wp {
 491                                 rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_none>;
 492                         };
 493
 494                         sd1_bus1: sd1-bus-width1 {
 495                                 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>;
 496                         };
 497
 498                         sd1_bus4: sd1-bus-width4 {
 499                                 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>,
 500                                                 <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_none>,
 501                                                 <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_none>,
 502                                                 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>;
 503                         };
 504                 };
 505
 506                 i2s0 {
 507                         i2s0_bus: i2s0-bus {
 508                                 rockchip,pins = <RK_GPIO1 16 RK_FUNC_1 &pcfg_pull_none>,
 509                                                 <RK_GPIO1 17 RK_FUNC_1 &pcfg_pull_none>,
 510                                                 <RK_GPIO1 18 RK_FUNC_1 &pcfg_pull_none>,
 511                                                 <RK_GPIO1 19 RK_FUNC_1 &pcfg_pull_none>,
 512                                                 <RK_GPIO1 20 RK_FUNC_1 &pcfg_pull_none>,
 513                                                 <RK_GPIO1 21 RK_FUNC_1 &pcfg_pull_none>;
 514                         };
 515                 };
 516
 517                 spdif {
 518                         spdif_tx: spdif-tx {
 519                                 rockchip,pins = <RK_GPIO1 14 RK_FUNC_1 &pcfg_pull_none>;
 520                         };
 521                 };
 522         };
 523 };
 524
 525 &emac {
 526         compatible = "rockchip,rk3188-emac";
 527 };
 528
 529 &global_timer {
 530         interrupts = <GIC_PPI 11 0xf04>;
 531 };
 532
 533 &local_timer {
 534         interrupts = <GIC_PPI 13 0xf04>;
 535 };
 536
 537 &i2c0 {
 538         compatible = "rockchip,rk3188-i2c";
 539         pinctrl-names = "default";
 540         pinctrl-0 = <&i2c0_xfer>;
 541 };
 542
 543 &i2c1 {
 544         compatible = "rockchip,rk3188-i2c";
 545         pinctrl-names = "default";
 546         pinctrl-0 = <&i2c1_xfer>;
 547 };
 548
 549 &i2c2 {
 550         compatible = "rockchip,rk3188-i2c";
 551         pinctrl-names = "default";
 552         pinctrl-0 = <&i2c2_xfer>;
 553 };
 554
 555 &i2c3 {
 556         compatible = "rockchip,rk3188-i2c";
 557         pinctrl-names = "default";
 558         pinctrl-0 = <&i2c3_xfer>;
 559 };
 560
 561 &i2c4 {
 562         compatible = "rockchip,rk3188-i2c";
 563         pinctrl-names = "default";
 564         pinctrl-0 = <&i2c4_xfer>;
 565 };
 566
 567 &pwm0 {
 568         pinctrl-names = "default";
 569         pinctrl-0 = <&pwm0_out>;
 570 };
 571
 572 &pwm1 {
 573         pinctrl-names = "default";
 574         pinctrl-0 = <&pwm1_out>;
 575 };
 576
 577 &pwm2 {
 578         pinctrl-names = "default";
 579         pinctrl-0 = <&pwm2_out>;
 580 };
 581
 582 &pwm3 {
 583         pinctrl-names = "default";
 584         pinctrl-0 = <&pwm3_out>;
 585 };
 586
 587 &spi0 {
 588         compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
 589         pinctrl-names = "default";
 590         pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 591 };
 592
 593 &spi1 {
 594         compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
 595         pinctrl-names = "default";
 596         pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 597 };
 598
 599 &uart0 {
 600         pinctrl-names = "default";
 601         pinctrl-0 = <&uart0_xfer>;
 602 };
 603
 604 &uart1 {
 605         pinctrl-names = "default";
 606         pinctrl-0 = <&uart1_xfer>;
 607 };
 608
 609 &uart2 {
 610         pinctrl-names = "default";
 611         pinctrl-0 = <&uart2_xfer>;
 612 };
 613
 614 &uart3 {
 615         pinctrl-names = "default";
 616         pinctrl-0 = <&uart3_xfer>;
 617 };
 618
 619 &wdt {
 620         compatible = "rockchip,rk3188-wdt", "snps,dw-wdt";
 621 };