1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3228-cru.h>
8 #include <dt-bindings/thermal/thermal.h>
14 interrupt-parent = <&gic>;
29 compatible = "arm,cortex-a7";
31 resets = <&cru SRST_CORE0>;
32 operating-points-v2 = <&cpu0_opp_table>;
33 #cooling-cells = <2>; /* min followed by max */
34 clock-latency = <40000>;
35 clocks = <&cru ARMCLK>;
36 enable-method = "psci";
41 compatible = "arm,cortex-a7";
43 resets = <&cru SRST_CORE1>;
44 operating-points-v2 = <&cpu0_opp_table>;
45 #cooling-cells = <2>; /* min followed by max */
46 enable-method = "psci";
51 compatible = "arm,cortex-a7";
53 resets = <&cru SRST_CORE2>;
54 operating-points-v2 = <&cpu0_opp_table>;
55 #cooling-cells = <2>; /* min followed by max */
56 enable-method = "psci";
61 compatible = "arm,cortex-a7";
63 resets = <&cru SRST_CORE3>;
64 operating-points-v2 = <&cpu0_opp_table>;
65 #cooling-cells = <2>; /* min followed by max */
66 enable-method = "psci";
70 cpu0_opp_table: opp_table0 {
71 compatible = "operating-points-v2";
75 opp-hz = /bits/ 64 <408000000>;
76 opp-microvolt = <950000>;
77 clock-latency-ns = <40000>;
81 opp-hz = /bits/ 64 <600000000>;
82 opp-microvolt = <975000>;
85 opp-hz = /bits/ 64 <816000000>;
86 opp-microvolt = <1000000>;
89 opp-hz = /bits/ 64 <1008000000>;
90 opp-microvolt = <1175000>;
93 opp-hz = /bits/ 64 <1200000000>;
94 opp-microvolt = <1275000>;
99 compatible = "simple-bus";
100 #address-cells = <1>;
104 pdma: pdma@110f0000 {
105 compatible = "arm,pl330", "arm,primecell";
106 reg = <0x110f0000 0x4000>;
107 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
108 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
110 clocks = <&cru ACLK_DMAC>;
111 clock-names = "apb_pclk";
116 compatible = "arm,cortex-a7-pmu";
117 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
118 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
119 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
120 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
121 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
125 compatible = "arm,psci-1.0", "arm,psci-0.2";
130 compatible = "arm,armv7-timer";
131 arm,cpu-registers-not-fw-configured;
132 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
133 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
134 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
135 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
136 clock-frequency = <24000000>;
140 compatible = "fixed-clock";
141 clock-frequency = <24000000>;
142 clock-output-names = "xin24m";
146 i2s1: i2s1@100b0000 {
147 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
148 reg = <0x100b0000 0x4000>;
149 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
150 #address-cells = <1>;
152 clock-names = "i2s_clk", "i2s_hclk";
153 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
154 dmas = <&pdma 14>, <&pdma 15>;
155 dma-names = "tx", "rx";
156 pinctrl-names = "default";
157 pinctrl-0 = <&i2s1_bus>;
161 i2s0: i2s0@100c0000 {
162 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
163 reg = <0x100c0000 0x4000>;
164 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
165 #address-cells = <1>;
167 clock-names = "i2s_clk", "i2s_hclk";
168 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
169 dmas = <&pdma 11>, <&pdma 12>;
170 dma-names = "tx", "rx";
174 spdif: spdif@100d0000 {
175 compatible = "rockchip,rk3228-spdif";
176 reg = <0x100d0000 0x1000>;
177 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
178 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
179 clock-names = "mclk", "hclk";
182 pinctrl-names = "default";
183 pinctrl-0 = <&spdif_tx>;
187 i2s2: i2s2@100e0000 {
188 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
189 reg = <0x100e0000 0x4000>;
190 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
191 #address-cells = <1>;
193 clock-names = "i2s_clk", "i2s_hclk";
194 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
195 dmas = <&pdma 0>, <&pdma 1>;
196 dma-names = "tx", "rx";
200 grf: syscon@11000000 {
201 compatible = "rockchip,rk3228-grf", "syscon", "simple-mfd";
202 reg = <0x11000000 0x1000>;
203 #address-cells = <1>;
206 io_domains: io-domains {
207 compatible = "rockchip,rk3228-io-voltage-domain";
211 u2phy0: usb2-phy@760 {
212 compatible = "rockchip,rk3228-usb2phy";
214 clocks = <&cru SCLK_OTGPHY0>;
215 clock-names = "phyclk";
216 clock-output-names = "usb480m_phy0";
220 u2phy0_otg: otg-port {
221 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
222 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
223 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
224 interrupt-names = "otg-bvalid", "otg-id",
230 u2phy0_host: host-port {
231 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
232 interrupt-names = "linestate";
238 u2phy1: usb2-phy@800 {
239 compatible = "rockchip,rk3228-usb2phy";
241 clocks = <&cru SCLK_OTGPHY1>;
242 clock-names = "phyclk";
243 clock-output-names = "usb480m_phy1";
247 u2phy1_otg: otg-port {
248 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
249 interrupt-names = "linestate";
254 u2phy1_host: host-port {
255 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
256 interrupt-names = "linestate";
263 uart0: serial@11010000 {
264 compatible = "snps,dw-apb-uart";
265 reg = <0x11010000 0x100>;
266 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
267 clock-frequency = <24000000>;
268 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
269 clock-names = "baudclk", "apb_pclk";
270 pinctrl-names = "default";
271 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
277 uart1: serial@11020000 {
278 compatible = "snps,dw-apb-uart";
279 reg = <0x11020000 0x100>;
280 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
281 clock-frequency = <24000000>;
282 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
283 clock-names = "baudclk", "apb_pclk";
284 pinctrl-names = "default";
285 pinctrl-0 = <&uart1_xfer>;
291 uart2: serial@11030000 {
292 compatible = "snps,dw-apb-uart";
293 reg = <0x11030000 0x100>;
294 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
295 clock-frequency = <24000000>;
296 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
297 clock-names = "baudclk", "apb_pclk";
298 pinctrl-names = "default";
299 pinctrl-0 = <&uart2_xfer>;
305 efuse: efuse@11040000 {
306 compatible = "rockchip,rk3228-efuse";
307 reg = <0x11040000 0x20>;
308 clocks = <&cru PCLK_EFUSE_256>;
309 clock-names = "pclk_efuse";
310 #address-cells = <1>;
317 cpu_leakage: cpu_leakage@17 {
323 compatible = "rockchip,rk3228-i2c";
324 reg = <0x11050000 0x1000>;
325 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
326 #address-cells = <1>;
329 clocks = <&cru PCLK_I2C0>;
330 pinctrl-names = "default";
331 pinctrl-0 = <&i2c0_xfer>;
336 compatible = "rockchip,rk3228-i2c";
337 reg = <0x11060000 0x1000>;
338 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
339 #address-cells = <1>;
342 clocks = <&cru PCLK_I2C1>;
343 pinctrl-names = "default";
344 pinctrl-0 = <&i2c1_xfer>;
349 compatible = "rockchip,rk3228-i2c";
350 reg = <0x11070000 0x1000>;
351 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
352 #address-cells = <1>;
355 clocks = <&cru PCLK_I2C2>;
356 pinctrl-names = "default";
357 pinctrl-0 = <&i2c2_xfer>;
362 compatible = "rockchip,rk3228-i2c";
363 reg = <0x11080000 0x1000>;
364 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
365 #address-cells = <1>;
368 clocks = <&cru PCLK_I2C3>;
369 pinctrl-names = "default";
370 pinctrl-0 = <&i2c3_xfer>;
375 compatible = "rockchip,rk3228-spi";
376 reg = <0x11090000 0x1000>;
377 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
378 #address-cells = <1>;
380 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
381 clock-names = "spiclk", "apb_pclk";
382 pinctrl-names = "default";
383 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>;
387 wdt: watchdog@110a0000 {
388 compatible = "snps,dw-wdt";
389 reg = <0x110a0000 0x100>;
390 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
391 clocks = <&cru PCLK_CPU>;
396 compatible = "rockchip,rk3288-pwm";
397 reg = <0x110b0000 0x10>;
399 clocks = <&cru PCLK_PWM>;
401 pinctrl-names = "default";
402 pinctrl-0 = <&pwm0_pin>;
407 compatible = "rockchip,rk3288-pwm";
408 reg = <0x110b0010 0x10>;
410 clocks = <&cru PCLK_PWM>;
412 pinctrl-names = "default";
413 pinctrl-0 = <&pwm1_pin>;
418 compatible = "rockchip,rk3288-pwm";
419 reg = <0x110b0020 0x10>;
421 clocks = <&cru PCLK_PWM>;
423 pinctrl-names = "default";
424 pinctrl-0 = <&pwm2_pin>;
429 compatible = "rockchip,rk3288-pwm";
430 reg = <0x110b0030 0x10>;
432 clocks = <&cru PCLK_PWM>;
434 pinctrl-names = "default";
435 pinctrl-0 = <&pwm3_pin>;
439 timer: timer@110c0000 {
440 compatible = "rockchip,rk3228-timer", "rockchip,rk3288-timer";
441 reg = <0x110c0000 0x20>;
442 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
443 clocks = <&xin24m>, <&cru PCLK_TIMER>;
444 clock-names = "timer", "pclk";
447 cru: clock-controller@110e0000 {
448 compatible = "rockchip,rk3228-cru";
449 reg = <0x110e0000 0x1000>;
450 rockchip,grf = <&grf>;
454 <&cru PLL_GPLL>, <&cru ARMCLK>,
455 <&cru PLL_CPLL>, <&cru ACLK_PERI>,
456 <&cru HCLK_PERI>, <&cru PCLK_PERI>,
457 <&cru ACLK_CPU>, <&cru HCLK_CPU>,
459 assigned-clock-rates =
460 <594000000>, <816000000>,
461 <500000000>, <150000000>,
462 <150000000>, <75000000>,
463 <150000000>, <150000000>,
468 cpu_thermal: cpu-thermal {
469 polling-delay-passive = <100>; /* milliseconds */
470 polling-delay = <5000>; /* milliseconds */
472 thermal-sensors = <&tsadc 0>;
475 cpu_alert0: cpu_alert0 {
476 temperature = <70000>; /* millicelsius */
477 hysteresis = <2000>; /* millicelsius */
480 cpu_alert1: cpu_alert1 {
481 temperature = <75000>; /* millicelsius */
482 hysteresis = <2000>; /* millicelsius */
486 temperature = <90000>; /* millicelsius */
487 hysteresis = <2000>; /* millicelsius */
494 trip = <&cpu_alert0>;
496 <&cpu0 THERMAL_NO_LIMIT 6>,
497 <&cpu1 THERMAL_NO_LIMIT 6>,
498 <&cpu2 THERMAL_NO_LIMIT 6>,
499 <&cpu3 THERMAL_NO_LIMIT 6>;
502 trip = <&cpu_alert1>;
504 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
505 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
506 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
507 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
513 tsadc: tsadc@11150000 {
514 compatible = "rockchip,rk3228-tsadc";
515 reg = <0x11150000 0x100>;
516 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
517 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
518 clock-names = "tsadc", "apb_pclk";
519 assigned-clocks = <&cru SCLK_TSADC>;
520 assigned-clock-rates = <32768>;
521 resets = <&cru SRST_TSADC>;
522 reset-names = "tsadc-apb";
523 pinctrl-names = "init", "default", "sleep";
524 pinctrl-0 = <&otp_gpio>;
525 pinctrl-1 = <&otp_out>;
526 pinctrl-2 = <&otp_gpio>;
527 #thermal-sensor-cells = <0>;
528 rockchip,hw-tshut-temp = <95000>;
533 compatible = "rockchip,rk3228-mali", "arm,mali-400";
534 reg = <0x20000000 0x10000>;
535 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
536 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
537 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
538 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
539 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
540 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
541 interrupt-names = "gp",
547 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
548 clock-names = "core", "bus";
549 resets = <&cru SRST_GPU_A>;
553 vpu_mmu: iommu@20020800 {
554 compatible = "rockchip,iommu";
555 reg = <0x20020800 0x100>;
556 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
557 interrupt-names = "vpu_mmu";
558 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
559 clock-names = "aclk", "iface";
564 vdec_mmu: iommu@20030480 {
565 compatible = "rockchip,iommu";
566 reg = <0x20030480 0x40>, <0x200304c0 0x40>;
567 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
568 interrupt-names = "vdec_mmu";
569 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
570 clock-names = "aclk", "iface";
575 vop_mmu: iommu@20053f00 {
576 compatible = "rockchip,iommu";
577 reg = <0x20053f00 0x100>;
578 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
579 interrupt-names = "vop_mmu";
580 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
581 clock-names = "aclk", "iface";
586 iep_mmu: iommu@20070800 {
587 compatible = "rockchip,iommu";
588 reg = <0x20070800 0x100>;
589 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
590 interrupt-names = "iep_mmu";
591 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
592 clock-names = "aclk", "iface";
597 sdmmc: dwmmc@30000000 {
598 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
599 reg = <0x30000000 0x4000>;
600 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
601 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
602 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
603 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
604 fifo-depth = <0x100>;
605 pinctrl-names = "default";
606 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
610 sdio: dwmmc@30010000 {
611 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
612 reg = <0x30010000 0x4000>;
613 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
614 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
615 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
616 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
617 fifo-depth = <0x100>;
618 pinctrl-names = "default";
619 pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>;
623 emmc: dwmmc@30020000 {
624 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
625 reg = <0x30020000 0x4000>;
626 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
627 clock-frequency = <37500000>;
628 max-frequency = <37500000>;
629 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
630 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
631 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
633 default-sample-phase = <158>;
634 fifo-depth = <0x100>;
635 pinctrl-names = "default";
636 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
637 resets = <&cru SRST_EMMC>;
638 reset-names = "reset";
642 usb_otg: usb@30040000 {
643 compatible = "rockchip,rk3228-usb", "rockchip,rk3066-usb",
645 reg = <0x30040000 0x40000>;
646 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
647 clocks = <&cru HCLK_OTG>;
650 g-np-tx-fifo-size = <16>;
651 g-rx-fifo-size = <280>;
652 g-tx-fifo-size = <256 128 128 64 32 16>;
654 phys = <&u2phy0_otg>;
655 phy-names = "usb2-phy";
659 usb_host0_ehci: usb@30080000 {
660 compatible = "generic-ehci";
661 reg = <0x30080000 0x20000>;
662 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
663 clocks = <&cru HCLK_HOST0>, <&u2phy0>;
664 clock-names = "usbhost", "utmi";
665 phys = <&u2phy0_host>;
670 usb_host0_ohci: usb@300a0000 {
671 compatible = "generic-ohci";
672 reg = <0x300a0000 0x20000>;
673 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
674 clocks = <&cru HCLK_HOST0>, <&u2phy0>;
675 clock-names = "usbhost", "utmi";
676 phys = <&u2phy0_host>;
681 usb_host1_ehci: usb@300c0000 {
682 compatible = "generic-ehci";
683 reg = <0x300c0000 0x20000>;
684 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
685 clocks = <&cru HCLK_HOST1>, <&u2phy1>;
686 clock-names = "usbhost", "utmi";
687 phys = <&u2phy1_otg>;
692 usb_host1_ohci: usb@300e0000 {
693 compatible = "generic-ohci";
694 reg = <0x300e0000 0x20000>;
695 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
696 clocks = <&cru HCLK_HOST1>, <&u2phy1>;
697 clock-names = "usbhost", "utmi";
698 phys = <&u2phy1_otg>;
703 usb_host2_ehci: usb@30100000 {
704 compatible = "generic-ehci";
705 reg = <0x30100000 0x20000>;
706 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
707 clocks = <&cru HCLK_HOST2>, <&u2phy1>;
708 phys = <&u2phy1_host>;
710 clock-names = "usbhost", "utmi";
714 usb_host2_ohci: usb@30120000 {
715 compatible = "generic-ohci";
716 reg = <0x30120000 0x20000>;
717 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
718 clocks = <&cru HCLK_HOST2>, <&u2phy1>;
719 clock-names = "usbhost", "utmi";
720 phys = <&u2phy1_host>;
725 gmac: ethernet@30200000 {
726 compatible = "rockchip,rk3228-gmac";
727 reg = <0x30200000 0x10000>;
728 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
729 interrupt-names = "macirq";
730 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
731 <&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>,
732 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
734 clock-names = "stmmaceth", "mac_clk_rx",
735 "mac_clk_tx", "clk_mac_ref",
736 "clk_mac_refout", "aclk_mac",
738 resets = <&cru SRST_GMAC>;
739 reset-names = "stmmaceth";
740 rockchip,grf = <&grf>;
744 gic: interrupt-controller@32010000 {
745 compatible = "arm,gic-400";
746 interrupt-controller;
747 #interrupt-cells = <3>;
748 #address-cells = <0>;
750 reg = <0x32011000 0x1000>,
754 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
758 compatible = "rockchip,rk3228-pinctrl";
759 rockchip,grf = <&grf>;
760 #address-cells = <1>;
764 gpio0: gpio0@11110000 {
765 compatible = "rockchip,gpio-bank";
766 reg = <0x11110000 0x100>;
767 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
768 clocks = <&cru PCLK_GPIO0>;
773 interrupt-controller;
774 #interrupt-cells = <2>;
777 gpio1: gpio1@11120000 {
778 compatible = "rockchip,gpio-bank";
779 reg = <0x11120000 0x100>;
780 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
781 clocks = <&cru PCLK_GPIO1>;
786 interrupt-controller;
787 #interrupt-cells = <2>;
790 gpio2: gpio2@11130000 {
791 compatible = "rockchip,gpio-bank";
792 reg = <0x11130000 0x100>;
793 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
794 clocks = <&cru PCLK_GPIO2>;
799 interrupt-controller;
800 #interrupt-cells = <2>;
803 gpio3: gpio3@11140000 {
804 compatible = "rockchip,gpio-bank";
805 reg = <0x11140000 0x100>;
806 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
807 clocks = <&cru PCLK_GPIO3>;
812 interrupt-controller;
813 #interrupt-cells = <2>;
816 pcfg_pull_up: pcfg-pull-up {
820 pcfg_pull_down: pcfg-pull-down {
824 pcfg_pull_none: pcfg-pull-none {
828 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
829 drive-strength = <12>;
833 sdmmc_clk: sdmmc-clk {
834 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none_drv_12ma>;
837 sdmmc_cmd: sdmmc-cmd {
838 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_none_drv_12ma>;
841 sdmmc_bus4: sdmmc-bus4 {
842 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_none_drv_12ma>,
843 <1 RK_PC3 1 &pcfg_pull_none_drv_12ma>,
844 <1 RK_PC4 1 &pcfg_pull_none_drv_12ma>,
845 <1 RK_PC5 1 &pcfg_pull_none_drv_12ma>;
851 rockchip,pins = <3 RK_PA0 1 &pcfg_pull_none_drv_12ma>;
855 rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none_drv_12ma>;
858 sdio_bus4: sdio-bus4 {
859 rockchip,pins = <3 RK_PA2 1 &pcfg_pull_none_drv_12ma>,
860 <3 RK_PA3 1 &pcfg_pull_none_drv_12ma>,
861 <3 RK_PA4 1 &pcfg_pull_none_drv_12ma>,
862 <3 RK_PA5 1 &pcfg_pull_none_drv_12ma>;
868 rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>;
872 rockchip,pins = <1 RK_PC6 2 &pcfg_pull_none>;
875 emmc_bus8: emmc-bus8 {
876 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>,
877 <1 RK_PD1 2 &pcfg_pull_none>,
878 <1 RK_PD2 2 &pcfg_pull_none>,
879 <1 RK_PD3 2 &pcfg_pull_none>,
880 <1 RK_PD4 2 &pcfg_pull_none>,
881 <1 RK_PD5 2 &pcfg_pull_none>,
882 <1 RK_PD6 2 &pcfg_pull_none>,
883 <1 RK_PD7 2 &pcfg_pull_none>;
888 rgmii_pins: rgmii-pins {
889 rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>,
890 <2 RK_PB4 1 &pcfg_pull_none>,
891 <2 RK_PD1 1 &pcfg_pull_none>,
892 <2 RK_PC3 1 &pcfg_pull_none_drv_12ma>,
893 <2 RK_PC2 1 &pcfg_pull_none_drv_12ma>,
894 <2 RK_PC6 1 &pcfg_pull_none_drv_12ma>,
895 <2 RK_PC7 1 &pcfg_pull_none_drv_12ma>,
896 <2 RK_PB1 1 &pcfg_pull_none_drv_12ma>,
897 <2 RK_PB5 1 &pcfg_pull_none_drv_12ma>,
898 <2 RK_PC1 1 &pcfg_pull_none>,
899 <2 RK_PC0 1 &pcfg_pull_none>,
900 <2 RK_PC5 2 &pcfg_pull_none>,
901 <2 RK_PC4 2 &pcfg_pull_none>,
902 <2 RK_PB3 1 &pcfg_pull_none>,
903 <2 RK_PB0 1 &pcfg_pull_none>;
906 rmii_pins: rmii-pins {
907 rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>,
908 <2 RK_PB4 1 &pcfg_pull_none>,
909 <2 RK_PD1 1 &pcfg_pull_none>,
910 <2 RK_PC3 1 &pcfg_pull_none_drv_12ma>,
911 <2 RK_PC2 1 &pcfg_pull_none_drv_12ma>,
912 <2 RK_PB5 1 &pcfg_pull_none_drv_12ma>,
913 <2 RK_PC1 1 &pcfg_pull_none>,
914 <2 RK_PC0 1 &pcfg_pull_none>,
915 <2 RK_PB0 1 &pcfg_pull_none>,
916 <2 RK_PB7 1 &pcfg_pull_none>;
920 rockchip,pins = <2 RK_PB6 2 &pcfg_pull_none>,
921 <2 RK_PB0 2 &pcfg_pull_none>;
926 i2c0_xfer: i2c0-xfer {
927 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
928 <0 RK_PA1 1 &pcfg_pull_none>;
933 i2c1_xfer: i2c1-xfer {
934 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,
935 <0 RK_PA3 1 &pcfg_pull_none>;
940 i2c2_xfer: i2c2-xfer {
941 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>,
942 <2 RK_PC5 1 &pcfg_pull_none>;
947 i2c3_xfer: i2c3-xfer {
948 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,
949 <0 RK_PA7 1 &pcfg_pull_none>;
955 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_up>;
958 rockchip,pins = <0 RK_PB6 2 &pcfg_pull_up>;
961 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_up>;
964 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_up>;
967 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_up>;
973 rockchip,pins = <0 RK_PC7 2 &pcfg_pull_up>;
976 rockchip,pins = <2 RK_PA2 2 &pcfg_pull_up>;
979 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_up>;
982 rockchip,pins = <2 RK_PA1 2 &pcfg_pull_up>;
985 rockchip,pins = <2 RK_PA3 2 &pcfg_pull_up>;
991 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>,
992 <0 RK_PB1 1 &pcfg_pull_none>,
993 <0 RK_PB3 1 &pcfg_pull_none>,
994 <0 RK_PB4 1 &pcfg_pull_none>,
995 <0 RK_PB5 1 &pcfg_pull_none>,
996 <0 RK_PB6 1 &pcfg_pull_none>,
997 <1 RK_PA2 2 &pcfg_pull_none>,
998 <1 RK_PA4 2 &pcfg_pull_none>,
999 <1 RK_PA5 2 &pcfg_pull_none>;
1004 pwm0_pin: pwm0-pin {
1005 rockchip,pins = <3 RK_PC5 1 &pcfg_pull_none>;
1010 pwm1_pin: pwm1-pin {
1011 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>;
1016 pwm2_pin: pwm2-pin {
1017 rockchip,pins = <1 RK_PB4 2 &pcfg_pull_none>;
1022 pwm3_pin: pwm3-pin {
1023 rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>;
1028 spdif_tx: spdif-tx {
1029 rockchip,pins = <3 RK_PD7 2 &pcfg_pull_none>;
1034 otp_gpio: otp-gpio {
1035 rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
1039 rockchip,pins = <0 RK_PD0 2 &pcfg_pull_none>;
1044 uart0_xfer: uart0-xfer {
1045 rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>,
1046 <2 RK_PD3 1 &pcfg_pull_none>;
1049 uart0_cts: uart0-cts {
1050 rockchip,pins = <2 RK_PD5 1 &pcfg_pull_none>;
1053 uart0_rts: uart0-rts {
1054 rockchip,pins = <0 RK_PC1 1 &pcfg_pull_none>;
1059 uart1_xfer: uart1-xfer {
1060 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>,
1061 <1 RK_PB2 1 &pcfg_pull_none>;
1064 uart1_cts: uart1-cts {
1065 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>;
1068 uart1_rts: uart1-rts {
1069 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>;
1074 uart2_xfer: uart2-xfer {
1075 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>,
1076 <1 RK_PC3 2 &pcfg_pull_none>;
1079 uart21_xfer: uart21-xfer {
1080 rockchip,pins = <1 RK_PB2 2 &pcfg_pull_up>,
1081 <1 RK_PB1 2 &pcfg_pull_none>;
1084 uart2_cts: uart2-cts {
1085 rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>;
1088 uart2_rts: uart2-rts {
1089 rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>;