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mtd: nand: atmel: Relax tADL_min constraint
[mirror_ubuntu-artful-kernel.git] / arch / arm / boot / dts / rk3288.dtsi
1 /*
2 * This file is dual-licensed: you can use it either under the terms
3 * of the GPL or the X11 license, at your option. Note that this dual
4 * licensing only applies to this file, and not this project as a
5 * whole.
6 *
7 * a) This file is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of the
10 * License, or (at your option) any later version.
11 *
12 * This file is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * Or, alternatively,
18 *
19 * b) Permission is hereby granted, free of charge, to any person
20 * obtaining a copy of this software and associated documentation
21 * files (the "Software"), to deal in the Software without
22 * restriction, including without limitation the rights to use,
23 * copy, modify, merge, publish, distribute, sublicense, and/or
24 * sell copies of the Software, and to permit persons to whom the
25 * Software is furnished to do so, subject to the following
26 * conditions:
27 *
28 * The above copyright notice and this permission notice shall be
29 * included in all copies or substantial portions of the Software.
30 *
31 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
32 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
33 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
34 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
35 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
36 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
37 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
38 * OTHER DEALINGS IN THE SOFTWARE.
39 */
40
41 #include <dt-bindings/gpio/gpio.h>
42 #include <dt-bindings/interrupt-controller/irq.h>
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/pinctrl/rockchip.h>
45 #include <dt-bindings/clock/rk3288-cru.h>
46 #include <dt-bindings/power/rk3288-power.h>
47 #include <dt-bindings/thermal/thermal.h>
48 #include <dt-bindings/power/rk3288-power.h>
49 #include <dt-bindings/soc/rockchip,boot-mode.h>
50
51 / {
52 #address-cells = <1>;
53 #size-cells = <1>;
54
55 compatible = "rockchip,rk3288";
56
57 interrupt-parent = <&gic>;
58
59 aliases {
60 ethernet0 = &gmac;
61 i2c0 = &i2c0;
62 i2c1 = &i2c1;
63 i2c2 = &i2c2;
64 i2c3 = &i2c3;
65 i2c4 = &i2c4;
66 i2c5 = &i2c5;
67 mshc0 = &emmc;
68 mshc1 = &sdmmc;
69 mshc2 = &sdio0;
70 mshc3 = &sdio1;
71 serial0 = &uart0;
72 serial1 = &uart1;
73 serial2 = &uart2;
74 serial3 = &uart3;
75 serial4 = &uart4;
76 spi0 = &spi0;
77 spi1 = &spi1;
78 spi2 = &spi2;
79 };
80
81 arm-pmu {
82 compatible = "arm,cortex-a12-pmu";
83 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
84 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
85 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
86 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
87 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
88 };
89
90 cpus {
91 #address-cells = <1>;
92 #size-cells = <0>;
93 enable-method = "rockchip,rk3066-smp";
94 rockchip,pmu = <&pmu>;
95
96 cpu0: cpu@500 {
97 device_type = "cpu";
98 compatible = "arm,cortex-a12";
99 reg = <0x500>;
100 resets = <&cru SRST_CORE0>;
101 operating-points = <
102 /* KHz uV */
103 1608000 1350000
104 1512000 1300000
105 1416000 1200000
106 1200000 1100000
107 1008000 1050000
108 816000 1000000
109 696000 950000
110 600000 900000
111 408000 900000
112 312000 900000
113 216000 900000
114 126000 900000
115 >;
116 #cooling-cells = <2>; /* min followed by max */
117 clock-latency = <40000>;
118 clocks = <&cru ARMCLK>;
119 };
120 cpu1: cpu@501 {
121 device_type = "cpu";
122 compatible = "arm,cortex-a12";
123 reg = <0x501>;
124 resets = <&cru SRST_CORE1>;
125 };
126 cpu2: cpu@502 {
127 device_type = "cpu";
128 compatible = "arm,cortex-a12";
129 reg = <0x502>;
130 resets = <&cru SRST_CORE2>;
131 };
132 cpu3: cpu@503 {
133 device_type = "cpu";
134 compatible = "arm,cortex-a12";
135 reg = <0x503>;
136 resets = <&cru SRST_CORE3>;
137 };
138 };
139
140 amba {
141 compatible = "simple-bus";
142 #address-cells = <1>;
143 #size-cells = <1>;
144 ranges;
145
146 dmac_peri: dma-controller@ff250000 {
147 compatible = "arm,pl330", "arm,primecell";
148 reg = <0xff250000 0x4000>;
149 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
150 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
151 #dma-cells = <1>;
152 arm,pl330-broken-no-flushp;
153 clocks = <&cru ACLK_DMAC2>;
154 clock-names = "apb_pclk";
155 };
156
157 dmac_bus_ns: dma-controller@ff600000 {
158 compatible = "arm,pl330", "arm,primecell";
159 reg = <0xff600000 0x4000>;
160 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
161 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
162 #dma-cells = <1>;
163 arm,pl330-broken-no-flushp;
164 clocks = <&cru ACLK_DMAC1>;
165 clock-names = "apb_pclk";
166 status = "disabled";
167 };
168
169 dmac_bus_s: dma-controller@ffb20000 {
170 compatible = "arm,pl330", "arm,primecell";
171 reg = <0xffb20000 0x4000>;
172 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
173 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
174 #dma-cells = <1>;
175 arm,pl330-broken-no-flushp;
176 clocks = <&cru ACLK_DMAC1>;
177 clock-names = "apb_pclk";
178 };
179 };
180
181 reserved-memory {
182 #address-cells = <1>;
183 #size-cells = <1>;
184 ranges;
185
186 /*
187 * The rk3288 cannot use the memory area above 0xfe000000
188 * for dma operations for some reason. While there is
189 * probably a better solution available somewhere, we
190 * haven't found it yet and while devices with 2GB of ram
191 * are not affected, this issue prevents 4GB from booting.
192 * So to make these devices at least bootable, block
193 * this area for the time being until the real solution
194 * is found.
195 */
196 dma-unusable@fe000000 {
197 reg = <0xfe000000 0x1000000>;
198 };
199 };
200
201 xin24m: oscillator {
202 compatible = "fixed-clock";
203 clock-frequency = <24000000>;
204 clock-output-names = "xin24m";
205 #clock-cells = <0>;
206 };
207
208 timer {
209 compatible = "arm,armv7-timer";
210 arm,cpu-registers-not-fw-configured;
211 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
212 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
213 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
214 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
215 clock-frequency = <24000000>;
216 };
217
218 timer: timer@ff810000 {
219 compatible = "rockchip,rk3288-timer";
220 reg = <0xff810000 0x20>;
221 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
222 clocks = <&xin24m>, <&cru PCLK_TIMER>;
223 clock-names = "timer", "pclk";
224 };
225
226 display-subsystem {
227 compatible = "rockchip,display-subsystem";
228 ports = <&vopl_out>, <&vopb_out>;
229 };
230
231 sdmmc: dwmmc@ff0c0000 {
232 compatible = "rockchip,rk3288-dw-mshc";
233 max-frequency = <150000000>;
234 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
235 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
236 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
237 fifo-depth = <0x100>;
238 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
239 reg = <0xff0c0000 0x4000>;
240 resets = <&cru SRST_MMC0>;
241 reset-names = "reset";
242 status = "disabled";
243 };
244
245 sdio0: dwmmc@ff0d0000 {
246 compatible = "rockchip,rk3288-dw-mshc";
247 max-frequency = <150000000>;
248 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
249 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
250 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
251 fifo-depth = <0x100>;
252 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
253 reg = <0xff0d0000 0x4000>;
254 resets = <&cru SRST_SDIO0>;
255 reset-names = "reset";
256 status = "disabled";
257 };
258
259 sdio1: dwmmc@ff0e0000 {
260 compatible = "rockchip,rk3288-dw-mshc";
261 max-frequency = <150000000>;
262 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
263 <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
264 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
265 fifo-depth = <0x100>;
266 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
267 reg = <0xff0e0000 0x4000>;
268 resets = <&cru SRST_SDIO1>;
269 reset-names = "reset";
270 status = "disabled";
271 };
272
273 emmc: dwmmc@ff0f0000 {
274 compatible = "rockchip,rk3288-dw-mshc";
275 max-frequency = <150000000>;
276 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
277 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
278 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
279 fifo-depth = <0x100>;
280 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
281 reg = <0xff0f0000 0x4000>;
282 resets = <&cru SRST_EMMC>;
283 reset-names = "reset";
284 status = "disabled";
285 };
286
287 saradc: saradc@ff100000 {
288 compatible = "rockchip,saradc";
289 reg = <0xff100000 0x100>;
290 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
291 #io-channel-cells = <1>;
292 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
293 clock-names = "saradc", "apb_pclk";
294 resets = <&cru SRST_SARADC>;
295 reset-names = "saradc-apb";
296 status = "disabled";
297 };
298
299 spi0: spi@ff110000 {
300 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
301 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
302 clock-names = "spiclk", "apb_pclk";
303 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
304 dma-names = "tx", "rx";
305 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
306 pinctrl-names = "default";
307 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
308 reg = <0xff110000 0x1000>;
309 #address-cells = <1>;
310 #size-cells = <0>;
311 status = "disabled";
312 };
313
314 spi1: spi@ff120000 {
315 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
316 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
317 clock-names = "spiclk", "apb_pclk";
318 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
319 dma-names = "tx", "rx";
320 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
321 pinctrl-names = "default";
322 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
323 reg = <0xff120000 0x1000>;
324 #address-cells = <1>;
325 #size-cells = <0>;
326 status = "disabled";
327 };
328
329 spi2: spi@ff130000 {
330 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
331 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
332 clock-names = "spiclk", "apb_pclk";
333 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
334 dma-names = "tx", "rx";
335 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
336 pinctrl-names = "default";
337 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
338 reg = <0xff130000 0x1000>;
339 #address-cells = <1>;
340 #size-cells = <0>;
341 status = "disabled";
342 };
343
344 i2c1: i2c@ff140000 {
345 compatible = "rockchip,rk3288-i2c";
346 reg = <0xff140000 0x1000>;
347 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
348 #address-cells = <1>;
349 #size-cells = <0>;
350 clock-names = "i2c";
351 clocks = <&cru PCLK_I2C1>;
352 pinctrl-names = "default";
353 pinctrl-0 = <&i2c1_xfer>;
354 status = "disabled";
355 };
356
357 i2c3: i2c@ff150000 {
358 compatible = "rockchip,rk3288-i2c";
359 reg = <0xff150000 0x1000>;
360 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
361 #address-cells = <1>;
362 #size-cells = <0>;
363 clock-names = "i2c";
364 clocks = <&cru PCLK_I2C3>;
365 pinctrl-names = "default";
366 pinctrl-0 = <&i2c3_xfer>;
367 status = "disabled";
368 };
369
370 i2c4: i2c@ff160000 {
371 compatible = "rockchip,rk3288-i2c";
372 reg = <0xff160000 0x1000>;
373 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
374 #address-cells = <1>;
375 #size-cells = <0>;
376 clock-names = "i2c";
377 clocks = <&cru PCLK_I2C4>;
378 pinctrl-names = "default";
379 pinctrl-0 = <&i2c4_xfer>;
380 status = "disabled";
381 };
382
383 i2c5: i2c@ff170000 {
384 compatible = "rockchip,rk3288-i2c";
385 reg = <0xff170000 0x1000>;
386 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
387 #address-cells = <1>;
388 #size-cells = <0>;
389 clock-names = "i2c";
390 clocks = <&cru PCLK_I2C5>;
391 pinctrl-names = "default";
392 pinctrl-0 = <&i2c5_xfer>;
393 status = "disabled";
394 };
395
396 uart0: serial@ff180000 {
397 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
398 reg = <0xff180000 0x100>;
399 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
400 reg-shift = <2>;
401 reg-io-width = <4>;
402 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
403 clock-names = "baudclk", "apb_pclk";
404 pinctrl-names = "default";
405 pinctrl-0 = <&uart0_xfer>;
406 status = "disabled";
407 };
408
409 uart1: serial@ff190000 {
410 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
411 reg = <0xff190000 0x100>;
412 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
413 reg-shift = <2>;
414 reg-io-width = <4>;
415 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
416 clock-names = "baudclk", "apb_pclk";
417 pinctrl-names = "default";
418 pinctrl-0 = <&uart1_xfer>;
419 status = "disabled";
420 };
421
422 uart2: serial@ff690000 {
423 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
424 reg = <0xff690000 0x100>;
425 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
426 reg-shift = <2>;
427 reg-io-width = <4>;
428 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
429 clock-names = "baudclk", "apb_pclk";
430 pinctrl-names = "default";
431 pinctrl-0 = <&uart2_xfer>;
432 status = "disabled";
433 };
434
435 uart3: serial@ff1b0000 {
436 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
437 reg = <0xff1b0000 0x100>;
438 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
439 reg-shift = <2>;
440 reg-io-width = <4>;
441 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
442 clock-names = "baudclk", "apb_pclk";
443 pinctrl-names = "default";
444 pinctrl-0 = <&uart3_xfer>;
445 status = "disabled";
446 };
447
448 uart4: serial@ff1c0000 {
449 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
450 reg = <0xff1c0000 0x100>;
451 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
452 reg-shift = <2>;
453 reg-io-width = <4>;
454 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
455 clock-names = "baudclk", "apb_pclk";
456 pinctrl-names = "default";
457 pinctrl-0 = <&uart4_xfer>;
458 status = "disabled";
459 };
460
461 thermal-zones {
462 reserve_thermal: reserve_thermal {
463 polling-delay-passive = <1000>; /* milliseconds */
464 polling-delay = <5000>; /* milliseconds */
465
466 thermal-sensors = <&tsadc 0>;
467 };
468
469 cpu_thermal: cpu_thermal {
470 polling-delay-passive = <100>; /* milliseconds */
471 polling-delay = <5000>; /* milliseconds */
472
473 thermal-sensors = <&tsadc 1>;
474
475 trips {
476 cpu_alert0: cpu_alert0 {
477 temperature = <70000>; /* millicelsius */
478 hysteresis = <2000>; /* millicelsius */
479 type = "passive";
480 };
481 cpu_alert1: cpu_alert1 {
482 temperature = <75000>; /* millicelsius */
483 hysteresis = <2000>; /* millicelsius */
484 type = "passive";
485 };
486 cpu_crit: cpu_crit {
487 temperature = <90000>; /* millicelsius */
488 hysteresis = <2000>; /* millicelsius */
489 type = "critical";
490 };
491 };
492
493 cooling-maps {
494 map0 {
495 trip = <&cpu_alert0>;
496 cooling-device =
497 <&cpu0 THERMAL_NO_LIMIT 6>;
498 };
499 map1 {
500 trip = <&cpu_alert1>;
501 cooling-device =
502 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
503 };
504 };
505 };
506
507 gpu_thermal: gpu_thermal {
508 polling-delay-passive = <100>; /* milliseconds */
509 polling-delay = <5000>; /* milliseconds */
510
511 thermal-sensors = <&tsadc 2>;
512
513 trips {
514 gpu_alert0: gpu_alert0 {
515 temperature = <70000>; /* millicelsius */
516 hysteresis = <2000>; /* millicelsius */
517 type = "passive";
518 };
519 gpu_crit: gpu_crit {
520 temperature = <90000>; /* millicelsius */
521 hysteresis = <2000>; /* millicelsius */
522 type = "critical";
523 };
524 };
525
526 cooling-maps {
527 map0 {
528 trip = <&gpu_alert0>;
529 cooling-device =
530 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
531 };
532 };
533 };
534 };
535
536 tsadc: tsadc@ff280000 {
537 compatible = "rockchip,rk3288-tsadc";
538 reg = <0xff280000 0x100>;
539 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
540 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
541 clock-names = "tsadc", "apb_pclk";
542 resets = <&cru SRST_TSADC>;
543 reset-names = "tsadc-apb";
544 pinctrl-names = "init", "default", "sleep";
545 pinctrl-0 = <&otp_gpio>;
546 pinctrl-1 = <&otp_out>;
547 pinctrl-2 = <&otp_gpio>;
548 #thermal-sensor-cells = <1>;
549 rockchip,hw-tshut-temp = <95000>;
550 status = "disabled";
551 };
552
553 gmac: ethernet@ff290000 {
554 compatible = "rockchip,rk3288-gmac";
555 reg = <0xff290000 0x10000>;
556 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
557 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
558 interrupt-names = "macirq", "eth_wake_irq";
559 rockchip,grf = <&grf>;
560 clocks = <&cru SCLK_MAC>,
561 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
562 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
563 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
564 clock-names = "stmmaceth",
565 "mac_clk_rx", "mac_clk_tx",
566 "clk_mac_ref", "clk_mac_refout",
567 "aclk_mac", "pclk_mac";
568 resets = <&cru SRST_MAC>;
569 reset-names = "stmmaceth";
570 status = "disabled";
571 };
572
573 usb_host0_ehci: usb@ff500000 {
574 compatible = "generic-ehci";
575 reg = <0xff500000 0x100>;
576 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
577 clocks = <&cru HCLK_USBHOST0>;
578 clock-names = "usbhost";
579 phys = <&usbphy1>;
580 phy-names = "usb";
581 status = "disabled";
582 };
583
584 /* NOTE: ohci@ff520000 doesn't actually work on hardware */
585
586 usb_host1: usb@ff540000 {
587 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
588 "snps,dwc2";
589 reg = <0xff540000 0x40000>;
590 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
591 clocks = <&cru HCLK_USBHOST1>;
592 clock-names = "otg";
593 dr_mode = "host";
594 phys = <&usbphy2>;
595 phy-names = "usb2-phy";
596 status = "disabled";
597 };
598
599 usb_otg: usb@ff580000 {
600 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
601 "snps,dwc2";
602 reg = <0xff580000 0x40000>;
603 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
604 clocks = <&cru HCLK_OTG0>;
605 clock-names = "otg";
606 dr_mode = "otg";
607 g-np-tx-fifo-size = <16>;
608 g-rx-fifo-size = <275>;
609 g-tx-fifo-size = <256 128 128 64 64 32>;
610 phys = <&usbphy0>;
611 phy-names = "usb2-phy";
612 status = "disabled";
613 };
614
615 usb_hsic: usb@ff5c0000 {
616 compatible = "generic-ehci";
617 reg = <0xff5c0000 0x100>;
618 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
619 clocks = <&cru HCLK_HSIC>;
620 clock-names = "usbhost";
621 status = "disabled";
622 };
623
624 i2c0: i2c@ff650000 {
625 compatible = "rockchip,rk3288-i2c";
626 reg = <0xff650000 0x1000>;
627 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
628 #address-cells = <1>;
629 #size-cells = <0>;
630 clock-names = "i2c";
631 clocks = <&cru PCLK_I2C0>;
632 pinctrl-names = "default";
633 pinctrl-0 = <&i2c0_xfer>;
634 status = "disabled";
635 };
636
637 i2c2: i2c@ff660000 {
638 compatible = "rockchip,rk3288-i2c";
639 reg = <0xff660000 0x1000>;
640 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
641 #address-cells = <1>;
642 #size-cells = <0>;
643 clock-names = "i2c";
644 clocks = <&cru PCLK_I2C2>;
645 pinctrl-names = "default";
646 pinctrl-0 = <&i2c2_xfer>;
647 status = "disabled";
648 };
649
650 pwm0: pwm@ff680000 {
651 compatible = "rockchip,rk3288-pwm";
652 reg = <0xff680000 0x10>;
653 #pwm-cells = <3>;
654 pinctrl-names = "default";
655 pinctrl-0 = <&pwm0_pin>;
656 clocks = <&cru PCLK_PWM>;
657 clock-names = "pwm";
658 status = "disabled";
659 };
660
661 pwm1: pwm@ff680010 {
662 compatible = "rockchip,rk3288-pwm";
663 reg = <0xff680010 0x10>;
664 #pwm-cells = <3>;
665 pinctrl-names = "default";
666 pinctrl-0 = <&pwm1_pin>;
667 clocks = <&cru PCLK_PWM>;
668 clock-names = "pwm";
669 status = "disabled";
670 };
671
672 pwm2: pwm@ff680020 {
673 compatible = "rockchip,rk3288-pwm";
674 reg = <0xff680020 0x10>;
675 #pwm-cells = <3>;
676 pinctrl-names = "default";
677 pinctrl-0 = <&pwm2_pin>;
678 clocks = <&cru PCLK_PWM>;
679 clock-names = "pwm";
680 status = "disabled";
681 };
682
683 pwm3: pwm@ff680030 {
684 compatible = "rockchip,rk3288-pwm";
685 reg = <0xff680030 0x10>;
686 #pwm-cells = <2>;
687 pinctrl-names = "default";
688 pinctrl-0 = <&pwm3_pin>;
689 clocks = <&cru PCLK_PWM>;
690 clock-names = "pwm";
691 status = "disabled";
692 };
693
694 bus_intmem@ff700000 {
695 compatible = "mmio-sram";
696 reg = <0xff700000 0x18000>;
697 #address-cells = <1>;
698 #size-cells = <1>;
699 ranges = <0 0xff700000 0x18000>;
700 smp-sram@0 {
701 compatible = "rockchip,rk3066-smp-sram";
702 reg = <0x00 0x10>;
703 };
704 };
705
706 sram@ff720000 {
707 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
708 reg = <0xff720000 0x1000>;
709 };
710
711 pmu: power-management@ff730000 {
712 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
713 reg = <0xff730000 0x100>;
714
715 power: power-controller {
716 compatible = "rockchip,rk3288-power-controller";
717 #power-domain-cells = <1>;
718 #address-cells = <1>;
719 #size-cells = <0>;
720
721 assigned-clocks = <&cru SCLK_EDP_24M>;
722 assigned-clock-parents = <&xin24m>;
723
724 /*
725 * Note: Although SCLK_* are the working clocks
726 * of device without including on the NOC, needed for
727 * synchronous reset.
728 *
729 * The clocks on the which NOC:
730 * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
731 * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
732 * ACLK_RGA is on ACLK_RGA_NIU.
733 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
734 *
735 * Which clock are device clocks:
736 * clocks devices
737 * *_IEP IEP:Image Enhancement Processor
738 * *_ISP ISP:Image Signal Processing
739 * *_VIP VIP:Video Input Processor
740 * *_VOP* VOP:Visual Output Processor
741 * *_RGA RGA
742 * *_EDP* EDP
743 * *_LVDS_* LVDS
744 * *_HDMI HDMI
745 * *_MIPI_* MIPI
746 */
747 pd_vio@RK3288_PD_VIO {
748 reg = <RK3288_PD_VIO>;
749 clocks = <&cru ACLK_IEP>,
750 <&cru ACLK_ISP>,
751 <&cru ACLK_RGA>,
752 <&cru ACLK_VIP>,
753 <&cru ACLK_VOP0>,
754 <&cru ACLK_VOP1>,
755 <&cru DCLK_VOP0>,
756 <&cru DCLK_VOP1>,
757 <&cru HCLK_IEP>,
758 <&cru HCLK_ISP>,
759 <&cru HCLK_RGA>,
760 <&cru HCLK_VIP>,
761 <&cru HCLK_VOP0>,
762 <&cru HCLK_VOP1>,
763 <&cru PCLK_EDP_CTRL>,
764 <&cru PCLK_HDMI_CTRL>,
765 <&cru PCLK_LVDS_PHY>,
766 <&cru PCLK_MIPI_CSI>,
767 <&cru PCLK_MIPI_DSI0>,
768 <&cru PCLK_MIPI_DSI1>,
769 <&cru SCLK_EDP_24M>,
770 <&cru SCLK_EDP>,
771 <&cru SCLK_ISP_JPE>,
772 <&cru SCLK_ISP>,
773 <&cru SCLK_RGA>;
774 pm_qos = <&qos_vio0_iep>,
775 <&qos_vio1_vop>,
776 <&qos_vio1_isp_w0>,
777 <&qos_vio1_isp_w1>,
778 <&qos_vio0_vop>,
779 <&qos_vio0_vip>,
780 <&qos_vio2_rga_r>,
781 <&qos_vio2_rga_w>,
782 <&qos_vio1_isp_r>;
783 };
784
785 /*
786 * Note: The following 3 are HEVC(H.265) clocks,
787 * and on the ACLK_HEVC_NIU (NOC).
788 */
789 pd_hevc@RK3288_PD_HEVC {
790 reg = <RK3288_PD_HEVC>;
791 clocks = <&cru ACLK_HEVC>,
792 <&cru SCLK_HEVC_CABAC>,
793 <&cru SCLK_HEVC_CORE>;
794 pm_qos = <&qos_hevc_r>,
795 <&qos_hevc_w>;
796 };
797
798 /*
799 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
800 * (video endecoder & decoder) clocks that on the
801 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
802 */
803 pd_video@RK3288_PD_VIDEO {
804 reg = <RK3288_PD_VIDEO>;
805 clocks = <&cru ACLK_VCODEC>,
806 <&cru HCLK_VCODEC>;
807 pm_qos = <&qos_video>;
808 };
809
810 /*
811 * Note: ACLK_GPU is the GPU clock,
812 * and on the ACLK_GPU_NIU (NOC).
813 */
814 pd_gpu@RK3288_PD_GPU {
815 reg = <RK3288_PD_GPU>;
816 clocks = <&cru ACLK_GPU>;
817 pm_qos = <&qos_gpu_r>,
818 <&qos_gpu_w>;
819 };
820 };
821
822 reboot-mode {
823 compatible = "syscon-reboot-mode";
824 offset = <0x94>;
825 mode-normal = <BOOT_NORMAL>;
826 mode-recovery = <BOOT_RECOVERY>;
827 mode-bootloader = <BOOT_FASTBOOT>;
828 mode-loader = <BOOT_BL_DOWNLOAD>;
829 };
830 };
831
832 sgrf: syscon@ff740000 {
833 compatible = "rockchip,rk3288-sgrf", "syscon";
834 reg = <0xff740000 0x1000>;
835 };
836
837 cru: clock-controller@ff760000 {
838 compatible = "rockchip,rk3288-cru";
839 reg = <0xff760000 0x1000>;
840 rockchip,grf = <&grf>;
841 #clock-cells = <1>;
842 #reset-cells = <1>;
843 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
844 <&cru PLL_NPLL>, <&cru ACLK_CPU>,
845 <&cru HCLK_CPU>, <&cru PCLK_CPU>,
846 <&cru ACLK_PERI>, <&cru HCLK_PERI>,
847 <&cru PCLK_PERI>;
848 assigned-clock-rates = <594000000>, <400000000>,
849 <500000000>, <300000000>,
850 <150000000>, <75000000>,
851 <300000000>, <150000000>,
852 <75000000>;
853 };
854
855 grf: syscon@ff770000 {
856 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
857 reg = <0xff770000 0x1000>;
858
859 edp_phy: edp-phy {
860 compatible = "rockchip,rk3288-dp-phy";
861 clocks = <&cru SCLK_EDP_24M>;
862 clock-names = "24m";
863 #phy-cells = <0>;
864 status = "disabled";
865 };
866
867 io_domains: io-domains {
868 compatible = "rockchip,rk3288-io-voltage-domain";
869 status = "disabled";
870 };
871
872 usbphy: usbphy {
873 compatible = "rockchip,rk3288-usb-phy";
874 #address-cells = <1>;
875 #size-cells = <0>;
876 status = "disabled";
877
878 usbphy0: usb-phy@320 {
879 #phy-cells = <0>;
880 reg = <0x320>;
881 clocks = <&cru SCLK_OTGPHY0>;
882 clock-names = "phyclk";
883 #clock-cells = <0>;
884 };
885
886 usbphy1: usb-phy@334 {
887 #phy-cells = <0>;
888 reg = <0x334>;
889 clocks = <&cru SCLK_OTGPHY1>;
890 clock-names = "phyclk";
891 #clock-cells = <0>;
892 };
893
894 usbphy2: usb-phy@348 {
895 #phy-cells = <0>;
896 reg = <0x348>;
897 clocks = <&cru SCLK_OTGPHY2>;
898 clock-names = "phyclk";
899 #clock-cells = <0>;
900 };
901 };
902 };
903
904 wdt: watchdog@ff800000 {
905 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
906 reg = <0xff800000 0x100>;
907 clocks = <&cru PCLK_WDT>;
908 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
909 status = "disabled";
910 };
911
912 spdif: sound@ff88b0000 {
913 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
914 reg = <0xff8b0000 0x10000>;
915 #sound-dai-cells = <0>;
916 clock-names = "hclk", "mclk";
917 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
918 dmas = <&dmac_bus_s 3>;
919 dma-names = "tx";
920 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
921 pinctrl-names = "default";
922 pinctrl-0 = <&spdif_tx>;
923 rockchip,grf = <&grf>;
924 status = "disabled";
925 };
926
927 i2s: i2s@ff890000 {
928 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
929 reg = <0xff890000 0x10000>;
930 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
931 #address-cells = <1>;
932 #size-cells = <0>;
933 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
934 dma-names = "tx", "rx";
935 clock-names = "i2s_hclk", "i2s_clk";
936 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
937 pinctrl-names = "default";
938 pinctrl-0 = <&i2s0_bus>;
939 rockchip,playback-channels = <8>;
940 rockchip,capture-channels = <2>;
941 status = "disabled";
942 };
943
944 crypto: cypto-controller@ff8a0000 {
945 compatible = "rockchip,rk3288-crypto";
946 reg = <0xff8a0000 0x4000>;
947 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
948 clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>,
949 <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>;
950 clock-names = "aclk", "hclk", "sclk", "apb_pclk";
951 resets = <&cru SRST_CRYPTO>;
952 reset-names = "crypto-rst";
953 status = "okay";
954 };
955
956 vopb: vop@ff930000 {
957 compatible = "rockchip,rk3288-vop";
958 reg = <0xff930000 0x19c>;
959 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
960 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
961 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
962 power-domains = <&power RK3288_PD_VIO>;
963 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
964 reset-names = "axi", "ahb", "dclk";
965 iommus = <&vopb_mmu>;
966 status = "disabled";
967
968 vopb_out: port {
969 #address-cells = <1>;
970 #size-cells = <0>;
971
972 vopb_out_hdmi: endpoint@0 {
973 reg = <0>;
974 remote-endpoint = <&hdmi_in_vopb>;
975 };
976
977 vopb_out_edp: endpoint@1 {
978 reg = <1>;
979 remote-endpoint = <&edp_in_vopb>;
980 };
981
982 vopb_out_mipi: endpoint@2 {
983 reg = <2>;
984 remote-endpoint = <&mipi_in_vopb>;
985 };
986 };
987 };
988
989 vopb_mmu: iommu@ff930300 {
990 compatible = "rockchip,iommu";
991 reg = <0xff930300 0x100>;
992 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
993 interrupt-names = "vopb_mmu";
994 power-domains = <&power RK3288_PD_VIO>;
995 #iommu-cells = <0>;
996 status = "disabled";
997 };
998
999 vopl: vop@ff940000 {
1000 compatible = "rockchip,rk3288-vop";
1001 reg = <0xff940000 0x19c>;
1002 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1003 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1004 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1005 power-domains = <&power RK3288_PD_VIO>;
1006 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
1007 reset-names = "axi", "ahb", "dclk";
1008 iommus = <&vopl_mmu>;
1009 status = "disabled";
1010
1011 vopl_out: port {
1012 #address-cells = <1>;
1013 #size-cells = <0>;
1014
1015 vopl_out_hdmi: endpoint@0 {
1016 reg = <0>;
1017 remote-endpoint = <&hdmi_in_vopl>;
1018 };
1019
1020 vopl_out_edp: endpoint@1 {
1021 reg = <1>;
1022 remote-endpoint = <&edp_in_vopl>;
1023 };
1024
1025 vopl_out_mipi: endpoint@2 {
1026 reg = <2>;
1027 remote-endpoint = <&mipi_in_vopl>;
1028 };
1029 };
1030 };
1031
1032 vopl_mmu: iommu@ff940300 {
1033 compatible = "rockchip,iommu";
1034 reg = <0xff940300 0x100>;
1035 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1036 interrupt-names = "vopl_mmu";
1037 power-domains = <&power RK3288_PD_VIO>;
1038 #iommu-cells = <0>;
1039 status = "disabled";
1040 };
1041
1042 mipi_dsi: mipi@ff960000 {
1043 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
1044 reg = <0xff960000 0x4000>;
1045 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1046 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
1047 clock-names = "ref", "pclk";
1048 power-domains = <&power RK3288_PD_VIO>;
1049 rockchip,grf = <&grf>;
1050 #address-cells = <1>;
1051 #size-cells = <0>;
1052 status = "disabled";
1053
1054 ports {
1055 mipi_in: port {
1056 #address-cells = <1>;
1057 #size-cells = <0>;
1058 mipi_in_vopb: endpoint@0 {
1059 reg = <0>;
1060 remote-endpoint = <&vopb_out_mipi>;
1061 };
1062 mipi_in_vopl: endpoint@1 {
1063 reg = <1>;
1064 remote-endpoint = <&vopl_out_mipi>;
1065 };
1066 };
1067 };
1068 };
1069
1070 edp: dp@ff970000 {
1071 compatible = "rockchip,rk3288-dp";
1072 reg = <0xff970000 0x4000>;
1073 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1074 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1075 clock-names = "dp", "pclk";
1076 phys = <&edp_phy>;
1077 phy-names = "dp";
1078 resets = <&cru SRST_EDP>;
1079 reset-names = "dp";
1080 rockchip,grf = <&grf>;
1081 status = "disabled";
1082
1083 ports {
1084 #address-cells = <1>;
1085 #size-cells = <0>;
1086 edp_in: port@0 {
1087 reg = <0>;
1088 #address-cells = <1>;
1089 #size-cells = <0>;
1090 edp_in_vopb: endpoint@0 {
1091 reg = <0>;
1092 remote-endpoint = <&vopb_out_edp>;
1093 };
1094 edp_in_vopl: endpoint@1 {
1095 reg = <1>;
1096 remote-endpoint = <&vopl_out_edp>;
1097 };
1098 };
1099 };
1100 };
1101
1102 hdmi: hdmi@ff980000 {
1103 compatible = "rockchip,rk3288-dw-hdmi";
1104 reg = <0xff980000 0x20000>;
1105 reg-io-width = <4>;
1106 rockchip,grf = <&grf>;
1107 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1108 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
1109 clock-names = "iahb", "isfr";
1110 power-domains = <&power RK3288_PD_VIO>;
1111 status = "disabled";
1112
1113 ports {
1114 hdmi_in: port {
1115 #address-cells = <1>;
1116 #size-cells = <0>;
1117 hdmi_in_vopb: endpoint@0 {
1118 reg = <0>;
1119 remote-endpoint = <&vopb_out_hdmi>;
1120 };
1121 hdmi_in_vopl: endpoint@1 {
1122 reg = <1>;
1123 remote-endpoint = <&vopl_out_hdmi>;
1124 };
1125 };
1126 };
1127 };
1128
1129 gpu: mali@ffa30000 {
1130 compatible = "rockchip,rk3288-mali", "arm,mali-t760", "arm,mali-midgard";
1131 reg = <0xffa30000 0x10000>;
1132 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1133 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1134 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1135 interrupt-names = "job", "mmu", "gpu";
1136 clocks = <&cru ACLK_GPU>;
1137 operating-points-v2 = <&gpu_opp_table>;
1138 power-domains = <&power RK3288_PD_GPU>;
1139 status = "disabled";
1140 };
1141
1142 gpu_opp_table: gpu-opp-table {
1143 compatible = "operating-points-v2";
1144
1145 opp@100000000 {
1146 opp-hz = /bits/ 64 <100000000>;
1147 opp-microvolt = <950000>;
1148 };
1149 opp@200000000 {
1150 opp-hz = /bits/ 64 <200000000>;
1151 opp-microvolt = <950000>;
1152 };
1153 opp@300000000 {
1154 opp-hz = /bits/ 64 <300000000>;
1155 opp-microvolt = <1000000>;
1156 };
1157 opp@400000000 {
1158 opp-hz = /bits/ 64 <400000000>;
1159 opp-microvolt = <1100000>;
1160 };
1161 opp@500000000 {
1162 opp-hz = /bits/ 64 <500000000>;
1163 opp-microvolt = <1200000>;
1164 };
1165 opp@600000000 {
1166 opp-hz = /bits/ 64 <600000000>;
1167 opp-microvolt = <1250000>;
1168 };
1169 };
1170
1171 qos_gpu_r: qos@ffaa0000 {
1172 compatible = "syscon";
1173 reg = <0xffaa0000 0x20>;
1174 };
1175
1176 qos_gpu_w: qos@ffaa0080 {
1177 compatible = "syscon";
1178 reg = <0xffaa0080 0x20>;
1179 };
1180
1181 qos_vio1_vop: qos@ffad0000 {
1182 compatible = "syscon";
1183 reg = <0xffad0000 0x20>;
1184 };
1185
1186 qos_vio1_isp_w0: qos@ffad0100 {
1187 compatible = "syscon";
1188 reg = <0xffad0100 0x20>;
1189 };
1190
1191 qos_vio1_isp_w1: qos@ffad0180 {
1192 compatible = "syscon";
1193 reg = <0xffad0180 0x20>;
1194 };
1195
1196 qos_vio0_vop: qos@ffad0400 {
1197 compatible = "syscon";
1198 reg = <0xffad0400 0x20>;
1199 };
1200
1201 qos_vio0_vip: qos@ffad0480 {
1202 compatible = "syscon";
1203 reg = <0xffad0480 0x20>;
1204 };
1205
1206 qos_vio0_iep: qos@ffad0500 {
1207 compatible = "syscon";
1208 reg = <0xffad0500 0x20>;
1209 };
1210
1211 qos_vio2_rga_r: qos@ffad0800 {
1212 compatible = "syscon";
1213 reg = <0xffad0800 0x20>;
1214 };
1215
1216 qos_vio2_rga_w: qos@ffad0880 {
1217 compatible = "syscon";
1218 reg = <0xffad0880 0x20>;
1219 };
1220
1221 qos_vio1_isp_r: qos@ffad0900 {
1222 compatible = "syscon";
1223 reg = <0xffad0900 0x20>;
1224 };
1225
1226 qos_video: qos@ffae0000 {
1227 compatible = "syscon";
1228 reg = <0xffae0000 0x20>;
1229 };
1230
1231 qos_hevc_r: qos@ffaf0000 {
1232 compatible = "syscon";
1233 reg = <0xffaf0000 0x20>;
1234 };
1235
1236 qos_hevc_w: qos@ffaf0080 {
1237 compatible = "syscon";
1238 reg = <0xffaf0080 0x20>;
1239 };
1240
1241 gic: interrupt-controller@ffc01000 {
1242 compatible = "arm,gic-400";
1243 interrupt-controller;
1244 #interrupt-cells = <3>;
1245 #address-cells = <0>;
1246
1247 reg = <0xffc01000 0x1000>,
1248 <0xffc02000 0x2000>,
1249 <0xffc04000 0x2000>,
1250 <0xffc06000 0x2000>;
1251 interrupts = <GIC_PPI 9 0xf04>;
1252 };
1253
1254 efuse: efuse@ffb40000 {
1255 compatible = "rockchip,rk3288-efuse";
1256 reg = <0xffb40000 0x20>;
1257 #address-cells = <1>;
1258 #size-cells = <1>;
1259 clocks = <&cru PCLK_EFUSE256>;
1260 clock-names = "pclk_efuse";
1261
1262 cpu_leakage: cpu_leakage@17 {
1263 reg = <0x17 0x1>;
1264 };
1265 };
1266
1267 pinctrl: pinctrl {
1268 compatible = "rockchip,rk3288-pinctrl";
1269 rockchip,grf = <&grf>;
1270 rockchip,pmu = <&pmu>;
1271 #address-cells = <1>;
1272 #size-cells = <1>;
1273 ranges;
1274
1275 gpio0: gpio0@ff750000 {
1276 compatible = "rockchip,gpio-bank";
1277 reg = <0xff750000 0x100>;
1278 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1279 clocks = <&cru PCLK_GPIO0>;
1280
1281 gpio-controller;
1282 #gpio-cells = <2>;
1283
1284 interrupt-controller;
1285 #interrupt-cells = <2>;
1286 };
1287
1288 gpio1: gpio1@ff780000 {
1289 compatible = "rockchip,gpio-bank";
1290 reg = <0xff780000 0x100>;
1291 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1292 clocks = <&cru PCLK_GPIO1>;
1293
1294 gpio-controller;
1295 #gpio-cells = <2>;
1296
1297 interrupt-controller;
1298 #interrupt-cells = <2>;
1299 };
1300
1301 gpio2: gpio2@ff790000 {
1302 compatible = "rockchip,gpio-bank";
1303 reg = <0xff790000 0x100>;
1304 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1305 clocks = <&cru PCLK_GPIO2>;
1306
1307 gpio-controller;
1308 #gpio-cells = <2>;
1309
1310 interrupt-controller;
1311 #interrupt-cells = <2>;
1312 };
1313
1314 gpio3: gpio3@ff7a0000 {
1315 compatible = "rockchip,gpio-bank";
1316 reg = <0xff7a0000 0x100>;
1317 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1318 clocks = <&cru PCLK_GPIO3>;
1319
1320 gpio-controller;
1321 #gpio-cells = <2>;
1322
1323 interrupt-controller;
1324 #interrupt-cells = <2>;
1325 };
1326
1327 gpio4: gpio4@ff7b0000 {
1328 compatible = "rockchip,gpio-bank";
1329 reg = <0xff7b0000 0x100>;
1330 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1331 clocks = <&cru PCLK_GPIO4>;
1332
1333 gpio-controller;
1334 #gpio-cells = <2>;
1335
1336 interrupt-controller;
1337 #interrupt-cells = <2>;
1338 };
1339
1340 gpio5: gpio5@ff7c0000 {
1341 compatible = "rockchip,gpio-bank";
1342 reg = <0xff7c0000 0x100>;
1343 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1344 clocks = <&cru PCLK_GPIO5>;
1345
1346 gpio-controller;
1347 #gpio-cells = <2>;
1348
1349 interrupt-controller;
1350 #interrupt-cells = <2>;
1351 };
1352
1353 gpio6: gpio6@ff7d0000 {
1354 compatible = "rockchip,gpio-bank";
1355 reg = <0xff7d0000 0x100>;
1356 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1357 clocks = <&cru PCLK_GPIO6>;
1358
1359 gpio-controller;
1360 #gpio-cells = <2>;
1361
1362 interrupt-controller;
1363 #interrupt-cells = <2>;
1364 };
1365
1366 gpio7: gpio7@ff7e0000 {
1367 compatible = "rockchip,gpio-bank";
1368 reg = <0xff7e0000 0x100>;
1369 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1370 clocks = <&cru PCLK_GPIO7>;
1371
1372 gpio-controller;
1373 #gpio-cells = <2>;
1374
1375 interrupt-controller;
1376 #interrupt-cells = <2>;
1377 };
1378
1379 gpio8: gpio8@ff7f0000 {
1380 compatible = "rockchip,gpio-bank";
1381 reg = <0xff7f0000 0x100>;
1382 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1383 clocks = <&cru PCLK_GPIO8>;
1384
1385 gpio-controller;
1386 #gpio-cells = <2>;
1387
1388 interrupt-controller;
1389 #interrupt-cells = <2>;
1390 };
1391
1392 hdmi {
1393 hdmi_ddc: hdmi-ddc {
1394 rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>,
1395 <7 20 RK_FUNC_2 &pcfg_pull_none>;
1396 };
1397 };
1398
1399 pcfg_pull_up: pcfg-pull-up {
1400 bias-pull-up;
1401 };
1402
1403 pcfg_pull_down: pcfg-pull-down {
1404 bias-pull-down;
1405 };
1406
1407 pcfg_pull_none: pcfg-pull-none {
1408 bias-disable;
1409 };
1410
1411 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1412 bias-disable;
1413 drive-strength = <12>;
1414 };
1415
1416 sleep {
1417 global_pwroff: global-pwroff {
1418 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1419 };
1420
1421 ddrio_pwroff: ddrio-pwroff {
1422 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1423 };
1424
1425 ddr0_retention: ddr0-retention {
1426 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1427 };
1428
1429 ddr1_retention: ddr1-retention {
1430 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1431 };
1432 };
1433
1434 edp {
1435 edp_hpd: edp-hpd {
1436 rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>;
1437 };
1438 };
1439
1440 i2c0 {
1441 i2c0_xfer: i2c0-xfer {
1442 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1443 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1444 };
1445 };
1446
1447 i2c1 {
1448 i2c1_xfer: i2c1-xfer {
1449 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1450 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1451 };
1452 };
1453
1454 i2c2 {
1455 i2c2_xfer: i2c2-xfer {
1456 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1457 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1458 };
1459 };
1460
1461 i2c3 {
1462 i2c3_xfer: i2c3-xfer {
1463 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1464 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1465 };
1466 };
1467
1468 i2c4 {
1469 i2c4_xfer: i2c4-xfer {
1470 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1471 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1472 };
1473 };
1474
1475 i2c5 {
1476 i2c5_xfer: i2c5-xfer {
1477 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1478 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1479 };
1480 };
1481
1482 i2s0 {
1483 i2s0_bus: i2s0-bus {
1484 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1485 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1486 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1487 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1488 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1489 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1490 };
1491 };
1492
1493 sdmmc {
1494 sdmmc_clk: sdmmc-clk {
1495 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1496 };
1497
1498 sdmmc_cmd: sdmmc-cmd {
1499 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1500 };
1501
1502 sdmmc_cd: sdmmc-cd {
1503 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1504 };
1505
1506 sdmmc_bus1: sdmmc-bus1 {
1507 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1508 };
1509
1510 sdmmc_bus4: sdmmc-bus4 {
1511 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1512 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1513 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1514 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1515 };
1516 };
1517
1518 sdio0 {
1519 sdio0_bus1: sdio0-bus1 {
1520 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1521 };
1522
1523 sdio0_bus4: sdio0-bus4 {
1524 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1525 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1526 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1527 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1528 };
1529
1530 sdio0_cmd: sdio0-cmd {
1531 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1532 };
1533
1534 sdio0_clk: sdio0-clk {
1535 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1536 };
1537
1538 sdio0_cd: sdio0-cd {
1539 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1540 };
1541
1542 sdio0_wp: sdio0-wp {
1543 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1544 };
1545
1546 sdio0_pwr: sdio0-pwr {
1547 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1548 };
1549
1550 sdio0_bkpwr: sdio0-bkpwr {
1551 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1552 };
1553
1554 sdio0_int: sdio0-int {
1555 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1556 };
1557 };
1558
1559 sdio1 {
1560 sdio1_bus1: sdio1-bus1 {
1561 rockchip,pins = <3 24 4 &pcfg_pull_up>;
1562 };
1563
1564 sdio1_bus4: sdio1-bus4 {
1565 rockchip,pins = <3 24 4 &pcfg_pull_up>,
1566 <3 25 4 &pcfg_pull_up>,
1567 <3 26 4 &pcfg_pull_up>,
1568 <3 27 4 &pcfg_pull_up>;
1569 };
1570
1571 sdio1_cd: sdio1-cd {
1572 rockchip,pins = <3 28 4 &pcfg_pull_up>;
1573 };
1574
1575 sdio1_wp: sdio1-wp {
1576 rockchip,pins = <3 29 4 &pcfg_pull_up>;
1577 };
1578
1579 sdio1_bkpwr: sdio1-bkpwr {
1580 rockchip,pins = <3 30 4 &pcfg_pull_up>;
1581 };
1582
1583 sdio1_int: sdio1-int {
1584 rockchip,pins = <3 31 4 &pcfg_pull_up>;
1585 };
1586
1587 sdio1_cmd: sdio1-cmd {
1588 rockchip,pins = <4 6 4 &pcfg_pull_up>;
1589 };
1590
1591 sdio1_clk: sdio1-clk {
1592 rockchip,pins = <4 7 4 &pcfg_pull_none>;
1593 };
1594
1595 sdio1_pwr: sdio1-pwr {
1596 rockchip,pins = <4 9 4 &pcfg_pull_up>;
1597 };
1598 };
1599
1600 emmc {
1601 emmc_clk: emmc-clk {
1602 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1603 };
1604
1605 emmc_cmd: emmc-cmd {
1606 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1607 };
1608
1609 emmc_pwr: emmc-pwr {
1610 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1611 };
1612
1613 emmc_bus1: emmc-bus1 {
1614 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1615 };
1616
1617 emmc_bus4: emmc-bus4 {
1618 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1619 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1620 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1621 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1622 };
1623
1624 emmc_bus8: emmc-bus8 {
1625 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1626 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1627 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1628 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1629 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1630 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1631 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1632 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1633 };
1634 };
1635
1636 spi0 {
1637 spi0_clk: spi0-clk {
1638 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1639 };
1640 spi0_cs0: spi0-cs0 {
1641 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1642 };
1643 spi0_tx: spi0-tx {
1644 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1645 };
1646 spi0_rx: spi0-rx {
1647 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1648 };
1649 spi0_cs1: spi0-cs1 {
1650 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1651 };
1652 };
1653 spi1 {
1654 spi1_clk: spi1-clk {
1655 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1656 };
1657 spi1_cs0: spi1-cs0 {
1658 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1659 };
1660 spi1_rx: spi1-rx {
1661 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1662 };
1663 spi1_tx: spi1-tx {
1664 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1665 };
1666 };
1667
1668 spi2 {
1669 spi2_cs1: spi2-cs1 {
1670 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1671 };
1672 spi2_clk: spi2-clk {
1673 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1674 };
1675 spi2_cs0: spi2-cs0 {
1676 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1677 };
1678 spi2_rx: spi2-rx {
1679 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1680 };
1681 spi2_tx: spi2-tx {
1682 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1683 };
1684 };
1685
1686 uart0 {
1687 uart0_xfer: uart0-xfer {
1688 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1689 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1690 };
1691
1692 uart0_cts: uart0-cts {
1693 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>;
1694 };
1695
1696 uart0_rts: uart0-rts {
1697 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1698 };
1699 };
1700
1701 uart1 {
1702 uart1_xfer: uart1-xfer {
1703 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1704 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1705 };
1706
1707 uart1_cts: uart1-cts {
1708 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>;
1709 };
1710
1711 uart1_rts: uart1-rts {
1712 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1713 };
1714 };
1715
1716 uart2 {
1717 uart2_xfer: uart2-xfer {
1718 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1719 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1720 };
1721 /* no rts / cts for uart2 */
1722 };
1723
1724 uart3 {
1725 uart3_xfer: uart3-xfer {
1726 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1727 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1728 };
1729
1730 uart3_cts: uart3-cts {
1731 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>;
1732 };
1733
1734 uart3_rts: uart3-rts {
1735 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1736 };
1737 };
1738
1739 uart4 {
1740 uart4_xfer: uart4-xfer {
1741 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1742 <5 13 3 &pcfg_pull_none>;
1743 };
1744
1745 uart4_cts: uart4-cts {
1746 rockchip,pins = <5 14 3 &pcfg_pull_up>;
1747 };
1748
1749 uart4_rts: uart4-rts {
1750 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1751 };
1752 };
1753
1754 tsadc {
1755 otp_gpio: otp-gpio {
1756 rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
1757 };
1758
1759 otp_out: otp-out {
1760 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1761 };
1762 };
1763
1764 pwm0 {
1765 pwm0_pin: pwm0-pin {
1766 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1767 };
1768 };
1769
1770 pwm1 {
1771 pwm1_pin: pwm1-pin {
1772 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1773 };
1774 };
1775
1776 pwm2 {
1777 pwm2_pin: pwm2-pin {
1778 rockchip,pins = <7 22 3 &pcfg_pull_none>;
1779 };
1780 };
1781
1782 pwm3 {
1783 pwm3_pin: pwm3-pin {
1784 rockchip,pins = <7 23 3 &pcfg_pull_none>;
1785 };
1786 };
1787
1788 gmac {
1789 rgmii_pins: rgmii-pins {
1790 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1791 <3 31 3 &pcfg_pull_none>,
1792 <3 26 3 &pcfg_pull_none>,
1793 <3 27 3 &pcfg_pull_none>,
1794 <3 28 3 &pcfg_pull_none_12ma>,
1795 <3 29 3 &pcfg_pull_none_12ma>,
1796 <3 24 3 &pcfg_pull_none_12ma>,
1797 <3 25 3 &pcfg_pull_none_12ma>,
1798 <4 0 3 &pcfg_pull_none>,
1799 <4 5 3 &pcfg_pull_none>,
1800 <4 6 3 &pcfg_pull_none>,
1801 <4 9 3 &pcfg_pull_none_12ma>,
1802 <4 4 3 &pcfg_pull_none_12ma>,
1803 <4 1 3 &pcfg_pull_none>,
1804 <4 3 3 &pcfg_pull_none>;
1805 };
1806
1807 rmii_pins: rmii-pins {
1808 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1809 <3 31 3 &pcfg_pull_none>,
1810 <3 28 3 &pcfg_pull_none>,
1811 <3 29 3 &pcfg_pull_none>,
1812 <4 0 3 &pcfg_pull_none>,
1813 <4 5 3 &pcfg_pull_none>,
1814 <4 4 3 &pcfg_pull_none>,
1815 <4 1 3 &pcfg_pull_none>,
1816 <4 2 3 &pcfg_pull_none>,
1817 <4 3 3 &pcfg_pull_none>;
1818 };
1819 };
1820
1821 spdif {
1822 spdif_tx: spdif-tx {
1823 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;
1824 };
1825 };
1826 };
1827 };
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