2 * This file is dual-licensed: you can use it either under the terms
3 * of the GPL or the X11 license, at your option. Note that this dual
4 * licensing only applies to this file, and not this project as a
7 * a) This file is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of the
10 * License, or (at your option) any later version.
12 * This file is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 * b) Permission is hereby granted, free of charge, to any person
20 * obtaining a copy of this software and associated documentation
21 * files (the "Software"), to deal in the Software without
22 * restriction, including without limitation the rights to use,
23 * copy, modify, merge, publish, distribute, sublicense, and/or
24 * sell copies of the Software, and to permit persons to whom the
25 * Software is furnished to do so, subject to the following
28 * The above copyright notice and this permission notice shall be
29 * included in all copies or substantial portions of the Software.
31 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
32 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
33 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
34 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
35 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
36 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
37 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
38 * OTHER DEALINGS IN THE SOFTWARE.
41 #include <dt-bindings/gpio/gpio.h>
42 #include <dt-bindings/interrupt-controller/irq.h>
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/pinctrl/rockchip.h>
45 #include <dt-bindings/clock/rk3288-cru.h>
46 #include <dt-bindings/thermal/thermal.h>
47 #include <dt-bindings/power/rk3288-power.h>
48 #include <dt-bindings/soc/rockchip,boot-mode.h>
49 #include "skeleton.dtsi"
52 compatible = "rockchip,rk3288";
54 interrupt-parent = <&gic>;
79 compatible = "arm,cortex-a12-pmu";
80 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
81 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
82 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
83 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
84 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
90 enable-method = "rockchip,rk3066-smp";
91 rockchip,pmu = <&pmu>;
95 compatible = "arm,cortex-a12";
97 resets = <&cru SRST_CORE0>;
113 #cooling-cells = <2>; /* min followed by max */
114 clock-latency = <40000>;
115 clocks = <&cru ARMCLK>;
119 compatible = "arm,cortex-a12";
121 resets = <&cru SRST_CORE1>;
125 compatible = "arm,cortex-a12";
127 resets = <&cru SRST_CORE2>;
131 compatible = "arm,cortex-a12";
133 resets = <&cru SRST_CORE3>;
138 compatible = "simple-bus";
139 #address-cells = <1>;
143 dmac_peri: dma-controller@ff250000 {
144 compatible = "arm,pl330", "arm,primecell";
145 reg = <0xff250000 0x4000>;
146 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
147 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
149 arm,pl330-broken-no-flushp;
150 clocks = <&cru ACLK_DMAC2>;
151 clock-names = "apb_pclk";
154 dmac_bus_ns: dma-controller@ff600000 {
155 compatible = "arm,pl330", "arm,primecell";
156 reg = <0xff600000 0x4000>;
157 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
158 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
160 arm,pl330-broken-no-flushp;
161 clocks = <&cru ACLK_DMAC1>;
162 clock-names = "apb_pclk";
166 dmac_bus_s: dma-controller@ffb20000 {
167 compatible = "arm,pl330", "arm,primecell";
168 reg = <0xffb20000 0x4000>;
169 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
170 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
172 arm,pl330-broken-no-flushp;
173 clocks = <&cru ACLK_DMAC1>;
174 clock-names = "apb_pclk";
179 #address-cells = <1>;
184 * The rk3288 cannot use the memory area above 0xfe000000
185 * for dma operations for some reason. While there is
186 * probably a better solution available somewhere, we
187 * haven't found it yet and while devices with 2GB of ram
188 * are not affected, this issue prevents 4GB from booting.
189 * So to make these devices at least bootable, block
190 * this area for the time being until the real solution
193 dma-unusable@fe000000 {
194 reg = <0xfe000000 0x1000000>;
199 compatible = "fixed-clock";
200 clock-frequency = <24000000>;
201 clock-output-names = "xin24m";
206 compatible = "arm,armv7-timer";
207 arm,cpu-registers-not-fw-configured;
208 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
209 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
210 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
211 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
212 clock-frequency = <24000000>;
215 timer: timer@ff810000 {
216 compatible = "rockchip,rk3288-timer";
217 reg = <0xff810000 0x20>;
218 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
219 clocks = <&xin24m>, <&cru PCLK_TIMER>;
220 clock-names = "timer", "pclk";
224 compatible = "rockchip,display-subsystem";
225 ports = <&vopl_out>, <&vopb_out>;
228 sdmmc: dwmmc@ff0c0000 {
229 compatible = "rockchip,rk3288-dw-mshc";
230 clock-freq-min-max = <400000 150000000>;
231 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
232 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
233 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
234 fifo-depth = <0x100>;
235 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
236 reg = <0xff0c0000 0x4000>;
240 sdio0: dwmmc@ff0d0000 {
241 compatible = "rockchip,rk3288-dw-mshc";
242 clock-freq-min-max = <400000 150000000>;
243 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
244 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
245 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
246 fifo-depth = <0x100>;
247 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
248 reg = <0xff0d0000 0x4000>;
252 sdio1: dwmmc@ff0e0000 {
253 compatible = "rockchip,rk3288-dw-mshc";
254 clock-freq-min-max = <400000 150000000>;
255 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
256 <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
257 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
258 fifo-depth = <0x100>;
259 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
260 reg = <0xff0e0000 0x4000>;
264 emmc: dwmmc@ff0f0000 {
265 compatible = "rockchip,rk3288-dw-mshc";
266 clock-freq-min-max = <400000 150000000>;
267 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
268 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
269 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
270 fifo-depth = <0x100>;
271 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
272 reg = <0xff0f0000 0x4000>;
276 saradc: saradc@ff100000 {
277 compatible = "rockchip,saradc";
278 reg = <0xff100000 0x100>;
279 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
280 #io-channel-cells = <1>;
281 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
282 clock-names = "saradc", "apb_pclk";
283 resets = <&cru SRST_SARADC>;
284 reset-names = "saradc-apb";
289 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
290 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
291 clock-names = "spiclk", "apb_pclk";
292 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
293 dma-names = "tx", "rx";
294 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
295 pinctrl-names = "default";
296 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
297 reg = <0xff110000 0x1000>;
298 #address-cells = <1>;
304 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
305 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
306 clock-names = "spiclk", "apb_pclk";
307 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
308 dma-names = "tx", "rx";
309 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
310 pinctrl-names = "default";
311 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
312 reg = <0xff120000 0x1000>;
313 #address-cells = <1>;
319 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
320 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
321 clock-names = "spiclk", "apb_pclk";
322 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
323 dma-names = "tx", "rx";
324 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
325 pinctrl-names = "default";
326 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
327 reg = <0xff130000 0x1000>;
328 #address-cells = <1>;
334 compatible = "rockchip,rk3288-i2c";
335 reg = <0xff140000 0x1000>;
336 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
337 #address-cells = <1>;
340 clocks = <&cru PCLK_I2C1>;
341 pinctrl-names = "default";
342 pinctrl-0 = <&i2c1_xfer>;
347 compatible = "rockchip,rk3288-i2c";
348 reg = <0xff150000 0x1000>;
349 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
350 #address-cells = <1>;
353 clocks = <&cru PCLK_I2C3>;
354 pinctrl-names = "default";
355 pinctrl-0 = <&i2c3_xfer>;
360 compatible = "rockchip,rk3288-i2c";
361 reg = <0xff160000 0x1000>;
362 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
363 #address-cells = <1>;
366 clocks = <&cru PCLK_I2C4>;
367 pinctrl-names = "default";
368 pinctrl-0 = <&i2c4_xfer>;
373 compatible = "rockchip,rk3288-i2c";
374 reg = <0xff170000 0x1000>;
375 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
376 #address-cells = <1>;
379 clocks = <&cru PCLK_I2C5>;
380 pinctrl-names = "default";
381 pinctrl-0 = <&i2c5_xfer>;
385 uart0: serial@ff180000 {
386 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
387 reg = <0xff180000 0x100>;
388 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
391 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
392 clock-names = "baudclk", "apb_pclk";
393 pinctrl-names = "default";
394 pinctrl-0 = <&uart0_xfer>;
398 uart1: serial@ff190000 {
399 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
400 reg = <0xff190000 0x100>;
401 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
404 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
405 clock-names = "baudclk", "apb_pclk";
406 pinctrl-names = "default";
407 pinctrl-0 = <&uart1_xfer>;
411 uart2: serial@ff690000 {
412 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
413 reg = <0xff690000 0x100>;
414 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
417 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
418 clock-names = "baudclk", "apb_pclk";
419 pinctrl-names = "default";
420 pinctrl-0 = <&uart2_xfer>;
424 uart3: serial@ff1b0000 {
425 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
426 reg = <0xff1b0000 0x100>;
427 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
430 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
431 clock-names = "baudclk", "apb_pclk";
432 pinctrl-names = "default";
433 pinctrl-0 = <&uart3_xfer>;
437 uart4: serial@ff1c0000 {
438 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
439 reg = <0xff1c0000 0x100>;
440 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
443 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
444 clock-names = "baudclk", "apb_pclk";
445 pinctrl-names = "default";
446 pinctrl-0 = <&uart4_xfer>;
451 reserve_thermal: reserve_thermal {
452 polling-delay-passive = <1000>; /* milliseconds */
453 polling-delay = <5000>; /* milliseconds */
455 thermal-sensors = <&tsadc 0>;
458 cpu_thermal: cpu_thermal {
459 polling-delay-passive = <100>; /* milliseconds */
460 polling-delay = <5000>; /* milliseconds */
462 thermal-sensors = <&tsadc 1>;
465 cpu_alert0: cpu_alert0 {
466 temperature = <70000>; /* millicelsius */
467 hysteresis = <2000>; /* millicelsius */
470 cpu_alert1: cpu_alert1 {
471 temperature = <75000>; /* millicelsius */
472 hysteresis = <2000>; /* millicelsius */
476 temperature = <90000>; /* millicelsius */
477 hysteresis = <2000>; /* millicelsius */
484 trip = <&cpu_alert0>;
486 <&cpu0 THERMAL_NO_LIMIT 6>;
489 trip = <&cpu_alert1>;
491 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
496 gpu_thermal: gpu_thermal {
497 polling-delay-passive = <100>; /* milliseconds */
498 polling-delay = <5000>; /* milliseconds */
500 thermal-sensors = <&tsadc 2>;
503 gpu_alert0: gpu_alert0 {
504 temperature = <70000>; /* millicelsius */
505 hysteresis = <2000>; /* millicelsius */
509 temperature = <90000>; /* millicelsius */
510 hysteresis = <2000>; /* millicelsius */
517 trip = <&gpu_alert0>;
519 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
525 tsadc: tsadc@ff280000 {
526 compatible = "rockchip,rk3288-tsadc";
527 reg = <0xff280000 0x100>;
528 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
529 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
530 clock-names = "tsadc", "apb_pclk";
531 resets = <&cru SRST_TSADC>;
532 reset-names = "tsadc-apb";
533 pinctrl-names = "init", "default", "sleep";
534 pinctrl-0 = <&otp_gpio>;
535 pinctrl-1 = <&otp_out>;
536 pinctrl-2 = <&otp_gpio>;
537 #thermal-sensor-cells = <1>;
538 rockchip,hw-tshut-temp = <95000>;
542 gmac: ethernet@ff290000 {
543 compatible = "rockchip,rk3288-gmac";
544 reg = <0xff290000 0x10000>;
545 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
546 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
547 interrupt-names = "macirq", "eth_wake_irq";
548 rockchip,grf = <&grf>;
549 clocks = <&cru SCLK_MAC>,
550 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
551 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
552 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
553 clock-names = "stmmaceth",
554 "mac_clk_rx", "mac_clk_tx",
555 "clk_mac_ref", "clk_mac_refout",
556 "aclk_mac", "pclk_mac";
557 resets = <&cru SRST_MAC>;
558 reset-names = "stmmaceth";
562 usb_host0_ehci: usb@ff500000 {
563 compatible = "generic-ehci";
564 reg = <0xff500000 0x100>;
565 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
566 clocks = <&cru HCLK_USBHOST0>;
567 clock-names = "usbhost";
573 /* NOTE: ohci@ff520000 doesn't actually work on hardware */
575 usb_host1: usb@ff540000 {
576 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
578 reg = <0xff540000 0x40000>;
579 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
580 clocks = <&cru HCLK_USBHOST1>;
584 phy-names = "usb2-phy";
588 usb_otg: usb@ff580000 {
589 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
591 reg = <0xff580000 0x40000>;
592 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
593 clocks = <&cru HCLK_OTG0>;
596 g-np-tx-fifo-size = <16>;
597 g-rx-fifo-size = <275>;
598 g-tx-fifo-size = <256 128 128 64 64 32>;
600 phy-names = "usb2-phy";
604 usb_hsic: usb@ff5c0000 {
605 compatible = "generic-ehci";
606 reg = <0xff5c0000 0x100>;
607 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
608 clocks = <&cru HCLK_HSIC>;
609 clock-names = "usbhost";
614 compatible = "rockchip,rk3288-i2c";
615 reg = <0xff650000 0x1000>;
616 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
617 #address-cells = <1>;
620 clocks = <&cru PCLK_I2C0>;
621 pinctrl-names = "default";
622 pinctrl-0 = <&i2c0_xfer>;
627 compatible = "rockchip,rk3288-i2c";
628 reg = <0xff660000 0x1000>;
629 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
630 #address-cells = <1>;
633 clocks = <&cru PCLK_I2C2>;
634 pinctrl-names = "default";
635 pinctrl-0 = <&i2c2_xfer>;
640 compatible = "rockchip,rk3288-pwm";
641 reg = <0xff680000 0x10>;
643 pinctrl-names = "default";
644 pinctrl-0 = <&pwm0_pin>;
645 clocks = <&cru PCLK_PWM>;
651 compatible = "rockchip,rk3288-pwm";
652 reg = <0xff680010 0x10>;
654 pinctrl-names = "default";
655 pinctrl-0 = <&pwm1_pin>;
656 clocks = <&cru PCLK_PWM>;
662 compatible = "rockchip,rk3288-pwm";
663 reg = <0xff680020 0x10>;
665 pinctrl-names = "default";
666 pinctrl-0 = <&pwm2_pin>;
667 clocks = <&cru PCLK_PWM>;
673 compatible = "rockchip,rk3288-pwm";
674 reg = <0xff680030 0x10>;
676 pinctrl-names = "default";
677 pinctrl-0 = <&pwm3_pin>;
678 clocks = <&cru PCLK_PWM>;
683 bus_intmem@ff700000 {
684 compatible = "mmio-sram";
685 reg = <0xff700000 0x18000>;
686 #address-cells = <1>;
688 ranges = <0 0xff700000 0x18000>;
690 compatible = "rockchip,rk3066-smp-sram";
696 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
697 reg = <0xff720000 0x1000>;
700 pmu: power-management@ff730000 {
701 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
702 reg = <0xff730000 0x100>;
704 power: power-controller {
705 compatible = "rockchip,rk3288-power-controller";
706 #power-domain-cells = <1>;
707 #address-cells = <1>;
710 assigned-clocks = <&cru SCLK_EDP_24M>;
711 assigned-clock-parents = <&xin24m>;
714 * Note: Although SCLK_* are the working clocks
715 * of device without including on the NOC, needed for
718 * The clocks on the which NOC:
719 * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
720 * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
721 * ACLK_RGA is on ACLK_RGA_NIU.
722 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
724 * Which clock are device clocks:
726 * *_IEP IEP:Image Enhancement Processor
727 * *_ISP ISP:Image Signal Processing
728 * *_VIP VIP:Video Input Processor
729 * *_VOP* VOP:Visual Output Processor
736 pd_vio@RK3288_PD_VIO {
737 reg = <RK3288_PD_VIO>;
738 clocks = <&cru ACLK_IEP>,
752 <&cru PCLK_EDP_CTRL>,
753 <&cru PCLK_HDMI_CTRL>,
754 <&cru PCLK_LVDS_PHY>,
755 <&cru PCLK_MIPI_CSI>,
756 <&cru PCLK_MIPI_DSI0>,
757 <&cru PCLK_MIPI_DSI1>,
766 * Note: The following 3 are HEVC(H.265) clocks,
767 * and on the ACLK_HEVC_NIU (NOC).
769 pd_hevc@RK3288_PD_HEVC {
770 reg = <RK3288_PD_HEVC>;
771 clocks = <&cru ACLK_HEVC>,
772 <&cru SCLK_HEVC_CABAC>,
773 <&cru SCLK_HEVC_CORE>;
777 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
778 * (video endecoder & decoder) clocks that on the
779 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
781 pd_video@RK3288_PD_VIDEO {
782 reg = <RK3288_PD_VIDEO>;
783 clocks = <&cru ACLK_VCODEC>,
788 * Note: ACLK_GPU is the GPU clock,
789 * and on the ACLK_GPU_NIU (NOC).
791 pd_gpu@RK3288_PD_GPU {
792 reg = <RK3288_PD_GPU>;
793 clocks = <&cru ACLK_GPU>;
798 compatible = "syscon-reboot-mode";
800 mode-normal = <BOOT_NORMAL>;
801 mode-recovery = <BOOT_RECOVERY>;
802 mode-bootloader = <BOOT_FASTBOOT>;
803 mode-loader = <BOOT_BL_DOWNLOAD>;
807 sgrf: syscon@ff740000 {
808 compatible = "rockchip,rk3288-sgrf", "syscon";
809 reg = <0xff740000 0x1000>;
812 cru: clock-controller@ff760000 {
813 compatible = "rockchip,rk3288-cru";
814 reg = <0xff760000 0x1000>;
815 rockchip,grf = <&grf>;
818 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
819 <&cru PLL_NPLL>, <&cru ACLK_CPU>,
820 <&cru HCLK_CPU>, <&cru PCLK_CPU>,
821 <&cru ACLK_PERI>, <&cru HCLK_PERI>,
823 assigned-clock-rates = <594000000>, <400000000>,
824 <500000000>, <300000000>,
825 <150000000>, <75000000>,
826 <300000000>, <150000000>,
830 grf: syscon@ff770000 {
831 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
832 reg = <0xff770000 0x1000>;
835 compatible = "rockchip,rk3288-dp-phy";
836 clocks = <&cru SCLK_EDP_24M>;
842 io_domains: io-domains {
843 compatible = "rockchip,rk3288-io-voltage-domain";
848 compatible = "rockchip,rk3288-usb-phy";
849 #address-cells = <1>;
853 usbphy0: usb-phy@320 {
856 clocks = <&cru SCLK_OTGPHY0>;
857 clock-names = "phyclk";
861 usbphy1: usb-phy@334 {
864 clocks = <&cru SCLK_OTGPHY1>;
865 clock-names = "phyclk";
869 usbphy2: usb-phy@348 {
872 clocks = <&cru SCLK_OTGPHY2>;
873 clock-names = "phyclk";
879 wdt: watchdog@ff800000 {
880 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
881 reg = <0xff800000 0x100>;
882 clocks = <&cru PCLK_WDT>;
883 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
887 spdif: sound@ff88b0000 {
888 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
889 reg = <0xff8b0000 0x10000>;
890 #sound-dai-cells = <0>;
891 clock-names = "hclk", "mclk";
892 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
893 dmas = <&dmac_bus_s 3>;
895 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
896 pinctrl-names = "default";
897 pinctrl-0 = <&spdif_tx>;
898 rockchip,grf = <&grf>;
903 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
904 reg = <0xff890000 0x10000>;
905 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
906 #address-cells = <1>;
908 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
909 dma-names = "tx", "rx";
910 clock-names = "i2s_hclk", "i2s_clk";
911 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
912 pinctrl-names = "default";
913 pinctrl-0 = <&i2s0_bus>;
914 rockchip,playback-channels = <8>;
915 rockchip,capture-channels = <2>;
919 crypto: cypto-controller@ff8a0000 {
920 compatible = "rockchip,rk3288-crypto";
921 reg = <0xff8a0000 0x4000>;
922 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
923 clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>,
924 <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>;
925 clock-names = "aclk", "hclk", "sclk", "apb_pclk";
926 resets = <&cru SRST_CRYPTO>;
927 reset-names = "crypto-rst";
932 compatible = "rockchip,rk3288-vop";
933 reg = <0xff930000 0x19c>;
934 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
935 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
936 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
937 power-domains = <&power RK3288_PD_VIO>;
938 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
939 reset-names = "axi", "ahb", "dclk";
940 iommus = <&vopb_mmu>;
944 #address-cells = <1>;
947 vopb_out_hdmi: endpoint@0 {
949 remote-endpoint = <&hdmi_in_vopb>;
952 vopb_out_edp: endpoint@1 {
954 remote-endpoint = <&edp_in_vopb>;
957 vopb_out_mipi: endpoint@2 {
959 remote-endpoint = <&mipi_in_vopb>;
964 vopb_mmu: iommu@ff930300 {
965 compatible = "rockchip,iommu";
966 reg = <0xff930300 0x100>;
967 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
968 interrupt-names = "vopb_mmu";
969 power-domains = <&power RK3288_PD_VIO>;
975 compatible = "rockchip,rk3288-vop";
976 reg = <0xff940000 0x19c>;
977 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
978 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
979 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
980 power-domains = <&power RK3288_PD_VIO>;
981 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
982 reset-names = "axi", "ahb", "dclk";
983 iommus = <&vopl_mmu>;
987 #address-cells = <1>;
990 vopl_out_hdmi: endpoint@0 {
992 remote-endpoint = <&hdmi_in_vopl>;
995 vopl_out_edp: endpoint@1 {
997 remote-endpoint = <&edp_in_vopl>;
1000 vopl_out_mipi: endpoint@2 {
1002 remote-endpoint = <&mipi_in_vopl>;
1007 vopl_mmu: iommu@ff940300 {
1008 compatible = "rockchip,iommu";
1009 reg = <0xff940300 0x100>;
1010 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1011 interrupt-names = "vopl_mmu";
1012 power-domains = <&power RK3288_PD_VIO>;
1014 status = "disabled";
1017 mipi_dsi: mipi@ff960000 {
1018 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
1019 reg = <0xff960000 0x4000>;
1020 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1021 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
1022 clock-names = "ref", "pclk";
1023 power-domains = <&power RK3288_PD_VIO>;
1024 rockchip,grf = <&grf>;
1025 #address-cells = <1>;
1027 status = "disabled";
1031 #address-cells = <1>;
1033 mipi_in_vopb: endpoint@0 {
1035 remote-endpoint = <&vopb_out_mipi>;
1037 mipi_in_vopl: endpoint@1 {
1039 remote-endpoint = <&vopl_out_mipi>;
1046 compatible = "rockchip,rk3288-dp";
1047 reg = <0xff970000 0x4000>;
1048 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1049 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1050 clock-names = "dp", "pclk";
1053 resets = <&cru SRST_EDP>;
1055 rockchip,grf = <&grf>;
1056 status = "disabled";
1059 #address-cells = <1>;
1063 #address-cells = <1>;
1065 edp_in_vopb: endpoint@0 {
1067 remote-endpoint = <&vopb_out_edp>;
1069 edp_in_vopl: endpoint@1 {
1071 remote-endpoint = <&vopl_out_edp>;
1077 hdmi: hdmi@ff980000 {
1078 compatible = "rockchip,rk3288-dw-hdmi";
1079 reg = <0xff980000 0x20000>;
1081 rockchip,grf = <&grf>;
1082 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1083 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
1084 clock-names = "iahb", "isfr";
1085 power-domains = <&power RK3288_PD_VIO>;
1086 status = "disabled";
1090 #address-cells = <1>;
1092 hdmi_in_vopb: endpoint@0 {
1094 remote-endpoint = <&vopb_out_hdmi>;
1096 hdmi_in_vopl: endpoint@1 {
1098 remote-endpoint = <&vopl_out_hdmi>;
1104 gic: interrupt-controller@ffc01000 {
1105 compatible = "arm,gic-400";
1106 interrupt-controller;
1107 #interrupt-cells = <3>;
1108 #address-cells = <0>;
1110 reg = <0xffc01000 0x1000>,
1111 <0xffc02000 0x1000>,
1112 <0xffc04000 0x2000>,
1113 <0xffc06000 0x2000>;
1114 interrupts = <GIC_PPI 9 0xf04>;
1117 efuse: efuse@ffb40000 {
1118 compatible = "rockchip,rockchip-efuse";
1119 reg = <0xffb40000 0x20>;
1120 #address-cells = <1>;
1122 clocks = <&cru PCLK_EFUSE256>;
1123 clock-names = "pclk_efuse";
1125 cpu_leakage: cpu_leakage@17 {
1131 compatible = "rockchip,rk3288-pinctrl";
1132 rockchip,grf = <&grf>;
1133 rockchip,pmu = <&pmu>;
1134 #address-cells = <1>;
1138 gpio0: gpio0@ff750000 {
1139 compatible = "rockchip,gpio-bank";
1140 reg = <0xff750000 0x100>;
1141 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1142 clocks = <&cru PCLK_GPIO0>;
1147 interrupt-controller;
1148 #interrupt-cells = <2>;
1151 gpio1: gpio1@ff780000 {
1152 compatible = "rockchip,gpio-bank";
1153 reg = <0xff780000 0x100>;
1154 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1155 clocks = <&cru PCLK_GPIO1>;
1160 interrupt-controller;
1161 #interrupt-cells = <2>;
1164 gpio2: gpio2@ff790000 {
1165 compatible = "rockchip,gpio-bank";
1166 reg = <0xff790000 0x100>;
1167 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1168 clocks = <&cru PCLK_GPIO2>;
1173 interrupt-controller;
1174 #interrupt-cells = <2>;
1177 gpio3: gpio3@ff7a0000 {
1178 compatible = "rockchip,gpio-bank";
1179 reg = <0xff7a0000 0x100>;
1180 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1181 clocks = <&cru PCLK_GPIO3>;
1186 interrupt-controller;
1187 #interrupt-cells = <2>;
1190 gpio4: gpio4@ff7b0000 {
1191 compatible = "rockchip,gpio-bank";
1192 reg = <0xff7b0000 0x100>;
1193 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1194 clocks = <&cru PCLK_GPIO4>;
1199 interrupt-controller;
1200 #interrupt-cells = <2>;
1203 gpio5: gpio5@ff7c0000 {
1204 compatible = "rockchip,gpio-bank";
1205 reg = <0xff7c0000 0x100>;
1206 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1207 clocks = <&cru PCLK_GPIO5>;
1212 interrupt-controller;
1213 #interrupt-cells = <2>;
1216 gpio6: gpio6@ff7d0000 {
1217 compatible = "rockchip,gpio-bank";
1218 reg = <0xff7d0000 0x100>;
1219 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1220 clocks = <&cru PCLK_GPIO6>;
1225 interrupt-controller;
1226 #interrupt-cells = <2>;
1229 gpio7: gpio7@ff7e0000 {
1230 compatible = "rockchip,gpio-bank";
1231 reg = <0xff7e0000 0x100>;
1232 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1233 clocks = <&cru PCLK_GPIO7>;
1238 interrupt-controller;
1239 #interrupt-cells = <2>;
1242 gpio8: gpio8@ff7f0000 {
1243 compatible = "rockchip,gpio-bank";
1244 reg = <0xff7f0000 0x100>;
1245 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1246 clocks = <&cru PCLK_GPIO8>;
1251 interrupt-controller;
1252 #interrupt-cells = <2>;
1256 hdmi_ddc: hdmi-ddc {
1257 rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>,
1258 <7 20 RK_FUNC_2 &pcfg_pull_none>;
1262 pcfg_pull_up: pcfg-pull-up {
1266 pcfg_pull_down: pcfg-pull-down {
1270 pcfg_pull_none: pcfg-pull-none {
1274 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1276 drive-strength = <12>;
1280 global_pwroff: global-pwroff {
1281 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1284 ddrio_pwroff: ddrio-pwroff {
1285 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1288 ddr0_retention: ddr0-retention {
1289 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1292 ddr1_retention: ddr1-retention {
1293 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1299 rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>;
1304 i2c0_xfer: i2c0-xfer {
1305 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1306 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1311 i2c1_xfer: i2c1-xfer {
1312 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1313 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1318 i2c2_xfer: i2c2-xfer {
1319 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1320 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1325 i2c3_xfer: i2c3-xfer {
1326 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1327 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1332 i2c4_xfer: i2c4-xfer {
1333 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1334 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1339 i2c5_xfer: i2c5-xfer {
1340 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1341 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1346 i2s0_bus: i2s0-bus {
1347 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1348 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1349 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1350 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1351 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1352 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1357 sdmmc_clk: sdmmc-clk {
1358 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1361 sdmmc_cmd: sdmmc-cmd {
1362 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1365 sdmmc_cd: sdmmc-cd {
1366 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1369 sdmmc_bus1: sdmmc-bus1 {
1370 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1373 sdmmc_bus4: sdmmc-bus4 {
1374 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1375 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1376 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1377 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1382 sdio0_bus1: sdio0-bus1 {
1383 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1386 sdio0_bus4: sdio0-bus4 {
1387 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1388 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1389 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1390 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1393 sdio0_cmd: sdio0-cmd {
1394 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1397 sdio0_clk: sdio0-clk {
1398 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1401 sdio0_cd: sdio0-cd {
1402 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1405 sdio0_wp: sdio0-wp {
1406 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1409 sdio0_pwr: sdio0-pwr {
1410 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1413 sdio0_bkpwr: sdio0-bkpwr {
1414 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1417 sdio0_int: sdio0-int {
1418 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1423 sdio1_bus1: sdio1-bus1 {
1424 rockchip,pins = <3 24 4 &pcfg_pull_up>;
1427 sdio1_bus4: sdio1-bus4 {
1428 rockchip,pins = <3 24 4 &pcfg_pull_up>,
1429 <3 25 4 &pcfg_pull_up>,
1430 <3 26 4 &pcfg_pull_up>,
1431 <3 27 4 &pcfg_pull_up>;
1434 sdio1_cd: sdio1-cd {
1435 rockchip,pins = <3 28 4 &pcfg_pull_up>;
1438 sdio1_wp: sdio1-wp {
1439 rockchip,pins = <3 29 4 &pcfg_pull_up>;
1442 sdio1_bkpwr: sdio1-bkpwr {
1443 rockchip,pins = <3 30 4 &pcfg_pull_up>;
1446 sdio1_int: sdio1-int {
1447 rockchip,pins = <3 31 4 &pcfg_pull_up>;
1450 sdio1_cmd: sdio1-cmd {
1451 rockchip,pins = <4 6 4 &pcfg_pull_up>;
1454 sdio1_clk: sdio1-clk {
1455 rockchip,pins = <4 7 4 &pcfg_pull_none>;
1458 sdio1_pwr: sdio1-pwr {
1459 rockchip,pins = <4 9 4 &pcfg_pull_up>;
1464 emmc_clk: emmc-clk {
1465 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1468 emmc_cmd: emmc-cmd {
1469 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1472 emmc_pwr: emmc-pwr {
1473 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1476 emmc_bus1: emmc-bus1 {
1477 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1480 emmc_bus4: emmc-bus4 {
1481 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1482 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1483 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1484 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1487 emmc_bus8: emmc-bus8 {
1488 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1489 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1490 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1491 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1492 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1493 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1494 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1495 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1500 spi0_clk: spi0-clk {
1501 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1503 spi0_cs0: spi0-cs0 {
1504 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1507 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1510 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1512 spi0_cs1: spi0-cs1 {
1513 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1517 spi1_clk: spi1-clk {
1518 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1520 spi1_cs0: spi1-cs0 {
1521 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1524 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1527 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1532 spi2_cs1: spi2-cs1 {
1533 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1535 spi2_clk: spi2-clk {
1536 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1538 spi2_cs0: spi2-cs0 {
1539 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1542 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1545 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1550 uart0_xfer: uart0-xfer {
1551 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1552 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1555 uart0_cts: uart0-cts {
1556 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>;
1559 uart0_rts: uart0-rts {
1560 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1565 uart1_xfer: uart1-xfer {
1566 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1567 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1570 uart1_cts: uart1-cts {
1571 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>;
1574 uart1_rts: uart1-rts {
1575 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1580 uart2_xfer: uart2-xfer {
1581 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1582 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1584 /* no rts / cts for uart2 */
1588 uart3_xfer: uart3-xfer {
1589 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1590 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1593 uart3_cts: uart3-cts {
1594 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>;
1597 uart3_rts: uart3-rts {
1598 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1603 uart4_xfer: uart4-xfer {
1604 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1605 <5 13 3 &pcfg_pull_none>;
1608 uart4_cts: uart4-cts {
1609 rockchip,pins = <5 14 3 &pcfg_pull_up>;
1612 uart4_rts: uart4-rts {
1613 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1618 otp_gpio: otp-gpio {
1619 rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
1623 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1628 pwm0_pin: pwm0-pin {
1629 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1634 pwm1_pin: pwm1-pin {
1635 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1640 pwm2_pin: pwm2-pin {
1641 rockchip,pins = <7 22 3 &pcfg_pull_none>;
1646 pwm3_pin: pwm3-pin {
1647 rockchip,pins = <7 23 3 &pcfg_pull_none>;
1652 rgmii_pins: rgmii-pins {
1653 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1654 <3 31 3 &pcfg_pull_none>,
1655 <3 26 3 &pcfg_pull_none>,
1656 <3 27 3 &pcfg_pull_none>,
1657 <3 28 3 &pcfg_pull_none_12ma>,
1658 <3 29 3 &pcfg_pull_none_12ma>,
1659 <3 24 3 &pcfg_pull_none_12ma>,
1660 <3 25 3 &pcfg_pull_none_12ma>,
1661 <4 0 3 &pcfg_pull_none>,
1662 <4 5 3 &pcfg_pull_none>,
1663 <4 6 3 &pcfg_pull_none>,
1664 <4 9 3 &pcfg_pull_none_12ma>,
1665 <4 4 3 &pcfg_pull_none_12ma>,
1666 <4 1 3 &pcfg_pull_none>,
1667 <4 3 3 &pcfg_pull_none>;
1670 rmii_pins: rmii-pins {
1671 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1672 <3 31 3 &pcfg_pull_none>,
1673 <3 28 3 &pcfg_pull_none>,
1674 <3 29 3 &pcfg_pull_none>,
1675 <4 0 3 &pcfg_pull_none>,
1676 <4 5 3 &pcfg_pull_none>,
1677 <4 4 3 &pcfg_pull_none>,
1678 <4 1 3 &pcfg_pull_none>,
1679 <4 2 3 &pcfg_pull_none>,
1680 <4 3 3 &pcfg_pull_none>;
1685 spdif_tx: spdif-tx {
1686 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;