2 * This file is dual-licensed: you can use it either under the terms
3 * of the GPL or the X11 license, at your option. Note that this dual
4 * licensing only applies to this file, and not this project as a
7 * a) This file is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of the
10 * License, or (at your option) any later version.
12 * This file is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 * b) Permission is hereby granted, free of charge, to any person
20 * obtaining a copy of this software and associated documentation
21 * files (the "Software"), to deal in the Software without
22 * restriction, including without limitation the rights to use,
23 * copy, modify, merge, publish, distribute, sublicense, and/or
24 * sell copies of the Software, and to permit persons to whom the
25 * Software is furnished to do so, subject to the following
28 * The above copyright notice and this permission notice shall be
29 * included in all copies or substantial portions of the Software.
31 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
32 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
33 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
34 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
35 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
36 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
37 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
38 * OTHER DEALINGS IN THE SOFTWARE.
41 #include <dt-bindings/gpio/gpio.h>
42 #include <dt-bindings/interrupt-controller/irq.h>
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/pinctrl/rockchip.h>
45 #include <dt-bindings/clock/rk3288-cru.h>
46 #include <dt-bindings/power/rk3288-power.h>
47 #include <dt-bindings/thermal/thermal.h>
48 #include <dt-bindings/power/rk3288-power.h>
49 #include <dt-bindings/soc/rockchip,boot-mode.h>
55 compatible = "rockchip,rk3288";
57 interrupt-parent = <&gic>;
82 compatible = "arm,cortex-a12-pmu";
83 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
84 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
85 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
86 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
87 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
93 enable-method = "rockchip,rk3066-smp";
94 rockchip,pmu = <&pmu>;
98 compatible = "arm,cortex-a12";
100 resets = <&cru SRST_CORE0>;
116 #cooling-cells = <2>; /* min followed by max */
117 clock-latency = <40000>;
118 clocks = <&cru ARMCLK>;
122 compatible = "arm,cortex-a12";
124 resets = <&cru SRST_CORE1>;
128 compatible = "arm,cortex-a12";
130 resets = <&cru SRST_CORE2>;
134 compatible = "arm,cortex-a12";
136 resets = <&cru SRST_CORE3>;
141 compatible = "simple-bus";
142 #address-cells = <1>;
146 dmac_peri: dma-controller@ff250000 {
147 compatible = "arm,pl330", "arm,primecell";
148 reg = <0xff250000 0x4000>;
149 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
150 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
152 arm,pl330-broken-no-flushp;
153 clocks = <&cru ACLK_DMAC2>;
154 clock-names = "apb_pclk";
157 dmac_bus_ns: dma-controller@ff600000 {
158 compatible = "arm,pl330", "arm,primecell";
159 reg = <0xff600000 0x4000>;
160 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
161 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
163 arm,pl330-broken-no-flushp;
164 clocks = <&cru ACLK_DMAC1>;
165 clock-names = "apb_pclk";
169 dmac_bus_s: dma-controller@ffb20000 {
170 compatible = "arm,pl330", "arm,primecell";
171 reg = <0xffb20000 0x4000>;
172 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
173 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
175 arm,pl330-broken-no-flushp;
176 clocks = <&cru ACLK_DMAC1>;
177 clock-names = "apb_pclk";
182 #address-cells = <1>;
187 * The rk3288 cannot use the memory area above 0xfe000000
188 * for dma operations for some reason. While there is
189 * probably a better solution available somewhere, we
190 * haven't found it yet and while devices with 2GB of ram
191 * are not affected, this issue prevents 4GB from booting.
192 * So to make these devices at least bootable, block
193 * this area for the time being until the real solution
196 dma-unusable@fe000000 {
197 reg = <0xfe000000 0x1000000>;
202 compatible = "fixed-clock";
203 clock-frequency = <24000000>;
204 clock-output-names = "xin24m";
209 compatible = "arm,armv7-timer";
210 arm,cpu-registers-not-fw-configured;
211 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
212 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
213 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
214 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
215 clock-frequency = <24000000>;
218 timer: timer@ff810000 {
219 compatible = "rockchip,rk3288-timer";
220 reg = <0xff810000 0x20>;
221 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
222 clocks = <&xin24m>, <&cru PCLK_TIMER>;
223 clock-names = "timer", "pclk";
227 compatible = "rockchip,display-subsystem";
228 ports = <&vopl_out>, <&vopb_out>;
231 sdmmc: dwmmc@ff0c0000 {
232 compatible = "rockchip,rk3288-dw-mshc";
233 max-frequency = <150000000>;
234 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
235 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
236 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
237 fifo-depth = <0x100>;
238 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
239 reg = <0xff0c0000 0x4000>;
240 resets = <&cru SRST_MMC0>;
241 reset-names = "reset";
245 sdio0: dwmmc@ff0d0000 {
246 compatible = "rockchip,rk3288-dw-mshc";
247 max-frequency = <150000000>;
248 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
249 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
250 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
251 fifo-depth = <0x100>;
252 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
253 reg = <0xff0d0000 0x4000>;
254 resets = <&cru SRST_SDIO0>;
255 reset-names = "reset";
259 sdio1: dwmmc@ff0e0000 {
260 compatible = "rockchip,rk3288-dw-mshc";
261 max-frequency = <150000000>;
262 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
263 <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
264 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
265 fifo-depth = <0x100>;
266 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
267 reg = <0xff0e0000 0x4000>;
268 resets = <&cru SRST_SDIO1>;
269 reset-names = "reset";
273 emmc: dwmmc@ff0f0000 {
274 compatible = "rockchip,rk3288-dw-mshc";
275 max-frequency = <150000000>;
276 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
277 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
278 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
279 fifo-depth = <0x100>;
280 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
281 reg = <0xff0f0000 0x4000>;
282 resets = <&cru SRST_EMMC>;
283 reset-names = "reset";
287 saradc: saradc@ff100000 {
288 compatible = "rockchip,saradc";
289 reg = <0xff100000 0x100>;
290 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
291 #io-channel-cells = <1>;
292 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
293 clock-names = "saradc", "apb_pclk";
294 resets = <&cru SRST_SARADC>;
295 reset-names = "saradc-apb";
300 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
301 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
302 clock-names = "spiclk", "apb_pclk";
303 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
304 dma-names = "tx", "rx";
305 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
306 pinctrl-names = "default";
307 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
308 reg = <0xff110000 0x1000>;
309 #address-cells = <1>;
315 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
316 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
317 clock-names = "spiclk", "apb_pclk";
318 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
319 dma-names = "tx", "rx";
320 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
321 pinctrl-names = "default";
322 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
323 reg = <0xff120000 0x1000>;
324 #address-cells = <1>;
330 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
331 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
332 clock-names = "spiclk", "apb_pclk";
333 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
334 dma-names = "tx", "rx";
335 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
336 pinctrl-names = "default";
337 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
338 reg = <0xff130000 0x1000>;
339 #address-cells = <1>;
345 compatible = "rockchip,rk3288-i2c";
346 reg = <0xff140000 0x1000>;
347 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
348 #address-cells = <1>;
351 clocks = <&cru PCLK_I2C1>;
352 pinctrl-names = "default";
353 pinctrl-0 = <&i2c1_xfer>;
358 compatible = "rockchip,rk3288-i2c";
359 reg = <0xff150000 0x1000>;
360 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
361 #address-cells = <1>;
364 clocks = <&cru PCLK_I2C3>;
365 pinctrl-names = "default";
366 pinctrl-0 = <&i2c3_xfer>;
371 compatible = "rockchip,rk3288-i2c";
372 reg = <0xff160000 0x1000>;
373 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
374 #address-cells = <1>;
377 clocks = <&cru PCLK_I2C4>;
378 pinctrl-names = "default";
379 pinctrl-0 = <&i2c4_xfer>;
384 compatible = "rockchip,rk3288-i2c";
385 reg = <0xff170000 0x1000>;
386 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
387 #address-cells = <1>;
390 clocks = <&cru PCLK_I2C5>;
391 pinctrl-names = "default";
392 pinctrl-0 = <&i2c5_xfer>;
396 uart0: serial@ff180000 {
397 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
398 reg = <0xff180000 0x100>;
399 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
402 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
403 clock-names = "baudclk", "apb_pclk";
404 pinctrl-names = "default";
405 pinctrl-0 = <&uart0_xfer>;
409 uart1: serial@ff190000 {
410 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
411 reg = <0xff190000 0x100>;
412 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
415 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
416 clock-names = "baudclk", "apb_pclk";
417 pinctrl-names = "default";
418 pinctrl-0 = <&uart1_xfer>;
422 uart2: serial@ff690000 {
423 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
424 reg = <0xff690000 0x100>;
425 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
428 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
429 clock-names = "baudclk", "apb_pclk";
430 pinctrl-names = "default";
431 pinctrl-0 = <&uart2_xfer>;
435 uart3: serial@ff1b0000 {
436 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
437 reg = <0xff1b0000 0x100>;
438 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
441 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
442 clock-names = "baudclk", "apb_pclk";
443 pinctrl-names = "default";
444 pinctrl-0 = <&uart3_xfer>;
448 uart4: serial@ff1c0000 {
449 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
450 reg = <0xff1c0000 0x100>;
451 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
454 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
455 clock-names = "baudclk", "apb_pclk";
456 pinctrl-names = "default";
457 pinctrl-0 = <&uart4_xfer>;
462 reserve_thermal: reserve_thermal {
463 polling-delay-passive = <1000>; /* milliseconds */
464 polling-delay = <5000>; /* milliseconds */
466 thermal-sensors = <&tsadc 0>;
469 cpu_thermal: cpu_thermal {
470 polling-delay-passive = <100>; /* milliseconds */
471 polling-delay = <5000>; /* milliseconds */
473 thermal-sensors = <&tsadc 1>;
476 cpu_alert0: cpu_alert0 {
477 temperature = <70000>; /* millicelsius */
478 hysteresis = <2000>; /* millicelsius */
481 cpu_alert1: cpu_alert1 {
482 temperature = <75000>; /* millicelsius */
483 hysteresis = <2000>; /* millicelsius */
487 temperature = <90000>; /* millicelsius */
488 hysteresis = <2000>; /* millicelsius */
495 trip = <&cpu_alert0>;
497 <&cpu0 THERMAL_NO_LIMIT 6>;
500 trip = <&cpu_alert1>;
502 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
507 gpu_thermal: gpu_thermal {
508 polling-delay-passive = <100>; /* milliseconds */
509 polling-delay = <5000>; /* milliseconds */
511 thermal-sensors = <&tsadc 2>;
514 gpu_alert0: gpu_alert0 {
515 temperature = <70000>; /* millicelsius */
516 hysteresis = <2000>; /* millicelsius */
520 temperature = <90000>; /* millicelsius */
521 hysteresis = <2000>; /* millicelsius */
528 trip = <&gpu_alert0>;
530 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
536 tsadc: tsadc@ff280000 {
537 compatible = "rockchip,rk3288-tsadc";
538 reg = <0xff280000 0x100>;
539 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
540 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
541 clock-names = "tsadc", "apb_pclk";
542 resets = <&cru SRST_TSADC>;
543 reset-names = "tsadc-apb";
544 pinctrl-names = "init", "default", "sleep";
545 pinctrl-0 = <&otp_gpio>;
546 pinctrl-1 = <&otp_out>;
547 pinctrl-2 = <&otp_gpio>;
548 #thermal-sensor-cells = <1>;
549 rockchip,hw-tshut-temp = <95000>;
553 gmac: ethernet@ff290000 {
554 compatible = "rockchip,rk3288-gmac";
555 reg = <0xff290000 0x10000>;
556 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
557 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
558 interrupt-names = "macirq", "eth_wake_irq";
559 rockchip,grf = <&grf>;
560 clocks = <&cru SCLK_MAC>,
561 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
562 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
563 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
564 clock-names = "stmmaceth",
565 "mac_clk_rx", "mac_clk_tx",
566 "clk_mac_ref", "clk_mac_refout",
567 "aclk_mac", "pclk_mac";
568 resets = <&cru SRST_MAC>;
569 reset-names = "stmmaceth";
573 usb_host0_ehci: usb@ff500000 {
574 compatible = "generic-ehci";
575 reg = <0xff500000 0x100>;
576 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
577 clocks = <&cru HCLK_USBHOST0>;
578 clock-names = "usbhost";
584 /* NOTE: ohci@ff520000 doesn't actually work on hardware */
586 usb_host1: usb@ff540000 {
587 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
589 reg = <0xff540000 0x40000>;
590 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
591 clocks = <&cru HCLK_USBHOST1>;
595 phy-names = "usb2-phy";
599 usb_otg: usb@ff580000 {
600 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
602 reg = <0xff580000 0x40000>;
603 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
604 clocks = <&cru HCLK_OTG0>;
607 g-np-tx-fifo-size = <16>;
608 g-rx-fifo-size = <275>;
609 g-tx-fifo-size = <256 128 128 64 64 32>;
611 phy-names = "usb2-phy";
615 usb_hsic: usb@ff5c0000 {
616 compatible = "generic-ehci";
617 reg = <0xff5c0000 0x100>;
618 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
619 clocks = <&cru HCLK_HSIC>;
620 clock-names = "usbhost";
625 compatible = "rockchip,rk3288-i2c";
626 reg = <0xff650000 0x1000>;
627 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
628 #address-cells = <1>;
631 clocks = <&cru PCLK_I2C0>;
632 pinctrl-names = "default";
633 pinctrl-0 = <&i2c0_xfer>;
638 compatible = "rockchip,rk3288-i2c";
639 reg = <0xff660000 0x1000>;
640 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
641 #address-cells = <1>;
644 clocks = <&cru PCLK_I2C2>;
645 pinctrl-names = "default";
646 pinctrl-0 = <&i2c2_xfer>;
651 compatible = "rockchip,rk3288-pwm";
652 reg = <0xff680000 0x10>;
654 pinctrl-names = "default";
655 pinctrl-0 = <&pwm0_pin>;
656 clocks = <&cru PCLK_PWM>;
662 compatible = "rockchip,rk3288-pwm";
663 reg = <0xff680010 0x10>;
665 pinctrl-names = "default";
666 pinctrl-0 = <&pwm1_pin>;
667 clocks = <&cru PCLK_PWM>;
673 compatible = "rockchip,rk3288-pwm";
674 reg = <0xff680020 0x10>;
676 pinctrl-names = "default";
677 pinctrl-0 = <&pwm2_pin>;
678 clocks = <&cru PCLK_PWM>;
684 compatible = "rockchip,rk3288-pwm";
685 reg = <0xff680030 0x10>;
687 pinctrl-names = "default";
688 pinctrl-0 = <&pwm3_pin>;
689 clocks = <&cru PCLK_PWM>;
694 bus_intmem@ff700000 {
695 compatible = "mmio-sram";
696 reg = <0xff700000 0x18000>;
697 #address-cells = <1>;
699 ranges = <0 0xff700000 0x18000>;
701 compatible = "rockchip,rk3066-smp-sram";
707 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
708 reg = <0xff720000 0x1000>;
711 pmu: power-management@ff730000 {
712 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
713 reg = <0xff730000 0x100>;
715 power: power-controller {
716 compatible = "rockchip,rk3288-power-controller";
717 #power-domain-cells = <1>;
718 #address-cells = <1>;
721 assigned-clocks = <&cru SCLK_EDP_24M>;
722 assigned-clock-parents = <&xin24m>;
725 * Note: Although SCLK_* are the working clocks
726 * of device without including on the NOC, needed for
729 * The clocks on the which NOC:
730 * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
731 * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
732 * ACLK_RGA is on ACLK_RGA_NIU.
733 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
735 * Which clock are device clocks:
737 * *_IEP IEP:Image Enhancement Processor
738 * *_ISP ISP:Image Signal Processing
739 * *_VIP VIP:Video Input Processor
740 * *_VOP* VOP:Visual Output Processor
747 pd_vio@RK3288_PD_VIO {
748 reg = <RK3288_PD_VIO>;
749 clocks = <&cru ACLK_IEP>,
763 <&cru PCLK_EDP_CTRL>,
764 <&cru PCLK_HDMI_CTRL>,
765 <&cru PCLK_LVDS_PHY>,
766 <&cru PCLK_MIPI_CSI>,
767 <&cru PCLK_MIPI_DSI0>,
768 <&cru PCLK_MIPI_DSI1>,
774 pm_qos = <&qos_vio0_iep>,
786 * Note: The following 3 are HEVC(H.265) clocks,
787 * and on the ACLK_HEVC_NIU (NOC).
789 pd_hevc@RK3288_PD_HEVC {
790 reg = <RK3288_PD_HEVC>;
791 clocks = <&cru ACLK_HEVC>,
792 <&cru SCLK_HEVC_CABAC>,
793 <&cru SCLK_HEVC_CORE>;
794 pm_qos = <&qos_hevc_r>,
799 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
800 * (video endecoder & decoder) clocks that on the
801 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
803 pd_video@RK3288_PD_VIDEO {
804 reg = <RK3288_PD_VIDEO>;
805 clocks = <&cru ACLK_VCODEC>,
807 pm_qos = <&qos_video>;
811 * Note: ACLK_GPU is the GPU clock,
812 * and on the ACLK_GPU_NIU (NOC).
814 pd_gpu@RK3288_PD_GPU {
815 reg = <RK3288_PD_GPU>;
816 clocks = <&cru ACLK_GPU>;
817 pm_qos = <&qos_gpu_r>,
823 compatible = "syscon-reboot-mode";
825 mode-normal = <BOOT_NORMAL>;
826 mode-recovery = <BOOT_RECOVERY>;
827 mode-bootloader = <BOOT_FASTBOOT>;
828 mode-loader = <BOOT_BL_DOWNLOAD>;
832 sgrf: syscon@ff740000 {
833 compatible = "rockchip,rk3288-sgrf", "syscon";
834 reg = <0xff740000 0x1000>;
837 cru: clock-controller@ff760000 {
838 compatible = "rockchip,rk3288-cru";
839 reg = <0xff760000 0x1000>;
840 rockchip,grf = <&grf>;
843 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
844 <&cru PLL_NPLL>, <&cru ACLK_CPU>,
845 <&cru HCLK_CPU>, <&cru PCLK_CPU>,
846 <&cru ACLK_PERI>, <&cru HCLK_PERI>,
848 assigned-clock-rates = <594000000>, <400000000>,
849 <500000000>, <300000000>,
850 <150000000>, <75000000>,
851 <300000000>, <150000000>,
855 grf: syscon@ff770000 {
856 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
857 reg = <0xff770000 0x1000>;
860 compatible = "rockchip,rk3288-dp-phy";
861 clocks = <&cru SCLK_EDP_24M>;
867 io_domains: io-domains {
868 compatible = "rockchip,rk3288-io-voltage-domain";
873 compatible = "rockchip,rk3288-usb-phy";
874 #address-cells = <1>;
878 usbphy0: usb-phy@320 {
881 clocks = <&cru SCLK_OTGPHY0>;
882 clock-names = "phyclk";
886 usbphy1: usb-phy@334 {
889 clocks = <&cru SCLK_OTGPHY1>;
890 clock-names = "phyclk";
894 usbphy2: usb-phy@348 {
897 clocks = <&cru SCLK_OTGPHY2>;
898 clock-names = "phyclk";
904 wdt: watchdog@ff800000 {
905 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
906 reg = <0xff800000 0x100>;
907 clocks = <&cru PCLK_WDT>;
908 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
912 spdif: sound@ff88b0000 {
913 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
914 reg = <0xff8b0000 0x10000>;
915 #sound-dai-cells = <0>;
916 clock-names = "hclk", "mclk";
917 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
918 dmas = <&dmac_bus_s 3>;
920 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
921 pinctrl-names = "default";
922 pinctrl-0 = <&spdif_tx>;
923 rockchip,grf = <&grf>;
928 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
929 reg = <0xff890000 0x10000>;
930 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
931 #address-cells = <1>;
933 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
934 dma-names = "tx", "rx";
935 clock-names = "i2s_hclk", "i2s_clk";
936 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
937 pinctrl-names = "default";
938 pinctrl-0 = <&i2s0_bus>;
939 rockchip,playback-channels = <8>;
940 rockchip,capture-channels = <2>;
944 crypto: cypto-controller@ff8a0000 {
945 compatible = "rockchip,rk3288-crypto";
946 reg = <0xff8a0000 0x4000>;
947 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
948 clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>,
949 <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>;
950 clock-names = "aclk", "hclk", "sclk", "apb_pclk";
951 resets = <&cru SRST_CRYPTO>;
952 reset-names = "crypto-rst";
957 compatible = "rockchip,rk3288-vop";
958 reg = <0xff930000 0x19c>;
959 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
960 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
961 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
962 power-domains = <&power RK3288_PD_VIO>;
963 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
964 reset-names = "axi", "ahb", "dclk";
965 iommus = <&vopb_mmu>;
969 #address-cells = <1>;
972 vopb_out_hdmi: endpoint@0 {
974 remote-endpoint = <&hdmi_in_vopb>;
977 vopb_out_edp: endpoint@1 {
979 remote-endpoint = <&edp_in_vopb>;
982 vopb_out_mipi: endpoint@2 {
984 remote-endpoint = <&mipi_in_vopb>;
989 vopb_mmu: iommu@ff930300 {
990 compatible = "rockchip,iommu";
991 reg = <0xff930300 0x100>;
992 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
993 interrupt-names = "vopb_mmu";
994 power-domains = <&power RK3288_PD_VIO>;
1000 compatible = "rockchip,rk3288-vop";
1001 reg = <0xff940000 0x19c>;
1002 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1003 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1004 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1005 power-domains = <&power RK3288_PD_VIO>;
1006 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
1007 reset-names = "axi", "ahb", "dclk";
1008 iommus = <&vopl_mmu>;
1009 status = "disabled";
1012 #address-cells = <1>;
1015 vopl_out_hdmi: endpoint@0 {
1017 remote-endpoint = <&hdmi_in_vopl>;
1020 vopl_out_edp: endpoint@1 {
1022 remote-endpoint = <&edp_in_vopl>;
1025 vopl_out_mipi: endpoint@2 {
1027 remote-endpoint = <&mipi_in_vopl>;
1032 vopl_mmu: iommu@ff940300 {
1033 compatible = "rockchip,iommu";
1034 reg = <0xff940300 0x100>;
1035 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1036 interrupt-names = "vopl_mmu";
1037 power-domains = <&power RK3288_PD_VIO>;
1039 status = "disabled";
1042 mipi_dsi: mipi@ff960000 {
1043 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
1044 reg = <0xff960000 0x4000>;
1045 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1046 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
1047 clock-names = "ref", "pclk";
1048 power-domains = <&power RK3288_PD_VIO>;
1049 rockchip,grf = <&grf>;
1050 #address-cells = <1>;
1052 status = "disabled";
1056 #address-cells = <1>;
1058 mipi_in_vopb: endpoint@0 {
1060 remote-endpoint = <&vopb_out_mipi>;
1062 mipi_in_vopl: endpoint@1 {
1064 remote-endpoint = <&vopl_out_mipi>;
1071 compatible = "rockchip,rk3288-dp";
1072 reg = <0xff970000 0x4000>;
1073 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1074 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1075 clock-names = "dp", "pclk";
1078 resets = <&cru SRST_EDP>;
1080 rockchip,grf = <&grf>;
1081 status = "disabled";
1084 #address-cells = <1>;
1088 #address-cells = <1>;
1090 edp_in_vopb: endpoint@0 {
1092 remote-endpoint = <&vopb_out_edp>;
1094 edp_in_vopl: endpoint@1 {
1096 remote-endpoint = <&vopl_out_edp>;
1102 hdmi: hdmi@ff980000 {
1103 compatible = "rockchip,rk3288-dw-hdmi";
1104 reg = <0xff980000 0x20000>;
1106 rockchip,grf = <&grf>;
1107 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1108 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
1109 clock-names = "iahb", "isfr";
1110 power-domains = <&power RK3288_PD_VIO>;
1111 status = "disabled";
1115 #address-cells = <1>;
1117 hdmi_in_vopb: endpoint@0 {
1119 remote-endpoint = <&vopb_out_hdmi>;
1121 hdmi_in_vopl: endpoint@1 {
1123 remote-endpoint = <&vopl_out_hdmi>;
1130 compatible = "rockchip,rk3288-mali", "arm,mali-t760";
1131 reg = <0xffa30000 0x10000>;
1132 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1133 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1134 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1135 interrupt-names = "job", "mmu", "gpu";
1136 clocks = <&cru ACLK_GPU>;
1137 operating-points-v2 = <&gpu_opp_table>;
1138 power-domains = <&power RK3288_PD_GPU>;
1139 status = "disabled";
1142 gpu_opp_table: gpu-opp-table {
1143 compatible = "operating-points-v2";
1146 opp-hz = /bits/ 64 <100000000>;
1147 opp-microvolt = <950000>;
1150 opp-hz = /bits/ 64 <200000000>;
1151 opp-microvolt = <950000>;
1154 opp-hz = /bits/ 64 <300000000>;
1155 opp-microvolt = <1000000>;
1158 opp-hz = /bits/ 64 <400000000>;
1159 opp-microvolt = <1100000>;
1162 opp-hz = /bits/ 64 <500000000>;
1163 opp-microvolt = <1200000>;
1166 opp-hz = /bits/ 64 <600000000>;
1167 opp-microvolt = <1250000>;
1171 qos_gpu_r: qos@ffaa0000 {
1172 compatible = "syscon";
1173 reg = <0xffaa0000 0x20>;
1176 qos_gpu_w: qos@ffaa0080 {
1177 compatible = "syscon";
1178 reg = <0xffaa0080 0x20>;
1181 qos_vio1_vop: qos@ffad0000 {
1182 compatible = "syscon";
1183 reg = <0xffad0000 0x20>;
1186 qos_vio1_isp_w0: qos@ffad0100 {
1187 compatible = "syscon";
1188 reg = <0xffad0100 0x20>;
1191 qos_vio1_isp_w1: qos@ffad0180 {
1192 compatible = "syscon";
1193 reg = <0xffad0180 0x20>;
1196 qos_vio0_vop: qos@ffad0400 {
1197 compatible = "syscon";
1198 reg = <0xffad0400 0x20>;
1201 qos_vio0_vip: qos@ffad0480 {
1202 compatible = "syscon";
1203 reg = <0xffad0480 0x20>;
1206 qos_vio0_iep: qos@ffad0500 {
1207 compatible = "syscon";
1208 reg = <0xffad0500 0x20>;
1211 qos_vio2_rga_r: qos@ffad0800 {
1212 compatible = "syscon";
1213 reg = <0xffad0800 0x20>;
1216 qos_vio2_rga_w: qos@ffad0880 {
1217 compatible = "syscon";
1218 reg = <0xffad0880 0x20>;
1221 qos_vio1_isp_r: qos@ffad0900 {
1222 compatible = "syscon";
1223 reg = <0xffad0900 0x20>;
1226 qos_video: qos@ffae0000 {
1227 compatible = "syscon";
1228 reg = <0xffae0000 0x20>;
1231 qos_hevc_r: qos@ffaf0000 {
1232 compatible = "syscon";
1233 reg = <0xffaf0000 0x20>;
1236 qos_hevc_w: qos@ffaf0080 {
1237 compatible = "syscon";
1238 reg = <0xffaf0080 0x20>;
1241 gic: interrupt-controller@ffc01000 {
1242 compatible = "arm,gic-400";
1243 interrupt-controller;
1244 #interrupt-cells = <3>;
1245 #address-cells = <0>;
1247 reg = <0xffc01000 0x1000>,
1248 <0xffc02000 0x2000>,
1249 <0xffc04000 0x2000>,
1250 <0xffc06000 0x2000>;
1251 interrupts = <GIC_PPI 9 0xf04>;
1254 efuse: efuse@ffb40000 {
1255 compatible = "rockchip,rk3288-efuse";
1256 reg = <0xffb40000 0x20>;
1257 #address-cells = <1>;
1259 clocks = <&cru PCLK_EFUSE256>;
1260 clock-names = "pclk_efuse";
1262 cpu_leakage: cpu_leakage@17 {
1268 compatible = "rockchip,rk3288-pinctrl";
1269 rockchip,grf = <&grf>;
1270 rockchip,pmu = <&pmu>;
1271 #address-cells = <1>;
1275 gpio0: gpio0@ff750000 {
1276 compatible = "rockchip,gpio-bank";
1277 reg = <0xff750000 0x100>;
1278 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1279 clocks = <&cru PCLK_GPIO0>;
1284 interrupt-controller;
1285 #interrupt-cells = <2>;
1288 gpio1: gpio1@ff780000 {
1289 compatible = "rockchip,gpio-bank";
1290 reg = <0xff780000 0x100>;
1291 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1292 clocks = <&cru PCLK_GPIO1>;
1297 interrupt-controller;
1298 #interrupt-cells = <2>;
1301 gpio2: gpio2@ff790000 {
1302 compatible = "rockchip,gpio-bank";
1303 reg = <0xff790000 0x100>;
1304 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1305 clocks = <&cru PCLK_GPIO2>;
1310 interrupt-controller;
1311 #interrupt-cells = <2>;
1314 gpio3: gpio3@ff7a0000 {
1315 compatible = "rockchip,gpio-bank";
1316 reg = <0xff7a0000 0x100>;
1317 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1318 clocks = <&cru PCLK_GPIO3>;
1323 interrupt-controller;
1324 #interrupt-cells = <2>;
1327 gpio4: gpio4@ff7b0000 {
1328 compatible = "rockchip,gpio-bank";
1329 reg = <0xff7b0000 0x100>;
1330 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1331 clocks = <&cru PCLK_GPIO4>;
1336 interrupt-controller;
1337 #interrupt-cells = <2>;
1340 gpio5: gpio5@ff7c0000 {
1341 compatible = "rockchip,gpio-bank";
1342 reg = <0xff7c0000 0x100>;
1343 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1344 clocks = <&cru PCLK_GPIO5>;
1349 interrupt-controller;
1350 #interrupt-cells = <2>;
1353 gpio6: gpio6@ff7d0000 {
1354 compatible = "rockchip,gpio-bank";
1355 reg = <0xff7d0000 0x100>;
1356 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1357 clocks = <&cru PCLK_GPIO6>;
1362 interrupt-controller;
1363 #interrupt-cells = <2>;
1366 gpio7: gpio7@ff7e0000 {
1367 compatible = "rockchip,gpio-bank";
1368 reg = <0xff7e0000 0x100>;
1369 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1370 clocks = <&cru PCLK_GPIO7>;
1375 interrupt-controller;
1376 #interrupt-cells = <2>;
1379 gpio8: gpio8@ff7f0000 {
1380 compatible = "rockchip,gpio-bank";
1381 reg = <0xff7f0000 0x100>;
1382 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1383 clocks = <&cru PCLK_GPIO8>;
1388 interrupt-controller;
1389 #interrupt-cells = <2>;
1393 hdmi_ddc: hdmi-ddc {
1394 rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>,
1395 <7 20 RK_FUNC_2 &pcfg_pull_none>;
1399 pcfg_pull_up: pcfg-pull-up {
1403 pcfg_pull_down: pcfg-pull-down {
1407 pcfg_pull_none: pcfg-pull-none {
1411 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1413 drive-strength = <12>;
1417 global_pwroff: global-pwroff {
1418 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1421 ddrio_pwroff: ddrio-pwroff {
1422 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1425 ddr0_retention: ddr0-retention {
1426 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1429 ddr1_retention: ddr1-retention {
1430 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1436 rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>;
1441 i2c0_xfer: i2c0-xfer {
1442 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1443 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1448 i2c1_xfer: i2c1-xfer {
1449 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1450 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1455 i2c2_xfer: i2c2-xfer {
1456 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1457 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1462 i2c3_xfer: i2c3-xfer {
1463 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1464 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1469 i2c4_xfer: i2c4-xfer {
1470 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1471 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1476 i2c5_xfer: i2c5-xfer {
1477 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1478 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1483 i2s0_bus: i2s0-bus {
1484 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1485 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1486 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1487 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1488 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1489 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1494 sdmmc_clk: sdmmc-clk {
1495 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1498 sdmmc_cmd: sdmmc-cmd {
1499 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1502 sdmmc_cd: sdmmc-cd {
1503 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1506 sdmmc_bus1: sdmmc-bus1 {
1507 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1510 sdmmc_bus4: sdmmc-bus4 {
1511 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1512 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1513 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1514 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1519 sdio0_bus1: sdio0-bus1 {
1520 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1523 sdio0_bus4: sdio0-bus4 {
1524 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1525 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1526 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1527 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1530 sdio0_cmd: sdio0-cmd {
1531 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1534 sdio0_clk: sdio0-clk {
1535 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1538 sdio0_cd: sdio0-cd {
1539 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1542 sdio0_wp: sdio0-wp {
1543 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1546 sdio0_pwr: sdio0-pwr {
1547 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1550 sdio0_bkpwr: sdio0-bkpwr {
1551 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1554 sdio0_int: sdio0-int {
1555 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1560 sdio1_bus1: sdio1-bus1 {
1561 rockchip,pins = <3 24 4 &pcfg_pull_up>;
1564 sdio1_bus4: sdio1-bus4 {
1565 rockchip,pins = <3 24 4 &pcfg_pull_up>,
1566 <3 25 4 &pcfg_pull_up>,
1567 <3 26 4 &pcfg_pull_up>,
1568 <3 27 4 &pcfg_pull_up>;
1571 sdio1_cd: sdio1-cd {
1572 rockchip,pins = <3 28 4 &pcfg_pull_up>;
1575 sdio1_wp: sdio1-wp {
1576 rockchip,pins = <3 29 4 &pcfg_pull_up>;
1579 sdio1_bkpwr: sdio1-bkpwr {
1580 rockchip,pins = <3 30 4 &pcfg_pull_up>;
1583 sdio1_int: sdio1-int {
1584 rockchip,pins = <3 31 4 &pcfg_pull_up>;
1587 sdio1_cmd: sdio1-cmd {
1588 rockchip,pins = <4 6 4 &pcfg_pull_up>;
1591 sdio1_clk: sdio1-clk {
1592 rockchip,pins = <4 7 4 &pcfg_pull_none>;
1595 sdio1_pwr: sdio1-pwr {
1596 rockchip,pins = <4 9 4 &pcfg_pull_up>;
1601 emmc_clk: emmc-clk {
1602 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1605 emmc_cmd: emmc-cmd {
1606 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1609 emmc_pwr: emmc-pwr {
1610 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1613 emmc_bus1: emmc-bus1 {
1614 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1617 emmc_bus4: emmc-bus4 {
1618 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1619 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1620 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1621 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1624 emmc_bus8: emmc-bus8 {
1625 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1626 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1627 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1628 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1629 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1630 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1631 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1632 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1637 spi0_clk: spi0-clk {
1638 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1640 spi0_cs0: spi0-cs0 {
1641 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1644 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1647 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1649 spi0_cs1: spi0-cs1 {
1650 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1654 spi1_clk: spi1-clk {
1655 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1657 spi1_cs0: spi1-cs0 {
1658 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1661 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1664 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1669 spi2_cs1: spi2-cs1 {
1670 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1672 spi2_clk: spi2-clk {
1673 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1675 spi2_cs0: spi2-cs0 {
1676 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1679 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1682 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1687 uart0_xfer: uart0-xfer {
1688 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1689 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1692 uart0_cts: uart0-cts {
1693 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>;
1696 uart0_rts: uart0-rts {
1697 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1702 uart1_xfer: uart1-xfer {
1703 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1704 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1707 uart1_cts: uart1-cts {
1708 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>;
1711 uart1_rts: uart1-rts {
1712 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1717 uart2_xfer: uart2-xfer {
1718 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1719 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1721 /* no rts / cts for uart2 */
1725 uart3_xfer: uart3-xfer {
1726 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1727 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1730 uart3_cts: uart3-cts {
1731 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>;
1734 uart3_rts: uart3-rts {
1735 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1740 uart4_xfer: uart4-xfer {
1741 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1742 <5 13 3 &pcfg_pull_none>;
1745 uart4_cts: uart4-cts {
1746 rockchip,pins = <5 14 3 &pcfg_pull_up>;
1749 uart4_rts: uart4-rts {
1750 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1755 otp_gpio: otp-gpio {
1756 rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
1760 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1765 pwm0_pin: pwm0-pin {
1766 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1771 pwm1_pin: pwm1-pin {
1772 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1777 pwm2_pin: pwm2-pin {
1778 rockchip,pins = <7 22 3 &pcfg_pull_none>;
1783 pwm3_pin: pwm3-pin {
1784 rockchip,pins = <7 23 3 &pcfg_pull_none>;
1789 rgmii_pins: rgmii-pins {
1790 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1791 <3 31 3 &pcfg_pull_none>,
1792 <3 26 3 &pcfg_pull_none>,
1793 <3 27 3 &pcfg_pull_none>,
1794 <3 28 3 &pcfg_pull_none_12ma>,
1795 <3 29 3 &pcfg_pull_none_12ma>,
1796 <3 24 3 &pcfg_pull_none_12ma>,
1797 <3 25 3 &pcfg_pull_none_12ma>,
1798 <4 0 3 &pcfg_pull_none>,
1799 <4 5 3 &pcfg_pull_none>,
1800 <4 6 3 &pcfg_pull_none>,
1801 <4 9 3 &pcfg_pull_none_12ma>,
1802 <4 4 3 &pcfg_pull_none_12ma>,
1803 <4 1 3 &pcfg_pull_none>,
1804 <4 3 3 &pcfg_pull_none>;
1807 rmii_pins: rmii-pins {
1808 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1809 <3 31 3 &pcfg_pull_none>,
1810 <3 28 3 &pcfg_pull_none>,
1811 <3 29 3 &pcfg_pull_none>,
1812 <4 0 3 &pcfg_pull_none>,
1813 <4 5 3 &pcfg_pull_none>,
1814 <4 4 3 &pcfg_pull_none>,
1815 <4 1 3 &pcfg_pull_none>,
1816 <4 2 3 &pcfg_pull_none>,
1817 <4 3 3 &pcfg_pull_none>;
1822 spdif_tx: spdif-tx {
1823 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;