arch/arm/boot/dts/rk3xxx.dtsi

   1 /*
   2  * Copyright (c) 2013 MundoReader S.L.
   3  * Author: Heiko Stuebner <heiko@sntech.de>
   4  *
   5  * This file is dual-licensed: you can use it either under the terms
   6  * of the GPL or the X11 license, at your option. Note that this dual
   7  * licensing only applies to this file, and not this project as a
   8  * whole.
   9  *
  10  *  a) This file is free software; you can redistribute it and/or
  11  *     modify it under the terms of the GNU General Public License as
  12  *     published by the Free Software Foundation; either version 2 of the
  13  *     License, or (at your option) any later version.
  14  *
  15  *     This file is distributed in the hope that it will be useful,
  16  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *     GNU General Public License for more details.
  19  *
  20  * Or, alternatively,
  21  *
  22  *  b) Permission is hereby granted, free of charge, to any person
  23  *     obtaining a copy of this software and associated documentation
  24  *     files (the "Software"), to deal in the Software without
  25  *     restriction, including without limitation the rights to use,
  26  *     copy, modify, merge, publish, distribute, sublicense, and/or
  27  *     sell copies of the Software, and to permit persons to whom the
  28  *     Software is furnished to do so, subject to the following
  29  *     conditions:
  30  *
  31  *     The above copyright notice and this permission notice shall be
  32  *     included in all copies or substantial portions of the Software.
  33  *
  34  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  35  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  36  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  37  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  38  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  39  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  40  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  41  *     OTHER DEALINGS IN THE SOFTWARE.
  42  */
  43
  44 #include <dt-bindings/interrupt-controller/irq.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include "skeleton.dtsi"
  47
  48 / {
  49         interrupt-parent = <&gic>;
  50
  51         aliases {
  52                 ethernet0 = &emac;
  53                 i2c0 = &i2c0;
  54                 i2c1 = &i2c1;
  55                 i2c2 = &i2c2;
  56                 i2c3 = &i2c3;
  57                 i2c4 = &i2c4;
  58                 mshc0 = &emmc;
  59                 mshc1 = &mmc0;
  60                 mshc2 = &mmc1;
  61                 serial0 = &uart0;
  62                 serial1 = &uart1;
  63                 serial2 = &uart2;
  64                 serial3 = &uart3;
  65                 spi0 = &spi0;
  66                 spi1 = &spi1;
  67         };
  68
  69         amba {
  70                 compatible = "arm,amba-bus";
  71                 #address-cells = <1>;
  72                 #size-cells = <1>;
  73                 ranges;
  74
  75                 dmac1_s: dma-controller@20018000 {
  76                         compatible = "arm,pl330", "arm,primecell";
  77                         reg = <0x20018000 0x4000>;
  78                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
  79                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
  80                         #dma-cells = <1>;
  81                         clocks = <&cru ACLK_DMA1>;
  82                         clock-names = "apb_pclk";
  83                 };
  84
  85                 dmac1_ns: dma-controller@2001c000 {
  86                         compatible = "arm,pl330", "arm,primecell";
  87                         reg = <0x2001c000 0x4000>;
  88                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
  89                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
  90                         #dma-cells = <1>;
  91                         clocks = <&cru ACLK_DMA1>;
  92                         clock-names = "apb_pclk";
  93                         status = "disabled";
  94                 };
  95
  96                 dmac2: dma-controller@20078000 {
  97                         compatible = "arm,pl330", "arm,primecell";
  98                         reg = <0x20078000 0x4000>;
  99                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 100                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 101                         #dma-cells = <1>;
 102                         clocks = <&cru ACLK_DMA2>;
 103                         clock-names = "apb_pclk";
 104                 };
 105         };
 106
 107         xin24m: oscillator {
 108                 compatible = "fixed-clock";
 109                 clock-frequency = <24000000>;
 110                 #clock-cells = <0>;
 111                 clock-output-names = "xin24m";
 112         };
 113
 114         L2: l2-cache-controller@10138000 {
 115                 compatible = "arm,pl310-cache";
 116                 reg = <0x10138000 0x1000>;
 117                 cache-unified;
 118                 cache-level = <2>;
 119         };
 120
 121         scu@1013c000 {
 122                 compatible = "arm,cortex-a9-scu";
 123                 reg = <0x1013c000 0x100>;
 124         };
 125
 126         global_timer: global-timer@1013c200 {
 127                 compatible = "arm,cortex-a9-global-timer";
 128                 reg = <0x1013c200 0x20>;
 129                 interrupts = <GIC_PPI 11 0x304>;
 130                 clocks = <&cru CORE_PERI>;
 131         };
 132
 133         local_timer: local-timer@1013c600 {
 134                 compatible = "arm,cortex-a9-twd-timer";
 135                 reg = <0x1013c600 0x20>;
 136                 interrupts = <GIC_PPI 13 0x304>;
 137                 clocks = <&cru CORE_PERI>;
 138         };
 139
 140         gic: interrupt-controller@1013d000 {
 141                 compatible = "arm,cortex-a9-gic";
 142                 interrupt-controller;
 143                 #interrupt-cells = <3>;
 144                 reg = <0x1013d000 0x1000>,
 145                       <0x1013c100 0x0100>;
 146         };
 147
 148         uart0: serial@10124000 {
 149                 compatible = "snps,dw-apb-uart";
 150                 reg = <0x10124000 0x400>;
 151                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 152                 reg-shift = <2>;
 153                 reg-io-width = <1>;
 154                 clock-names = "baudclk", "apb_pclk";
 155                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 156                 status = "disabled";
 157         };
 158
 159         uart1: serial@10126000 {
 160                 compatible = "snps,dw-apb-uart";
 161                 reg = <0x10126000 0x400>;
 162                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 163                 reg-shift = <2>;
 164                 reg-io-width = <1>;
 165                 clock-names = "baudclk", "apb_pclk";
 166                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 167                 status = "disabled";
 168         };
 169
 170         usb_otg: usb@10180000 {
 171                 compatible = "rockchip,rk3066-usb", "snps,dwc2";
 172                 reg = <0x10180000 0x40000>;
 173                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 174                 clocks = <&cru HCLK_OTG0>;
 175                 clock-names = "otg";
 176                 dr_mode = "otg";
 177                 g-np-tx-fifo-size = <16>;
 178                 g-rx-fifo-size = <275>;
 179                 g-tx-fifo-size = <256 128 128 64 64 32>;
 180                 g-use-dma;
 181                 phys = <&usbphy0>;
 182                 phy-names = "usb2-phy";
 183                 status = "disabled";
 184         };
 185
 186         usb_host: usb@101c0000 {
 187                 compatible = "snps,dwc2";
 188                 reg = <0x101c0000 0x40000>;
 189                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 190                 clocks = <&cru HCLK_OTG1>;
 191                 clock-names = "otg";
 192                 dr_mode = "host";
 193                 phys = <&usbphy1>;
 194                 phy-names = "usb2-phy";
 195                 status = "disabled";
 196         };
 197
 198         emac: ethernet@10204000 {
 199                 compatible = "snps,arc-emac";
 200                 reg = <0x10204000 0x3c>;
 201                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 202                 #address-cells = <1>;
 203                 #size-cells = <0>;
 204
 205                 rockchip,grf = <&grf>;
 206
 207                 clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>;
 208                 clock-names = "hclk", "macref";
 209                 max-speed = <100>;
 210                 phy-mode = "rmii";
 211
 212                 status = "disabled";
 213         };
 214
 215         mmc0: dwmmc@10214000 {
 216                 compatible = "rockchip,rk2928-dw-mshc";
 217                 reg = <0x10214000 0x1000>;
 218                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 219                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 220                 clock-names = "biu", "ciu";
 221                 fifo-depth = <256>;
 222                 status = "disabled";
 223         };
 224
 225         mmc1: dwmmc@10218000 {
 226                 compatible = "rockchip,rk2928-dw-mshc";
 227                 reg = <0x10218000 0x1000>;
 228                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 229                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>;
 230                 clock-names = "biu", "ciu";
 231                 fifo-depth = <256>;
 232                 status = "disabled";
 233         };
 234
 235         emmc: dwmmc@1021c000 {
 236                 compatible = "rockchip,rk2928-dw-mshc";
 237                 reg = <0x1021c000 0x1000>;
 238                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 239                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
 240                 clock-names = "biu", "ciu";
 241                 fifo-depth = <256>;
 242                 status = "disabled";
 243         };
 244
 245         pmu: pmu@20004000 {
 246                 compatible = "rockchip,rk3066-pmu", "syscon";
 247                 reg = <0x20004000 0x100>;
 248         };
 249
 250         grf: grf@20008000 {
 251                 compatible = "syscon";
 252                 reg = <0x20008000 0x200>;
 253         };
 254
 255         i2c0: i2c@2002d000 {
 256                 compatible = "rockchip,rk3066-i2c";
 257                 reg = <0x2002d000 0x1000>;
 258                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 259                 #address-cells = <1>;
 260                 #size-cells = <0>;
 261
 262                 rockchip,grf = <&grf>;
 263
 264                 clock-names = "i2c";
 265                 clocks = <&cru PCLK_I2C0>;
 266
 267                 status = "disabled";
 268         };
 269
 270         i2c1: i2c@2002f000 {
 271                 compatible = "rockchip,rk3066-i2c";
 272                 reg = <0x2002f000 0x1000>;
 273                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 274                 #address-cells = <1>;
 275                 #size-cells = <0>;
 276
 277                 rockchip,grf = <&grf>;
 278
 279                 clocks = <&cru PCLK_I2C1>;
 280                 clock-names = "i2c";
 281
 282                 status = "disabled";
 283         };
 284
 285         pwm0: pwm@20030000 {
 286                 compatible = "rockchip,rk2928-pwm";
 287                 reg = <0x20030000 0x10>;
 288                 #pwm-cells = <2>;
 289                 clocks = <&cru PCLK_PWM01>;
 290                 status = "disabled";
 291         };
 292
 293         pwm1: pwm@20030010 {
 294                 compatible = "rockchip,rk2928-pwm";
 295                 reg = <0x20030010 0x10>;
 296                 #pwm-cells = <2>;
 297                 clocks = <&cru PCLK_PWM01>;
 298                 status = "disabled";
 299         };
 300
 301         wdt: watchdog@2004c000 {
 302                 compatible = "snps,dw-wdt";
 303                 reg = <0x2004c000 0x100>;
 304                 clocks = <&cru PCLK_WDT>;
 305                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 306                 status = "disabled";
 307         };
 308
 309         pwm2: pwm@20050020 {
 310                 compatible = "rockchip,rk2928-pwm";
 311                 reg = <0x20050020 0x10>;
 312                 #pwm-cells = <2>;
 313                 clocks = <&cru PCLK_PWM23>;
 314                 status = "disabled";
 315         };
 316
 317         pwm3: pwm@20050030 {
 318                 compatible = "rockchip,rk2928-pwm";
 319                 reg = <0x20050030 0x10>;
 320                 #pwm-cells = <2>;
 321                 clocks = <&cru PCLK_PWM23>;
 322                 status = "disabled";
 323         };
 324
 325         i2c2: i2c@20056000 {
 326                 compatible = "rockchip,rk3066-i2c";
 327                 reg = <0x20056000 0x1000>;
 328                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 329                 #address-cells = <1>;
 330                 #size-cells = <0>;
 331
 332                 rockchip,grf = <&grf>;
 333
 334                 clocks = <&cru PCLK_I2C2>;
 335                 clock-names = "i2c";
 336
 337                 status = "disabled";
 338         };
 339
 340         i2c3: i2c@2005a000 {
 341                 compatible = "rockchip,rk3066-i2c";
 342                 reg = <0x2005a000 0x1000>;
 343                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 344                 #address-cells = <1>;
 345                 #size-cells = <0>;
 346
 347                 rockchip,grf = <&grf>;
 348
 349                 clocks = <&cru PCLK_I2C3>;
 350                 clock-names = "i2c";
 351
 352                 status = "disabled";
 353         };
 354
 355         i2c4: i2c@2005e000 {
 356                 compatible = "rockchip,rk3066-i2c";
 357                 reg = <0x2005e000 0x1000>;
 358                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 359                 #address-cells = <1>;
 360                 #size-cells = <0>;
 361
 362                 rockchip,grf = <&grf>;
 363
 364                 clocks = <&cru PCLK_I2C4>;
 365                 clock-names = "i2c";
 366
 367                 status = "disabled";
 368         };
 369
 370         uart2: serial@20064000 {
 371                 compatible = "snps,dw-apb-uart";
 372                 reg = <0x20064000 0x400>;
 373                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 374                 reg-shift = <2>;
 375                 reg-io-width = <1>;
 376                 clock-names = "baudclk", "apb_pclk";
 377                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 378                 status = "disabled";
 379         };
 380
 381         uart3: serial@20068000 {
 382                 compatible = "snps,dw-apb-uart";
 383                 reg = <0x20068000 0x400>;
 384                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 385                 reg-shift = <2>;
 386                 reg-io-width = <1>;
 387                 clock-names = "baudclk", "apb_pclk";
 388                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 389                 status = "disabled";
 390         };
 391
 392         saradc: saradc@2006c000 {
 393                 compatible = "rockchip,saradc";
 394                 reg = <0x2006c000 0x100>;
 395                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 396                 #io-channel-cells = <1>;
 397                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 398                 clock-names = "saradc", "apb_pclk";
 399                 status = "disabled";
 400         };
 401
 402         spi0: spi@20070000 {
 403                 compatible = "rockchip,rk3066-spi";
 404                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 405                 clock-names = "spiclk", "apb_pclk";
 406                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 407                 reg = <0x20070000 0x1000>;
 408                 #address-cells = <1>;
 409                 #size-cells = <0>;
 410                 dmas = <&dmac2 10>, <&dmac2 11>;
 411                 dma-names = "tx", "rx";
 412                 status = "disabled";
 413         };
 414
 415         spi1: spi@20074000 {
 416                 compatible = "rockchip,rk3066-spi";
 417                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 418                 clock-names = "spiclk", "apb_pclk";
 419                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 420                 reg = <0x20074000 0x1000>;
 421                 #address-cells = <1>;
 422                 #size-cells = <0>;
 423                 dmas = <&dmac2 12>, <&dmac2 13>;
 424                 dma-names = "tx", "rx";
 425                 status = "disabled";
 426         };
 427 };