arch/arm/boot/dts/rv1108.dtsi

   1 /*
   2  * This file is dual-licensed: you can use it either under the terms
   3  * of the GPL or the X11 license, at your option. Note that this dual
   4  * licensing only applies to this file, and not this project as a
   5  * whole.
   6  *
   7  *  a) This file is free software; you can redistribute it and/or
   8  *     modify it under the terms of the GNU General Public License as
   9  *     published by the Free Software Foundation; either version 2 of the
  10  *     License, or (at your option) any later version.
  11  *
  12  *     This file is distributed in the hope that it will be useful,
  13  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *     GNU General Public License for more details.
  16  *
  17  * Or, alternatively,
  18  *
  19  *  b) Permission is hereby granted, free of charge, to any person
  20  *     obtaining a copy of this software and associated documentation
  21  *     files (the "Software"), to deal in the Software without
  22  *     restriction, including without limitation the rights to use,
  23  *     copy, modify, merge, publish, distribute, sublicense, and/or
  24  *     sell copies of the Software, and to permit persons to whom the
  25  *     Software is furnished to do so, subject to the following
  26  *     conditions:
  27  *
  28  *     The above copyright notice and this permission notice shall be
  29  *     included in all copies or substantial portions of the Software.
  30  *
  31  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  32  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  33  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  34  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  35  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  36  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  37  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  38  *     OTHER DEALINGS IN THE SOFTWARE.
  39  */
  40
  41 #include <dt-bindings/gpio/gpio.h>
  42 #include <dt-bindings/interrupt-controller/irq.h>
  43 #include <dt-bindings/interrupt-controller/arm-gic.h>
  44 #include <dt-bindings/clock/rv1108-cru.h>
  45 #include <dt-bindings/pinctrl/rockchip.h>
  46 #include <dt-bindings/thermal/thermal.h>
  47 / {
  48         #address-cells = <1>;
  49         #size-cells = <1>;
  50
  51         compatible = "rockchip,rv1108";
  52
  53         interrupt-parent = <&gic>;
  54
  55         aliases {
  56                 i2c0 = &i2c0;
  57                 i2c1 = &i2c1;
  58                 i2c2 = &i2c2;
  59                 i2c3 = &i2c3;
  60                 serial0 = &uart0;
  61                 serial1 = &uart1;
  62                 serial2 = &uart2;
  63         };
  64
  65         cpus {
  66                 #address-cells = <1>;
  67                 #size-cells = <0>;
  68
  69                 cpu0: cpu@f00 {
  70                         device_type = "cpu";
  71                         compatible = "arm,cortex-a7";
  72                         reg = <0xf00>;
  73                         clocks = <&cru ARMCLK>;
  74                         #cooling-cells = <2>; /* min followed by max */
  75                         dynamic-power-coefficient = <75>;
  76                         operating-points-v2 = <&cpu_opp_table>;
  77                 };
  78         };
  79
  80         cpu_opp_table: opp_table {
  81                 compatible = "operating-points-v2";
  82
  83                 opp-408000000 {
  84                         opp-hz = /bits/ 64 <408000000>;
  85                         opp-microvolt = <975000>;
  86                         clock-latency-ns = <40000>;
  87                 };
  88                 opp-600000000 {
  89                         opp-hz = /bits/ 64 <600000000>;
  90                         opp-microvolt = <975000>;
  91                         clock-latency-ns = <40000>;
  92                 };
  93                 opp-816000000 {
  94                         opp-hz = /bits/ 64 <816000000>;
  95                         opp-microvolt = <1025000>;
  96                         clock-latency-ns = <40000>;
  97                 };
  98                 opp-1008000000 {
  99                         opp-hz = /bits/ 64 <1008000000>;
 100                         opp-microvolt = <1150000>;
 101                         clock-latency-ns = <40000>;
 102                 };
 103         };
 104
 105         arm-pmu {
 106                 compatible = "arm,cortex-a7-pmu";
 107                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 108         };
 109
 110         timer {
 111                 compatible = "arm,armv7-timer";
 112                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
 113                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
 114                 clock-frequency = <24000000>;
 115         };
 116
 117         xin24m: oscillator {
 118                 compatible = "fixed-clock";
 119                 clock-frequency = <24000000>;
 120                 clock-output-names = "xin24m";
 121                 #clock-cells = <0>;
 122         };
 123
 124         amba {
 125                 compatible = "simple-bus";
 126                 #address-cells = <1>;
 127                 #size-cells = <1>;
 128                 ranges;
 129
 130                 pdma: pdma@102a0000 {
 131                         compatible = "arm,pl330", "arm,primecell";
 132                         reg = <0x102a0000 0x4000>;
 133                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 134                         #dma-cells = <1>;
 135                         arm,pl330-broken-no-flushp;
 136                         clocks = <&cru ACLK_DMAC>;
 137                         clock-names = "apb_pclk";
 138                 };
 139         };
 140
 141         bus_intmem@10080000 {
 142                 compatible = "mmio-sram";
 143                 reg = <0x10080000 0x2000>;
 144                 #address-cells = <1>;
 145                 #size-cells = <1>;
 146                 ranges = <0 0x10080000 0x2000>;
 147         };
 148
 149         uart2: serial@10210000 {
 150                 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
 151                 reg = <0x10210000 0x100>;
 152                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 153                 reg-shift = <2>;
 154                 reg-io-width = <4>;
 155                 clock-frequency = <24000000>;
 156                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 157                 clock-names = "baudclk", "apb_pclk";
 158                 pinctrl-names = "default";
 159                 pinctrl-0 = <&uart2m0_xfer>;
 160                 status = "disabled";
 161         };
 162
 163         uart1: serial@10220000 {
 164                 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
 165                 reg = <0x10220000 0x100>;
 166                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 167                 reg-shift = <2>;
 168                 reg-io-width = <4>;
 169                 clock-frequency = <24000000>;
 170                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 171                 clock-names = "baudclk", "apb_pclk";
 172                 pinctrl-names = "default";
 173                 pinctrl-0 = <&uart1_xfer>;
 174                 status = "disabled";
 175         };
 176
 177         uart0: serial@10230000 {
 178                 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
 179                 reg = <0x10230000 0x100>;
 180                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 181                 reg-shift = <2>;
 182                 reg-io-width = <4>;
 183                 clock-frequency = <24000000>;
 184                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 185                 clock-names = "baudclk", "apb_pclk";
 186                 pinctrl-names = "default";
 187                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 188                 status = "disabled";
 189         };
 190
 191         i2c1: i2c@10240000 {
 192                 compatible = "rockchip,rv1108-i2c";
 193                 reg = <0x10240000 0x1000>;
 194                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 195                 #address-cells = <1>;
 196                 #size-cells = <0>;
 197                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 198                 clock-names = "i2c", "pclk";
 199                 pinctrl-names = "default";
 200                 pinctrl-0 = <&i2c1_xfer>;
 201                 rockchip,grf = <&grf>;
 202                 status = "disabled";
 203         };
 204
 205         i2c2: i2c@10250000 {
 206                 compatible = "rockchip,rv1108-i2c";
 207                 reg = <0x10250000 0x1000>;
 208                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 209                 #address-cells = <1>;
 210                 #size-cells = <0>;
 211                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 212                 clock-names = "i2c", "pclk";
 213                 pinctrl-names = "default";
 214                 pinctrl-0 = <&i2c2m1_xfer>;
 215                 rockchip,grf = <&grf>;
 216                 status = "disabled";
 217         };
 218
 219         i2c3: i2c@10260000 {
 220                 compatible = "rockchip,rv1108-i2c";
 221                 reg = <0x10260000 0x1000>;
 222                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 223                 #address-cells = <1>;
 224                 #size-cells = <0>;
 225                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 226                 clock-names = "i2c", "pclk";
 227                 pinctrl-names = "default";
 228                 pinctrl-0 = <&i2c3_xfer>;
 229                 rockchip,grf = <&grf>;
 230                 status = "disabled";
 231         };
 232
 233         spi: spi@10270000 {
 234                 compatible = "rockchip,rv1108-spi";
 235                 reg = <0x10270000 0x1000>;
 236                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 237                 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
 238                 clock-names = "spiclk", "apb_pclk";
 239                 dmas = <&pdma 8>, <&pdma 9>;
 240                 #dma-cells = <2>;
 241                 #address-cells = <1>;
 242                 #size-cells = <0>;
 243                 status = "disabled";
 244         };
 245
 246         pwm4: pwm@10280000 {
 247                 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
 248                 reg = <0x10280000 0x10>;
 249                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 250                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 251                 clock-names = "pwm", "pclk";
 252                 pinctrl-names = "default";
 253                 pinctrl-0 = <&pwm4_pin>;
 254                 #pwm-cells = <3>;
 255                 status = "disabled";
 256         };
 257
 258         pwm5: pwm@10280010 {
 259                 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
 260                 reg = <0x10280010 0x10>;
 261                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 262                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 263                 clock-names = "pwm", "pclk";
 264                 pinctrl-names = "default";
 265                 pinctrl-0 = <&pwm5_pin>;
 266                 #pwm-cells = <3>;
 267                 status = "disabled";
 268         };
 269
 270         pwm6: pwm@10280020 {
 271                 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
 272                 reg = <0x10280020 0x10>;
 273                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 274                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 275                 clock-names = "pwm", "pclk";
 276                 pinctrl-names = "default";
 277                 pinctrl-0 = <&pwm6_pin>;
 278                 #pwm-cells = <3>;
 279                 status = "disabled";
 280         };
 281
 282         pwm7: pwm@10280030 {
 283                 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
 284                 reg = <0x10280030 0x10>;
 285                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 286                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 287                 clock-names = "pwm", "pclk";
 288                 pinctrl-names = "default";
 289                 pinctrl-0 = <&pwm7_pin>;
 290                 #pwm-cells = <3>;
 291                 status = "disabled";
 292         };
 293
 294         grf: syscon@10300000 {
 295                 compatible = "rockchip,rv1108-grf", "syscon", "simple-mfd";
 296                 reg = <0x10300000 0x1000>;
 297                 #address-cells = <1>;
 298                 #size-cells = <1>;
 299
 300                 u2phy: usb2-phy@100 {
 301                         compatible = "rockchip,rv1108-usb2phy";
 302                         reg = <0x100 0x0c>;
 303                         clocks = <&cru SCLK_USBPHY>;
 304                         clock-names = "phyclk";
 305                         #clock-cells = <0>;
 306                         clock-output-names = "usbphy";
 307                         rockchip,usbgrf = <&usbgrf>;
 308                         status = "disabled";
 309
 310                         u2phy_otg: otg-port {
 311                                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 312                                 interrupt-names = "otg-mux";
 313                                 #phy-cells = <0>;
 314                                 status = "disabled";
 315                         };
 316
 317                         u2phy_host: host-port {
 318                                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 319                                 interrupt-names = "linestate";
 320                                 #phy-cells = <0>;
 321                                 status = "disabled";
 322                         };
 323                 };
 324         };
 325
 326         watchdog: wdt@10360000 {
 327                 compatible = "snps,dw-wdt";
 328                 reg = <0x10360000 0x100>;
 329                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 330                 clocks = <&cru PCLK_WDT>;
 331                 clock-names = "pclk_wdt";
 332                 status = "disabled";
 333         };
 334
 335         thermal-zones {
 336                 soc_thermal: soc-thermal {
 337                         polling-delay-passive = <20>;
 338                         polling-delay = <1000>;
 339                         sustainable-power = <50>;
 340                         thermal-sensors = <&tsadc 0>;
 341
 342                         trips {
 343                                 threshold: trip-point0 {
 344                                         temperature = <70000>;
 345                                         hysteresis = <2000>;
 346                                         type = "passive";
 347                                 };
 348                                 target: trip-point1 {
 349                                         temperature = <85000>;
 350                                         hysteresis = <2000>;
 351                                         type = "passive";
 352                                 };
 353                                 soc_crit: soc-crit {
 354                                         temperature = <95000>;
 355                                         hysteresis = <2000>;
 356                                         type = "critical";
 357                                 };
 358                         };
 359
 360                         cooling-maps {
 361                                 map0 {
 362                                         trip = <&target>;
 363                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 364                                         contribution = <4096>;
 365                                 };
 366                         };
 367                 };
 368         };
 369
 370         tsadc: tsadc@10370000 {
 371                 compatible = "rockchip,rv1108-tsadc";
 372                 reg = <0x10370000 0x100>;
 373                 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 374                 assigned-clocks = <&cru SCLK_TSADC>;
 375                 assigned-clock-rates = <750000>;
 376                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 377                 clock-names = "tsadc", "apb_pclk";
 378                 pinctrl-names = "init", "default", "sleep";
 379                 pinctrl-0 = <&otp_gpio>;
 380                 pinctrl-1 = <&otp_out>;
 381                 pinctrl-2 = <&otp_gpio>;
 382                 resets = <&cru SRST_TSADC>;
 383                 reset-names = "tsadc-apb";
 384                 rockchip,hw-tshut-temp = <120000>;
 385                 #thermal-sensor-cells = <1>;
 386                 status = "disabled";
 387         };
 388
 389         adc: adc@1038c000 {
 390                 compatible = "rockchip,rv1108-saradc", "rockchip,rk3399-saradc";
 391                 reg = <0x1038c000 0x100>;
 392                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 393                 #io-channel-cells = <1>;
 394                 clock-frequency = <1000000>;
 395                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 396                 clock-names = "saradc", "apb_pclk";
 397                 status = "disabled";
 398         };
 399
 400         i2c0: i2c@20000000 {
 401                 compatible = "rockchip,rv1108-i2c";
 402                 reg = <0x20000000 0x1000>;
 403                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 404                 #address-cells = <1>;
 405                 #size-cells = <0>;
 406                 clocks = <&cru SCLK_I2C0_PMU>, <&cru PCLK_I2C0_PMU>;
 407                 clock-names = "i2c", "pclk";
 408                 pinctrl-names = "default";
 409                 pinctrl-0 = <&i2c0_xfer>;
 410                 rockchip,grf = <&grf>;
 411                 status = "disabled";
 412         };
 413
 414         pwm0: pwm@20040000 {
 415                 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
 416                 reg = <0x20040000 0x10>;
 417                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 418                 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
 419                 clock-names = "pwm", "pclk";
 420                 pinctrl-names = "default";
 421                 pinctrl-0 = <&pwm0_pin>;
 422                 #pwm-cells = <3>;
 423                 status = "disabled";
 424         };
 425
 426         pwm1: pwm@20040010 {
 427                 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
 428                 reg = <0x20040010 0x10>;
 429                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 430                 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
 431                 clock-names = "pwm", "pclk";
 432                 pinctrl-names = "default";
 433                 pinctrl-0 = <&pwm1_pin>;
 434                 #pwm-cells = <3>;
 435                 status = "disabled";
 436         };
 437
 438         pwm2: pwm@20040020 {
 439                 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
 440                 reg = <0x20040020 0x10>;
 441                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 442                 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
 443                 clock-names = "pwm", "pclk";
 444                 pinctrl-names = "default";
 445                 pinctrl-0 = <&pwm2_pin>;
 446                 #pwm-cells = <3>;
 447                 status = "disabled";
 448         };
 449
 450         pwm3: pwm@20040030 {
 451                 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
 452                 reg = <0x20040030 0x10>;
 453                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 454                 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
 455                 clock-names = "pwm", "pclk";
 456                 pinctrl-names = "default";
 457                 pinctrl-0 = <&pwm3_pin>;
 458                 #pwm-cells = <3>;
 459                 status = "disabled";
 460         };
 461
 462         pmugrf: syscon@20060000 {
 463                 compatible = "rockchip,rv1108-pmugrf", "syscon";
 464                 reg = <0x20060000 0x1000>;
 465         };
 466
 467         usbgrf: syscon@202a0000 {
 468                 compatible = "rockchip,rv1108-usbgrf", "syscon";
 469                 reg = <0x202a0000 0x1000>;
 470         };
 471
 472         cru: clock-controller@20200000 {
 473                 compatible = "rockchip,rv1108-cru";
 474                 reg = <0x20200000 0x1000>;
 475                 rockchip,grf = <&grf>;
 476                 #clock-cells = <1>;
 477                 #reset-cells = <1>;
 478         };
 479
 480         emmc: dwmmc@30110000 {
 481                 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
 482                 reg = <0x30110000 0x4000>;
 483                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 484                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 485                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 486                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 487                 fifo-depth = <0x100>;
 488                 max-frequency = <150000000>;
 489                 status = "disabled";
 490         };
 491
 492         sdio: dwmmc@30120000 {
 493                 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
 494                 reg = <0x30120000 0x4000>;
 495                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 496                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 497                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 498                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 499                 fifo-depth = <0x100>;
 500                 max-frequency = <150000000>;
 501                 status = "disabled";
 502         };
 503
 504         sdmmc: dwmmc@30130000 {
 505                 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
 506                 reg = <0x30130000 0x4000>;
 507                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 508                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 509                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 510                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 511                 fifo-depth = <0x100>;
 512                 max-frequency = <100000000>;
 513                 pinctrl-names = "default";
 514                 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
 515                 status = "disabled";
 516         };
 517
 518         usb_host_ehci: usb@30140000 {
 519                 compatible = "generic-ehci";
 520                 reg = <0x30140000 0x20000>;
 521                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 522                 clocks = <&cru HCLK_HOST0>, <&u2phy>;
 523                 clock-names = "usbhost", "utmi";
 524                 phys = <&u2phy_host>;
 525                 phy-names = "usb";
 526                 status = "disabled";
 527         };
 528
 529         usb_host_ohci: usb@30160000 {
 530                 compatible = "generic-ohci";
 531                 reg = <0x30160000 0x20000>;
 532                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 533                 clocks = <&cru HCLK_HOST0>, <&u2phy>;
 534                 clock-names = "usbhost", "utmi";
 535                 phys = <&u2phy_host>;
 536                 phy-names = "usb";
 537                 status = "disabled";
 538         };
 539
 540         usb_otg: usb@30180000 {
 541                 compatible = "rockchip,rv1108-usb", "rockchip,rk3066-usb",
 542                              "snps,dwc2";
 543                 reg = <0x30180000 0x40000>;
 544                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 545                 clocks = <&cru HCLK_OTG>;
 546                 clock-names = "otg";
 547                 dr_mode = "otg";
 548                 g-np-tx-fifo-size = <16>;
 549                 g-rx-fifo-size = <280>;
 550                 g-tx-fifo-size = <256 128 128 64 32 16>;
 551                 g-use-dma;
 552                 phys = <&u2phy_otg>;
 553                 phy-names = "usb2-phy";
 554                 status = "disabled";
 555         };
 556
 557         gic: interrupt-controller@32010000 {
 558                 compatible = "arm,gic-400";
 559                 interrupt-controller;
 560                 #interrupt-cells = <3>;
 561                 #address-cells = <0>;
 562
 563                 reg = <0x32011000 0x1000>,
 564                       <0x32012000 0x2000>,
 565                       <0x32014000 0x2000>,
 566                       <0x32016000 0x2000>;
 567                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
 568         };
 569
 570         pinctrl: pinctrl {
 571                 compatible = "rockchip,rv1108-pinctrl";
 572                 rockchip,grf = <&grf>;
 573                 rockchip,pmu = <&pmugrf>;
 574                 #address-cells = <1>;
 575                 #size-cells = <1>;
 576                 ranges;
 577
 578                 gpio0: gpio0@20030000 {
 579                         compatible = "rockchip,gpio-bank";
 580                         reg = <0x20030000 0x100>;
 581                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 582                         clocks = <&xin24m>;
 583
 584                         gpio-controller;
 585                         #gpio-cells = <2>;
 586
 587                         interrupt-controller;
 588                         #interrupt-cells = <2>;
 589                 };
 590
 591                 gpio1: gpio1@10310000 {
 592                         compatible = "rockchip,gpio-bank";
 593                         reg = <0x10310000 0x100>;
 594                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 595                         clocks = <&xin24m>;
 596
 597                         gpio-controller;
 598                         #gpio-cells = <2>;
 599
 600                         interrupt-controller;
 601                         #interrupt-cells = <2>;
 602                 };
 603
 604                 gpio2: gpio2@10320000 {
 605                         compatible = "rockchip,gpio-bank";
 606                         reg = <0x10320000 0x100>;
 607                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 608                         clocks = <&xin24m>;
 609
 610                         gpio-controller;
 611                         #gpio-cells = <2>;
 612
 613                         interrupt-controller;
 614                         #interrupt-cells = <2>;
 615                 };
 616
 617                 gpio3: gpio3@10330000 {
 618                         compatible = "rockchip,gpio-bank";
 619                         reg = <0x10330000 0x100>;
 620                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 621                         clocks = <&xin24m>;
 622
 623                         gpio-controller;
 624                         #gpio-cells = <2>;
 625
 626                         interrupt-controller;
 627                         #interrupt-cells = <2>;
 628                 };
 629
 630                 pcfg_pull_up: pcfg-pull-up {
 631                         bias-pull-up;
 632                 };
 633
 634                 pcfg_pull_down: pcfg-pull-down {
 635                         bias-pull-down;
 636                 };
 637
 638                 pcfg_pull_none: pcfg-pull-none {
 639                         bias-disable;
 640                 };
 641
 642                 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
 643                         drive-strength = <8>;
 644                 };
 645
 646                 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
 647                         drive-strength = <12>;
 648                 };
 649
 650                 pcfg_pull_none_smt: pcfg-pull-none-smt {
 651                         bias-disable;
 652                         input-schmitt-enable;
 653                 };
 654
 655                 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
 656                         bias-pull-up;
 657                         drive-strength = <8>;
 658                 };
 659
 660                 pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
 661                         drive-strength = <4>;
 662                 };
 663
 664                 pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
 665                         bias-pull-up;
 666                         drive-strength = <4>;
 667                 };
 668
 669                 pcfg_output_high: pcfg-output-high {
 670                         output-high;
 671                 };
 672
 673                 pcfg_output_low: pcfg-output-low {
 674                         output-low;
 675                 };
 676
 677                 pcfg_input_high: pcfg-input-high {
 678                         bias-pull-up;
 679                         input-enable;
 680                 };
 681
 682                 i2c0 {
 683                         i2c0_xfer: i2c0-xfer {
 684                                 rockchip,pins = <0 RK_PB1 RK_FUNC_1 &pcfg_pull_none_smt>,
 685                                                 <0 RK_PB2 RK_FUNC_1 &pcfg_pull_none_smt>;
 686                         };
 687                 };
 688
 689                 i2c1 {
 690                         i2c1_xfer: i2c1-xfer {
 691                                 rockchip,pins = <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>,
 692                                                 <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>;
 693                         };
 694                 };
 695
 696                 i2c2m1 {
 697                         i2c2m1_xfer: i2c2m1-xfer {
 698                                 rockchip,pins = <0 RK_PC2 RK_FUNC_2 &pcfg_pull_none>,
 699                                                 <0 RK_PC6 RK_FUNC_3 &pcfg_pull_none>;
 700                         };
 701
 702                         i2c2m1_gpio: i2c2m1-gpio {
 703                                 rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>,
 704                                                 <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
 705                         };
 706                 };
 707
 708                 i2c2m05v {
 709                         i2c2m05v_xfer: i2c2m05v-xfer {
 710                                 rockchip,pins = <1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>,
 711                                                 <1 RK_PD4 RK_FUNC_2 &pcfg_pull_none>;
 712                         };
 713
 714                         i2c2m05v_gpio: i2c2m05v-gpio {
 715                                 rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>,
 716                                                 <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
 717                         };
 718                 };
 719
 720                 i2c3 {
 721                         i2c3_xfer: i2c3-xfer {
 722                                 rockchip,pins = <0 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
 723                                                 <0 RK_PC4 RK_FUNC_2 &pcfg_pull_none>;
 724                         };
 725                 };
 726
 727                 pwm0 {
 728                         pwm0_pin: pwm0-pin {
 729                                 rockchip,pins = <0 RK_PC5 RK_FUNC_1 &pcfg_pull_none>;
 730                         };
 731                 };
 732
 733                 pwm1 {
 734                         pwm1_pin: pwm1-pin {
 735                                 rockchip,pins = <0 RK_PC4 RK_FUNC_1 &pcfg_pull_none>;
 736                         };
 737                 };
 738
 739                 pwm2 {
 740                         pwm2_pin: pwm2-pin {
 741                                 rockchip,pins = <0 RK_PC6 RK_FUNC_1 &pcfg_pull_none>;
 742                         };
 743                 };
 744
 745                 pwm3 {
 746                         pwm3_pin: pwm3-pin {
 747                                 rockchip,pins = <0 RK_PC0 RK_FUNC_1 &pcfg_pull_none>;
 748                         };
 749                 };
 750
 751                 pwm4 {
 752                         pwm4_pin: pwm4-pin {
 753                                 rockchip,pins = <1 RK_PC1 RK_FUNC_3 &pcfg_pull_none>;
 754                         };
 755                 };
 756
 757                 pwm5 {
 758                         pwm5_pin: pwm5-pin {
 759                                 rockchip,pins = <1 RK_PA7 RK_FUNC_2 &pcfg_pull_none>;
 760                         };
 761                 };
 762
 763                 pwm6 {
 764                         pwm6_pin: pwm6-pin {
 765                                 rockchip,pins = <1 RK_PB0 RK_FUNC_2 &pcfg_pull_none>;
 766                         };
 767                 };
 768
 769                 pwm7 {
 770                         pwm7_pin: pwm7-pin {
 771                                 rockchip,pins = <1 RK_PB1 RK_FUNC_2 &pcfg_pull_none>;
 772                         };
 773                 };
 774
 775                 sdmmc {
 776                         sdmmc_clk: sdmmc-clk {
 777                                 rockchip,pins = <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
 778                         };
 779
 780                         sdmmc_cmd: sdmmc-cmd {
 781                                 rockchip,pins = <3 RK_PC5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
 782                         };
 783
 784                         sdmmc_cd: sdmmc-cd {
 785                                 rockchip,pins = <0 RK_PA1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
 786                         };
 787
 788                         sdmmc_bus1: sdmmc-bus1 {
 789                                 rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
 790                         };
 791
 792                         sdmmc_bus4: sdmmc-bus4 {
 793                                 rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
 794                                                 <3 RK_PC2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
 795                                                 <3 RK_PC1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
 796                                                 <3 RK_PC0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
 797                         };
 798                 };
 799
 800                 tsadc {
 801                         otp_out: otp-out {
 802                                 rockchip,pins = <0 RK_PB7 RK_FUNC_1 &pcfg_pull_none>;
 803                         };
 804
 805                         otp_gpio: otp-gpio {
 806                                 rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
 807                         };
 808                 };
 809
 810                 uart0 {
 811                         uart0_xfer: uart0-xfer {
 812                                 rockchip,pins = <3 RK_PA6 RK_FUNC_1 &pcfg_pull_up>,
 813                                                 <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>;
 814                         };
 815
 816                         uart0_cts: uart0-cts {
 817                                 rockchip,pins = <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>;
 818                         };
 819
 820                         uart0_rts: uart0-rts {
 821                                 rockchip,pins = <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>;
 822                         };
 823
 824                         uart0_rts_gpio: uart0-rts-gpio {
 825                                 rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
 826                         };
 827                 };
 828
 829                 uart1 {
 830                         uart1_xfer: uart1-xfer {
 831                                 rockchip,pins = <1 RK_PD3 RK_FUNC_1 &pcfg_pull_up>,
 832                                                 <1 RK_PD2 RK_FUNC_1 &pcfg_pull_none>;
 833                         };
 834
 835                         uart1_cts: uart1-cts {
 836                                 rockchip,pins = <1 RK_PD0 RK_FUNC_1 &pcfg_pull_none>;
 837                         };
 838
 839                         uart1_rts: uart1-rts {
 840                                 rockchip,pins = <1 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
 841                         };
 842                 };
 843
 844                 uart2m0 {
 845                         uart2m0_xfer: uart2m0-xfer {
 846                                 rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>,
 847                                                 <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
 848                         };
 849                 };
 850
 851                 uart2m1 {
 852                         uart2m1_xfer: uart2m1-xfer {
 853                                 rockchip,pins = <3 RK_PC3 RK_FUNC_2 &pcfg_pull_up>,
 854                                                 <3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>;
 855                         };
 856                 };
 857
 858                 uart2_5v {
 859                         uart2_5v_cts: uart2_5v-cts {
 860                                 rockchip,pins = <1 RK_PD4 RK_FUNC_1 &pcfg_pull_none>;
 861                         };
 862
 863                         uart2_5v_rts: uart2_5v-rts {
 864                                 rockchip,pins = <1 RK_PD5 RK_FUNC_1 &pcfg_pull_none>;
 865                         };
 866                 };
 867         };
 868 };