]> git.proxmox.com Git - mirror_ubuntu-focal-kernel.git/blob - arch/arm/boot/dts/sama5d2.dtsi
projects / mirror_ubuntu-focal-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge tag 'socfpga_updates_for_v4.20_part3' of git://git.kernel.org/pub/scm/linux...
[mirror_ubuntu-focal-kernel.git] / arch / arm / boot / dts / sama5d2.dtsi
1 /*
2 * sama5d2.dtsi - Device Tree Include file for SAMA5D2 family SoC
3 *
4 * Copyright (C) 2015 Atmel,
5 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com>
6 *
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
10 * whole.
11 *
12 * a) This file is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
16 *
17 * This file is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * Or, alternatively,
23 *
24 * b) Permission is hereby granted, free of charge, to any person
25 * obtaining a copy of this software and associated documentation
26 * files (the "Software"), to deal in the Software without
27 * restriction, including without limitation the rights to use,
28 * copy, modify, merge, publish, distribute, sublicense, and/or
29 * sell copies of the Software, and to permit persons to whom the
30 * Software is furnished to do so, subject to the following
31 * conditions:
32 *
33 * The above copyright notice and this permission notice shall be
34 * included in all copies or substantial portions of the Software.
35 *
36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 * OTHER DEALINGS IN THE SOFTWARE.
44 */
45
46 #include "skeleton.dtsi"
47 #include <dt-bindings/dma/at91.h>
48 #include <dt-bindings/interrupt-controller/irq.h>
49 #include <dt-bindings/clock/at91.h>
50 #include <dt-bindings/iio/adc/at91-sama5d2_adc.h>
51
52 / {
53 model = "Atmel SAMA5D2 family SoC";
54 compatible = "atmel,sama5d2";
55 interrupt-parent = <&aic>;
56
57 aliases {
58 serial0 = &uart1;
59 serial1 = &uart3;
60 tcb0 = &tcb0;
61 tcb1 = &tcb1;
62 i2s0 = &i2s0;
63 i2s1 = &i2s1;
64 };
65
66 cpus {
67 #address-cells = <1>;
68 #size-cells = <0>;
69
70 cpu@0 {
71 device_type = "cpu";
72 compatible = "arm,cortex-a5";
73 reg = <0>;
74 next-level-cache = <&L2>;
75 };
76 };
77
78 pmu {
79 compatible = "arm,cortex-a5-pmu";
80 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 0>;
81 };
82
83 etb {
84 compatible = "arm,coresight-etb10", "arm,primecell";
85 reg = <0x740000 0x1000>;
86
87 clocks = <&mck>;
88 clock-names = "apb_pclk";
89
90 in-ports {
91 port {
92 etb_in: endpoint {
93 remote-endpoint = <&etm_out>;
94 };
95 };
96 };
97 };
98
99 etm {
100 compatible = "arm,coresight-etm3x", "arm,primecell";
101 reg = <0x73C000 0x1000>;
102
103 clocks = <&mck>;
104 clock-names = "apb_pclk";
105
106 out-ports {
107 port {
108 etm_out: endpoint {
109 remote-endpoint = <&etb_in>;
110 };
111 };
112 };
113 };
114
115 memory {
116 reg = <0x20000000 0x20000000>;
117 };
118
119 clocks {
120 slow_xtal: slow_xtal {
121 compatible = "fixed-clock";
122 #clock-cells = <0>;
123 clock-frequency = <0>;
124 };
125
126 main_xtal: main_xtal {
127 compatible = "fixed-clock";
128 #clock-cells = <0>;
129 clock-frequency = <0>;
130 };
131 };
132
133 ns_sram: sram@200000 {
134 compatible = "mmio-sram";
135 reg = <0x00200000 0x20000>;
136 };
137
138 ahb {
139 compatible = "simple-bus";
140 #address-cells = <1>;
141 #size-cells = <1>;
142 ranges;
143
144 nfc_sram: sram@100000 {
145 compatible = "mmio-sram";
146 no-memory-wc;
147 reg = <0x00100000 0x2400>;
148 };
149
150 usb0: gadget@300000 {
151 #address-cells = <1>;
152 #size-cells = <0>;
153 compatible = "atmel,sama5d3-udc";
154 reg = <0x00300000 0x100000
155 0xfc02c000 0x400>;
156 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 2>;
157 clocks = <&udphs_clk>, <&utmi>;
158 clock-names = "pclk", "hclk";
159 status = "disabled";
160
161 ep@0 {
162 reg = <0>;
163 atmel,fifo-size = <64>;
164 atmel,nb-banks = <1>;
165 };
166
167 ep@1 {
168 reg = <1>;
169 atmel,fifo-size = <1024>;
170 atmel,nb-banks = <3>;
171 atmel,can-dma;
172 atmel,can-isoc;
173 };
174
175 ep@2 {
176 reg = <2>;
177 atmel,fifo-size = <1024>;
178 atmel,nb-banks = <3>;
179 atmel,can-dma;
180 atmel,can-isoc;
181 };
182
183 ep@3 {
184 reg = <3>;
185 atmel,fifo-size = <1024>;
186 atmel,nb-banks = <2>;
187 atmel,can-dma;
188 atmel,can-isoc;
189 };
190
191 ep@4 {
192 reg = <4>;
193 atmel,fifo-size = <1024>;
194 atmel,nb-banks = <2>;
195 atmel,can-dma;
196 atmel,can-isoc;
197 };
198
199 ep@5 {
200 reg = <5>;
201 atmel,fifo-size = <1024>;
202 atmel,nb-banks = <2>;
203 atmel,can-dma;
204 atmel,can-isoc;
205 };
206
207 ep@6 {
208 reg = <6>;
209 atmel,fifo-size = <1024>;
210 atmel,nb-banks = <2>;
211 atmel,can-dma;
212 atmel,can-isoc;
213 };
214
215 ep@7 {
216 reg = <7>;
217 atmel,fifo-size = <1024>;
218 atmel,nb-banks = <2>;
219 atmel,can-dma;
220 atmel,can-isoc;
221 };
222
223 ep@8 {
224 reg = <8>;
225 atmel,fifo-size = <1024>;
226 atmel,nb-banks = <2>;
227 atmel,can-isoc;
228 };
229
230 ep@9 {
231 reg = <9>;
232 atmel,fifo-size = <1024>;
233 atmel,nb-banks = <2>;
234 atmel,can-isoc;
235 };
236
237 ep@10 {
238 reg = <10>;
239 atmel,fifo-size = <1024>;
240 atmel,nb-banks = <2>;
241 atmel,can-isoc;
242 };
243
244 ep@11 {
245 reg = <11>;
246 atmel,fifo-size = <1024>;
247 atmel,nb-banks = <2>;
248 atmel,can-isoc;
249 };
250
251 ep@12 {
252 reg = <12>;
253 atmel,fifo-size = <1024>;
254 atmel,nb-banks = <2>;
255 atmel,can-isoc;
256 };
257
258 ep@13 {
259 reg = <13>;
260 atmel,fifo-size = <1024>;
261 atmel,nb-banks = <2>;
262 atmel,can-isoc;
263 };
264
265 ep@14 {
266 reg = <14>;
267 atmel,fifo-size = <1024>;
268 atmel,nb-banks = <2>;
269 atmel,can-isoc;
270 };
271
272 ep@15 {
273 reg = <15>;
274 atmel,fifo-size = <1024>;
275 atmel,nb-banks = <2>;
276 atmel,can-isoc;
277 };
278 };
279
280 usb1: ohci@400000 {
281 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
282 reg = <0x00400000 0x100000>;
283 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>;
284 clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
285 clock-names = "ohci_clk", "hclk", "uhpck";
286 status = "disabled";
287 };
288
289 usb2: ehci@500000 {
290 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
291 reg = <0x00500000 0x100000>;
292 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>;
293 clocks = <&utmi>, <&uhphs_clk>;
294 clock-names = "usb_clk", "ehci_clk";
295 status = "disabled";
296 };
297
298 L2: cache-controller@a00000 {
299 compatible = "arm,pl310-cache";
300 reg = <0x00a00000 0x1000>;
301 interrupts = <63 IRQ_TYPE_LEVEL_HIGH 4>;
302 cache-unified;
303 cache-level = <2>;
304 };
305
306 ebi: ebi@10000000 {
307 compatible = "atmel,sama5d3-ebi";
308 #address-cells = <2>;
309 #size-cells = <1>;
310 atmel,smc = <&hsmc>;
311 reg = <0x10000000 0x10000000
312 0x60000000 0x30000000>;
313 ranges = <0x0 0x0 0x10000000 0x10000000
314 0x1 0x0 0x60000000 0x10000000
315 0x2 0x0 0x70000000 0x10000000
316 0x3 0x0 0x80000000 0x10000000>;
317 clocks = <&mck>;
318 status = "disabled";
319
320 nand_controller: nand-controller {
321 compatible = "atmel,sama5d3-nand-controller";
322 atmel,nfc-sram = <&nfc_sram>;
323 atmel,nfc-io = <&nfc_io>;
324 ecc-engine = <&pmecc>;
325 #address-cells = <2>;
326 #size-cells = <1>;
327 ranges;
328 status = "disabled";
329 };
330 };
331
332 sdmmc0: sdio-host@a0000000 {
333 compatible = "atmel,sama5d2-sdhci";
334 reg = <0xa0000000 0x300>;
335 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
336 clocks = <&sdmmc0_hclk>, <&sdmmc0_gclk>, <&main>;
337 clock-names = "hclock", "multclk", "baseclk";
338 status = "disabled";
339 };
340
341 sdmmc1: sdio-host@b0000000 {
342 compatible = "atmel,sama5d2-sdhci";
343 reg = <0xb0000000 0x300>;
344 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 0>;
345 clocks = <&sdmmc1_hclk>, <&sdmmc1_gclk>, <&main>;
346 clock-names = "hclock", "multclk", "baseclk";
347 status = "disabled";
348 };
349
350 nfc_io: nfc-io@c0000000 {
351 compatible = "atmel,sama5d3-nfc-io", "syscon";
352 reg = <0xc0000000 0x8000000>;
353 };
354
355 apb {
356 compatible = "simple-bus";
357 #address-cells = <1>;
358 #size-cells = <1>;
359 ranges;
360
361 hlcdc: hlcdc@f0000000 {
362 compatible = "atmel,sama5d2-hlcdc";
363 reg = <0xf0000000 0x2000>;
364 interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>;
365 clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
366 clock-names = "periph_clk","sys_clk", "slow_clk";
367 status = "disabled";
368
369 hlcdc-display-controller {
370 compatible = "atmel,hlcdc-display-controller";
371 #address-cells = <1>;
372 #size-cells = <0>;
373
374 port@0 {
375 #address-cells = <1>;
376 #size-cells = <0>;
377 reg = <0>;
378 };
379 };
380
381 hlcdc_pwm: hlcdc-pwm {
382 compatible = "atmel,hlcdc-pwm";
383 #pwm-cells = <3>;
384 };
385 };
386
387 isc: isc@f0008000 {
388 compatible = "atmel,sama5d2-isc";
389 reg = <0xf0008000 0x4000>;
390 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 5>;
391 clocks = <&isc_clk>, <&iscck>, <&isc_gclk>;
392 clock-names = "hclock", "iscck", "gck";
393 #clock-cells = <0>;
394 clock-output-names = "isc-mck";
395 status = "disabled";
396 };
397
398 ramc0: ramc@f000c000 {
399 compatible = "atmel,sama5d3-ddramc";
400 reg = <0xf000c000 0x200>;
401 clocks = <&ddrck>, <&mpddr_clk>;
402 clock-names = "ddrck", "mpddr";
403 };
404
405 dma0: dma-controller@f0010000 {
406 compatible = "atmel,sama5d4-dma";
407 reg = <0xf0010000 0x1000>;
408 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>;
409 #dma-cells = <1>;
410 clocks = <&dma0_clk>;
411 clock-names = "dma_clk";
412 };
413
414 /* Place dma1 here despite its address */
415 dma1: dma-controller@f0004000 {
416 compatible = "atmel,sama5d4-dma";
417 reg = <0xf0004000 0x1000>;
418 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 0>;
419 #dma-cells = <1>;
420 clocks = <&dma1_clk>;
421 clock-names = "dma_clk";
422 };
423
424 pmc: pmc@f0014000 {
425 compatible = "atmel,sama5d2-pmc", "syscon";
426 reg = <0xf0014000 0x160>;
427 interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>;
428 interrupt-controller;
429 #address-cells = <1>;
430 #size-cells = <0>;
431 #interrupt-cells = <1>;
432
433 main_rc_osc: main_rc_osc {
434 compatible = "atmel,at91sam9x5-clk-main-rc-osc";
435 #clock-cells = <0>;
436 interrupt-parent = <&pmc>;
437 interrupts = <AT91_PMC_MOSCRCS>;
438 clock-frequency = <12000000>;
439 clock-accuracy = <100000000>;
440 };
441
442 main_osc: main_osc {
443 compatible = "atmel,at91rm9200-clk-main-osc";
444 #clock-cells = <0>;
445 interrupt-parent = <&pmc>;
446 interrupts = <AT91_PMC_MOSCS>;
447 clocks = <&main_xtal>;
448 };
449
450 main: mainck {
451 compatible = "atmel,at91sam9x5-clk-main";
452 #clock-cells = <0>;
453 interrupt-parent = <&pmc>;
454 interrupts = <AT91_PMC_MOSCSELS>;
455 clocks = <&main_rc_osc &main_osc>;
456 };
457
458 plla: pllack {
459 compatible = "atmel,sama5d3-clk-pll";
460 #clock-cells = <0>;
461 interrupt-parent = <&pmc>;
462 interrupts = <AT91_PMC_LOCKA>;
463 clocks = <&main>;
464 reg = <0>;
465 atmel,clk-input-range = <12000000 12000000>;
466 #atmel,pll-clk-output-range-cells = <4>;
467 atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>;
468 };
469
470 plladiv: plladivck {
471 compatible = "atmel,at91sam9x5-clk-plldiv";
472 #clock-cells = <0>;
473 clocks = <&plla>;
474 };
475
476 audio_pll_frac: audiopll_fracck {
477 compatible = "atmel,sama5d2-clk-audio-pll-frac";
478 #clock-cells = <0>;
479 clocks = <&main>;
480 };
481
482 audio_pll_pad: audiopll_padck {
483 compatible = "atmel,sama5d2-clk-audio-pll-pad";
484 #clock-cells = <0>;
485 clocks = <&audio_pll_frac>;
486 };
487
488 audio_pll_pmc: audiopll_pmcck {
489 compatible = "atmel,sama5d2-clk-audio-pll-pmc";
490 #clock-cells = <0>;
491 clocks = <&audio_pll_frac>;
492 };
493
494 utmi: utmick {
495 compatible = "atmel,at91sam9x5-clk-utmi";
496 #clock-cells = <0>;
497 interrupt-parent = <&pmc>;
498 interrupts = <AT91_PMC_LOCKU>;
499 clocks = <&main>;
500 };
501
502 mck: masterck {
503 compatible = "atmel,at91sam9x5-clk-master";
504 #clock-cells = <0>;
505 interrupt-parent = <&pmc>;
506 interrupts = <AT91_PMC_MCKRDY>;
507 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
508 atmel,clk-output-range = <124000000 166000000>;
509 atmel,clk-divisors = <1 2 4 3>;
510 };
511
512 h32ck: h32mxck {
513 #clock-cells = <0>;
514 compatible = "atmel,sama5d4-clk-h32mx";
515 clocks = <&mck>;
516 };
517
518 usb: usbck {
519 compatible = "atmel,at91sam9x5-clk-usb";
520 #clock-cells = <0>;
521 clocks = <&plladiv>, <&utmi>;
522 };
523
524 prog: progck {
525 compatible = "atmel,at91sam9x5-clk-programmable";
526 #address-cells = <1>;
527 #size-cells = <0>;
528 interrupt-parent = <&pmc>;
529 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
530
531 prog0: prog0 {
532 #clock-cells = <0>;
533 reg = <0>;
534 interrupts = <AT91_PMC_PCKRDY(0)>;
535 };
536
537 prog1: prog1 {
538 #clock-cells = <0>;
539 reg = <1>;
540 interrupts = <AT91_PMC_PCKRDY(1)>;
541 };
542
543 prog2: prog2 {
544 #clock-cells = <0>;
545 reg = <2>;
546 interrupts = <AT91_PMC_PCKRDY(2)>;
547 };
548 };
549
550 systemck {
551 compatible = "atmel,at91rm9200-clk-system";
552 #address-cells = <1>;
553 #size-cells = <0>;
554
555 ddrck: ddrck {
556 #clock-cells = <0>;
557 reg = <2>;
558 clocks = <&mck>;
559 };
560
561 lcdck: lcdck {
562 #clock-cells = <0>;
563 reg = <3>;
564 clocks = <&mck>;
565 };
566
567 uhpck: uhpck {
568 #clock-cells = <0>;
569 reg = <6>;
570 clocks = <&usb>;
571 };
572
573 udpck: udpck {
574 #clock-cells = <0>;
575 reg = <7>;
576 clocks = <&usb>;
577 };
578
579 pck0: pck0 {
580 #clock-cells = <0>;
581 reg = <8>;
582 clocks = <&prog0>;
583 };
584
585 pck1: pck1 {
586 #clock-cells = <0>;
587 reg = <9>;
588 clocks = <&prog1>;
589 };
590
591 pck2: pck2 {
592 #clock-cells = <0>;
593 reg = <10>;
594 clocks = <&prog2>;
595 };
596
597 iscck: iscck {
598 #clock-cells = <0>;
599 reg = <18>;
600 clocks = <&mck>;
601 };
602 };
603
604 periph32ck {
605 compatible = "atmel,at91sam9x5-clk-peripheral";
606 #address-cells = <1>;
607 #size-cells = <0>;
608 clocks = <&h32ck>;
609
610 macb0_clk: macb0_clk {
611 #clock-cells = <0>;
612 reg = <5>;
613 atmel,clk-output-range = <0 83000000>;
614 };
615
616 tdes_clk: tdes_clk {
617 #clock-cells = <0>;
618 reg = <11>;
619 atmel,clk-output-range = <0 83000000>;
620 };
621
622 matrix1_clk: matrix1_clk {
623 #clock-cells = <0>;
624 reg = <14>;
625 };
626
627 hsmc_clk: hsmc_clk {
628 #clock-cells = <0>;
629 reg = <17>;
630 };
631
632 pioA_clk: pioA_clk {
633 #clock-cells = <0>;
634 reg = <18>;
635 atmel,clk-output-range = <0 83000000>;
636 };
637
638 flx0_clk: flx0_clk {
639 #clock-cells = <0>;
640 reg = <19>;
641 atmel,clk-output-range = <0 83000000>;
642 };
643
644 flx1_clk: flx1_clk {
645 #clock-cells = <0>;
646 reg = <20>;
647 atmel,clk-output-range = <0 83000000>;
648 };
649
650 flx2_clk: flx2_clk {
651 #clock-cells = <0>;
652 reg = <21>;
653 atmel,clk-output-range = <0 83000000>;
654 };
655
656 flx3_clk: flx3_clk {
657 #clock-cells = <0>;
658 reg = <22>;
659 atmel,clk-output-range = <0 83000000>;
660 };
661
662 flx4_clk: flx4_clk {
663 #clock-cells = <0>;
664 reg = <23>;
665 atmel,clk-output-range = <0 83000000>;
666 };
667
668 uart0_clk: uart0_clk {
669 #clock-cells = <0>;
670 reg = <24>;
671 atmel,clk-output-range = <0 83000000>;
672 };
673
674 uart1_clk: uart1_clk {
675 #clock-cells = <0>;
676 reg = <25>;
677 atmel,clk-output-range = <0 83000000>;
678 };
679
680 uart2_clk: uart2_clk {
681 #clock-cells = <0>;
682 reg = <26>;
683 atmel,clk-output-range = <0 83000000>;
684 };
685
686 uart3_clk: uart3_clk {
687 #clock-cells = <0>;
688 reg = <27>;
689 atmel,clk-output-range = <0 83000000>;
690 };
691
692 uart4_clk: uart4_clk {
693 #clock-cells = <0>;
694 reg = <28>;
695 atmel,clk-output-range = <0 83000000>;
696 };
697
698 twi0_clk: twi0_clk {
699 reg = <29>;
700 #clock-cells = <0>;
701 atmel,clk-output-range = <0 83000000>;
702 };
703
704 twi1_clk: twi1_clk {
705 #clock-cells = <0>;
706 reg = <30>;
707 atmel,clk-output-range = <0 83000000>;
708 };
709
710 spi0_clk: spi0_clk {
711 #clock-cells = <0>;
712 reg = <33>;
713 atmel,clk-output-range = <0 83000000>;
714 };
715
716 spi1_clk: spi1_clk {
717 #clock-cells = <0>;
718 reg = <34>;
719 atmel,clk-output-range = <0 83000000>;
720 };
721
722 tcb0_clk: tcb0_clk {
723 #clock-cells = <0>;
724 reg = <35>;
725 atmel,clk-output-range = <0 83000000>;
726 };
727
728 tcb1_clk: tcb1_clk {
729 #clock-cells = <0>;
730 reg = <36>;
731 atmel,clk-output-range = <0 83000000>;
732 };
733
734 pwm_clk: pwm_clk {
735 #clock-cells = <0>;
736 reg = <38>;
737 atmel,clk-output-range = <0 83000000>;
738 };
739
740 adc_clk: adc_clk {
741 #clock-cells = <0>;
742 reg = <40>;
743 atmel,clk-output-range = <0 83000000>;
744 };
745
746 uhphs_clk: uhphs_clk {
747 #clock-cells = <0>;
748 reg = <41>;
749 atmel,clk-output-range = <0 83000000>;
750 };
751
752 udphs_clk: udphs_clk {
753 #clock-cells = <0>;
754 reg = <42>;
755 atmel,clk-output-range = <0 83000000>;
756 };
757
758 ssc0_clk: ssc0_clk {
759 #clock-cells = <0>;
760 reg = <43>;
761 atmel,clk-output-range = <0 83000000>;
762 };
763
764 ssc1_clk: ssc1_clk {
765 #clock-cells = <0>;
766 reg = <44>;
767 atmel,clk-output-range = <0 83000000>;
768 };
769
770 trng_clk: trng_clk {
771 #clock-cells = <0>;
772 reg = <47>;
773 atmel,clk-output-range = <0 83000000>;
774 };
775
776 pdmic_clk: pdmic_clk {
777 #clock-cells = <0>;
778 reg = <48>;
779 atmel,clk-output-range = <0 83000000>;
780 };
781
782 securam_clk: securam_clk {
783 #clock-cells = <0>;
784 reg = <51>;
785 };
786
787 i2s0_clk: i2s0_clk {
788 #clock-cells = <0>;
789 reg = <54>;
790 atmel,clk-output-range = <0 83000000>;
791 };
792
793 i2s1_clk: i2s1_clk {
794 #clock-cells = <0>;
795 reg = <55>;
796 atmel,clk-output-range = <0 83000000>;
797 };
798
799 can0_clk: can0_clk {
800 #clock-cells = <0>;
801 reg = <56>;
802 atmel,clk-output-range = <0 83000000>;
803 };
804
805 can1_clk: can1_clk {
806 #clock-cells = <0>;
807 reg = <57>;
808 atmel,clk-output-range = <0 83000000>;
809 };
810
811 classd_clk: classd_clk {
812 #clock-cells = <0>;
813 reg = <59>;
814 atmel,clk-output-range = <0 83000000>;
815 };
816 };
817
818 periph64ck {
819 compatible = "atmel,at91sam9x5-clk-peripheral";
820 #address-cells = <1>;
821 #size-cells = <0>;
822 clocks = <&mck>;
823
824 dma0_clk: dma0_clk {
825 #clock-cells = <0>;
826 reg = <6>;
827 };
828
829 dma1_clk: dma1_clk {
830 #clock-cells = <0>;
831 reg = <7>;
832 };
833
834 aes_clk: aes_clk {
835 #clock-cells = <0>;
836 reg = <9>;
837 };
838
839 aesb_clk: aesb_clk {
840 #clock-cells = <0>;
841 reg = <10>;
842 };
843
844 sha_clk: sha_clk {
845 #clock-cells = <0>;
846 reg = <12>;
847 };
848
849 mpddr_clk: mpddr_clk {
850 #clock-cells = <0>;
851 reg = <13>;
852 };
853
854 matrix0_clk: matrix0_clk {
855 #clock-cells = <0>;
856 reg = <15>;
857 };
858
859 sdmmc0_hclk: sdmmc0_hclk {
860 #clock-cells = <0>;
861 reg = <31>;
862 };
863
864 sdmmc1_hclk: sdmmc1_hclk {
865 #clock-cells = <0>;
866 reg = <32>;
867 };
868
869 lcdc_clk: lcdc_clk {
870 #clock-cells = <0>;
871 reg = <45>;
872 };
873
874 isc_clk: isc_clk {
875 #clock-cells = <0>;
876 reg = <46>;
877 };
878
879 qspi0_clk: qspi0_clk {
880 #clock-cells = <0>;
881 reg = <52>;
882 };
883
884 qspi1_clk: qspi1_clk {
885 #clock-cells = <0>;
886 reg = <53>;
887 };
888 };
889
890 gck {
891 compatible = "atmel,sama5d2-clk-generated";
892 #address-cells = <1>;
893 #size-cells = <0>;
894 interrupt-parent = <&pmc>;
895 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>, <&audio_pll_pmc>;
896
897 sdmmc0_gclk: sdmmc0_gclk {
898 #clock-cells = <0>;
899 reg = <31>;
900 };
901
902 sdmmc1_gclk: sdmmc1_gclk {
903 #clock-cells = <0>;
904 reg = <32>;
905 };
906
907 tcb0_gclk: tcb0_gclk {
908 #clock-cells = <0>;
909 reg = <35>;
910 atmel,clk-output-range = <0 83000000>;
911 };
912
913 tcb1_gclk: tcb1_gclk {
914 #clock-cells = <0>;
915 reg = <36>;
916 atmel,clk-output-range = <0 83000000>;
917 };
918
919 pwm_gclk: pwm_gclk {
920 #clock-cells = <0>;
921 reg = <38>;
922 atmel,clk-output-range = <0 83000000>;
923 };
924
925 isc_gclk: isc_gclk {
926 #clock-cells = <0>;
927 reg = <46>;
928 };
929
930 pdmic_gclk: pdmic_gclk {
931 #clock-cells = <0>;
932 reg = <48>;
933 };
934
935 i2s0_gclk: i2s0_gclk {
936 #clock-cells = <0>;
937 reg = <54>;
938 };
939
940 i2s1_gclk: i2s1_gclk {
941 #clock-cells = <0>;
942 reg = <55>;
943 };
944
945 can0_gclk: can0_gclk {
946 #clock-cells = <0>;
947 reg = <56>;
948 atmel,clk-output-range = <0 80000000>;
949 };
950
951 can1_gclk: can1_gclk {
952 #clock-cells = <0>;
953 reg = <57>;
954 atmel,clk-output-range = <0 80000000>;
955 };
956
957 classd_gclk: classd_gclk {
958 #clock-cells = <0>;
959 reg = <59>;
960 atmel,clk-output-range = <0 100000000>;
961 };
962 };
963
964 i2s_clkmux {
965 compatible = "atmel,sama5d2-clk-i2s-mux";
966 #address-cells = <1>;
967 #size-cells = <0>;
968
969 i2s0muxck: i2s0_muxclk {
970 clocks = <&i2s0_clk>, <&i2s0_gclk>;
971 #clock-cells = <0>;
972 reg = <0>;
973 };
974
975 i2s1muxck: i2s1_muxclk {
976 clocks = <&i2s1_clk>, <&i2s1_gclk>;
977 #clock-cells = <0>;
978 reg = <1>;
979 };
980 };
981 };
982
983 qspi0: spi@f0020000 {
984 compatible = "atmel,sama5d2-qspi";
985 reg = <0xf0020000 0x100>, <0xd0000000 0x08000000>;
986 reg-names = "qspi_base", "qspi_mmap";
987 interrupts = <52 IRQ_TYPE_LEVEL_HIGH 7>;
988 clocks = <&qspi0_clk>;
989 #address-cells = <1>;
990 #size-cells = <0>;
991 status = "disabled";
992 };
993
994 qspi1: spi@f0024000 {
995 compatible = "atmel,sama5d2-qspi";
996 reg = <0xf0024000 0x100>, <0xd8000000 0x08000000>;
997 reg-names = "qspi_base", "qspi_mmap";
998 interrupts = <53 IRQ_TYPE_LEVEL_HIGH 7>;
999 clocks = <&qspi1_clk>;
1000 #address-cells = <1>;
1001 #size-cells = <0>;
1002 status = "disabled";
1003 };
1004
1005 sha@f0028000 {
1006 compatible = "atmel,at91sam9g46-sha";
1007 reg = <0xf0028000 0x100>;
1008 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
1009 dmas = <&dma0
1010 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1011 AT91_XDMAC_DT_PERID(30))>;
1012 dma-names = "tx";
1013 clocks = <&sha_clk>;
1014 clock-names = "sha_clk";
1015 status = "okay";
1016 };
1017
1018 aes@f002c000 {
1019 compatible = "atmel,at91sam9g46-aes";
1020 reg = <0xf002c000 0x100>;
1021 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>;
1022 dmas = <&dma0
1023 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1024 AT91_XDMAC_DT_PERID(26))>,
1025 <&dma0
1026 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1027 AT91_XDMAC_DT_PERID(27))>;
1028 dma-names = "tx", "rx";
1029 clocks = <&aes_clk>;
1030 clock-names = "aes_clk";
1031 status = "okay";
1032 };
1033
1034 spi0: spi@f8000000 {
1035 compatible = "atmel,at91rm9200-spi";
1036 reg = <0xf8000000 0x100>;
1037 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>;
1038 dmas = <&dma0
1039 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1040 AT91_XDMAC_DT_PERID(6))>,
1041 <&dma0
1042 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1043 AT91_XDMAC_DT_PERID(7))>;
1044 dma-names = "tx", "rx";
1045 clocks = <&spi0_clk>;
1046 clock-names = "spi_clk";
1047 atmel,fifo-size = <16>;
1048 #address-cells = <1>;
1049 #size-cells = <0>;
1050 status = "disabled";
1051 };
1052
1053 ssc0: ssc@f8004000 {
1054 compatible = "atmel,at91sam9g45-ssc";
1055 reg = <0xf8004000 0x4000>;
1056 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 4>;
1057 dmas = <&dma0
1058 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1059 AT91_XDMAC_DT_PERID(21))>,
1060 <&dma0
1061 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1062 AT91_XDMAC_DT_PERID(22))>;
1063 dma-names = "tx", "rx";
1064 clocks = <&ssc0_clk>;
1065 clock-names = "pclk";
1066 status = "disabled";
1067 };
1068
1069 macb0: ethernet@f8008000 {
1070 compatible = "atmel,sama5d2-gem";
1071 reg = <0xf8008000 0x1000>;
1072 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 0 */
1073 66 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 1 */
1074 67 IRQ_TYPE_LEVEL_HIGH 3>; /* Queue 2 */
1075 #address-cells = <1>;
1076 #size-cells = <0>;
1077 clocks = <&macb0_clk>, <&macb0_clk>;
1078 clock-names = "hclk", "pclk";
1079 status = "disabled";
1080 };
1081
1082 tcb0: timer@f800c000 {
1083 compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
1084 #address-cells = <1>;
1085 #size-cells = <0>;
1086 reg = <0xf800c000 0x100>;
1087 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;
1088 clocks = <&tcb0_clk>, <&clk32k>;
1089 clock-names = "t0_clk", "slow_clk";
1090 };
1091
1092 tcb1: timer@f8010000 {
1093 compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
1094 #address-cells = <1>;
1095 #size-cells = <0>;
1096 reg = <0xf8010000 0x100>;
1097 interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
1098 clocks = <&tcb1_clk>, <&clk32k>;
1099 clock-names = "t0_clk", "slow_clk";
1100 };
1101
1102 hsmc: hsmc@f8014000 {
1103 compatible = "atmel,sama5d2-smc", "syscon", "simple-mfd";
1104 reg = <0xf8014000 0x1000>;
1105 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 6>;
1106 clocks = <&hsmc_clk>;
1107 #address-cells = <1>;
1108 #size-cells = <1>;
1109 ranges;
1110
1111 pmecc: ecc-engine@f8014070 {
1112 compatible = "atmel,sama5d2-pmecc";
1113 reg = <0xf8014070 0x490>,
1114 <0xf8014500 0x100>;
1115 };
1116 };
1117
1118 pdmic: pdmic@f8018000 {
1119 compatible = "atmel,sama5d2-pdmic";
1120 reg = <0xf8018000 0x124>;
1121 interrupts = <48 IRQ_TYPE_LEVEL_HIGH 7>;
1122 dmas = <&dma0
1123 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1124 | AT91_XDMAC_DT_PERID(50))>;
1125 dma-names = "rx";
1126 clocks = <&pdmic_clk>, <&pdmic_gclk>;
1127 clock-names = "pclk", "gclk";
1128 status = "disabled";
1129 };
1130
1131 uart0: serial@f801c000 {
1132 compatible = "atmel,at91sam9260-usart";
1133 reg = <0xf801c000 0x100>;
1134 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 7>;
1135 dmas = <&dma0
1136 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1137 AT91_XDMAC_DT_PERID(35))>,
1138 <&dma0
1139 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1140 AT91_XDMAC_DT_PERID(36))>;
1141 dma-names = "tx", "rx";
1142 clocks = <&uart0_clk>;
1143 clock-names = "usart";
1144 status = "disabled";
1145 };
1146
1147 uart1: serial@f8020000 {
1148 compatible = "atmel,at91sam9260-usart";
1149 reg = <0xf8020000 0x100>;
1150 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 7>;
1151 dmas = <&dma0
1152 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1153 AT91_XDMAC_DT_PERID(37))>,
1154 <&dma0
1155 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1156 AT91_XDMAC_DT_PERID(38))>;
1157 dma-names = "tx", "rx";
1158 clocks = <&uart1_clk>;
1159 clock-names = "usart";
1160 status = "disabled";
1161 };
1162
1163 uart2: serial@f8024000 {
1164 compatible = "atmel,at91sam9260-usart";
1165 reg = <0xf8024000 0x100>;
1166 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 7>;
1167 dmas = <&dma0
1168 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1169 AT91_XDMAC_DT_PERID(39))>,
1170 <&dma0
1171 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1172 AT91_XDMAC_DT_PERID(40))>;
1173 dma-names = "tx", "rx";
1174 clocks = <&uart2_clk>;
1175 clock-names = "usart";
1176 status = "disabled";
1177 };
1178
1179 i2c0: i2c@f8028000 {
1180 compatible = "atmel,sama5d2-i2c";
1181 reg = <0xf8028000 0x100>;
1182 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 7>;
1183 dmas = <&dma0
1184 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1185 AT91_XDMAC_DT_PERID(0))>,
1186 <&dma0
1187 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1188 AT91_XDMAC_DT_PERID(1))>;
1189 dma-names = "tx", "rx";
1190 #address-cells = <1>;
1191 #size-cells = <0>;
1192 clocks = <&twi0_clk>;
1193 atmel,fifo-size = <16>;
1194 status = "disabled";
1195 };
1196
1197 pwm0: pwm@f802c000 {
1198 compatible = "atmel,sama5d2-pwm";
1199 reg = <0xf802c000 0x4000>;
1200 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 7>;
1201 #pwm-cells = <3>;
1202 clocks = <&pwm_clk>;
1203 };
1204
1205 sfr: sfr@f8030000 {
1206 compatible = "atmel,sama5d2-sfr", "syscon";
1207 reg = <0xf8030000 0x98>;
1208 };
1209
1210 flx0: flexcom@f8034000 {
1211 compatible = "atmel,sama5d2-flexcom";
1212 reg = <0xf8034000 0x200>;
1213 clocks = <&flx0_clk>;
1214 #address-cells = <1>;
1215 #size-cells = <1>;
1216 ranges = <0x0 0xf8034000 0x800>;
1217 status = "disabled";
1218 };
1219
1220 flx1: flexcom@f8038000 {
1221 compatible = "atmel,sama5d2-flexcom";
1222 reg = <0xf8038000 0x200>;
1223 clocks = <&flx1_clk>;
1224 #address-cells = <1>;
1225 #size-cells = <1>;
1226 ranges = <0x0 0xf8038000 0x800>;
1227 status = "disabled";
1228 };
1229
1230 securam: sram@f8044000 {
1231 compatible = "atmel,sama5d2-securam", "mmio-sram";
1232 reg = <0xf8044000 0x1420>;
1233 clocks = <&securam_clk>;
1234 #address-cells = <1>;
1235 #size-cells = <1>;
1236 ranges = <0 0xf8044000 0x1420>;
1237 };
1238
1239 rstc@f8048000 {
1240 compatible = "atmel,sama5d3-rstc";
1241 reg = <0xf8048000 0x10>;
1242 clocks = <&clk32k>;
1243 };
1244
1245 shdwc@f8048010 {
1246 compatible = "atmel,sama5d2-shdwc";
1247 reg = <0xf8048010 0x10>;
1248 clocks = <&clk32k>;
1249 #address-cells = <1>;
1250 #size-cells = <0>;
1251 atmel,wakeup-rtc-timer;
1252 };
1253
1254 pit: timer@f8048030 {
1255 compatible = "atmel,at91sam9260-pit";
1256 reg = <0xf8048030 0x10>;
1257 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
1258 clocks = <&h32ck>;
1259 };
1260
1261 watchdog@f8048040 {
1262 compatible = "atmel,sama5d4-wdt";
1263 reg = <0xf8048040 0x10>;
1264 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>;
1265 clocks = <&clk32k>;
1266 status = "disabled";
1267 };
1268
1269 clk32k: sckc@f8048050 {
1270 compatible = "atmel,sama5d4-sckc";
1271 reg = <0xf8048050 0x4>;
1272
1273 clocks = <&slow_xtal>;
1274 #clock-cells = <0>;
1275 };
1276
1277 rtc@f80480b0 {
1278 compatible = "atmel,at91rm9200-rtc";
1279 reg = <0xf80480b0 0x30>;
1280 interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>;
1281 clocks = <&clk32k>;
1282 };
1283
1284 i2s0: i2s@f8050000 {
1285 compatible = "atmel,sama5d2-i2s";
1286 reg = <0xf8050000 0x100>;
1287 interrupts = <54 IRQ_TYPE_LEVEL_HIGH 7>;
1288 dmas = <&dma0
1289 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1290 AT91_XDMAC_DT_PERID(31))>,
1291 <&dma0
1292 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1293 AT91_XDMAC_DT_PERID(32))>;
1294 dma-names = "tx", "rx";
1295 clocks = <&i2s0_clk>, <&i2s0_gclk>;
1296 clock-names = "pclk", "gclk";
1297 assigned-clocks = <&i2s0muxck>;
1298 assigned-clock-parents = <&i2s0_gclk>;
1299 status = "disabled";
1300 };
1301
1302 can0: can@f8054000 {
1303 compatible = "bosch,m_can";
1304 reg = <0xf8054000 0x4000>, <0x210000 0x4000>;
1305 reg-names = "m_can", "message_ram";
1306 interrupts = <56 IRQ_TYPE_LEVEL_HIGH 7>,
1307 <64 IRQ_TYPE_LEVEL_HIGH 7>;
1308 interrupt-names = "int0", "int1";
1309 clocks = <&can0_clk>, <&can0_gclk>;
1310 clock-names = "hclk", "cclk";
1311 assigned-clocks = <&can0_gclk>;
1312 assigned-clock-parents = <&utmi>;
1313 assigned-clock-rates = <40000000>;
1314 bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>;
1315 status = "disabled";
1316 };
1317
1318 spi1: spi@fc000000 {
1319 compatible = "atmel,at91rm9200-spi";
1320 reg = <0xfc000000 0x100>;
1321 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>;
1322 dmas = <&dma0
1323 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1324 AT91_XDMAC_DT_PERID(8))>,
1325 <&dma0
1326 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1327 AT91_XDMAC_DT_PERID(9))>;
1328 dma-names = "tx", "rx";
1329 clocks = <&spi1_clk>;
1330 clock-names = "spi_clk";
1331 atmel,fifo-size = <16>;
1332 #address-cells = <1>;
1333 #size-cells = <0>;
1334 status = "disabled";
1335 };
1336
1337 uart3: serial@fc008000 {
1338 compatible = "atmel,at91sam9260-usart";
1339 reg = <0xfc008000 0x100>;
1340 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 7>;
1341 dmas = <&dma1
1342 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1343 AT91_XDMAC_DT_PERID(41))>,
1344 <&dma1
1345 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1346 AT91_XDMAC_DT_PERID(42))>;
1347 dma-names = "tx", "rx";
1348 clocks = <&uart3_clk>;
1349 clock-names = "usart";
1350 status = "disabled";
1351 };
1352
1353 uart4: serial@fc00c000 {
1354 compatible = "atmel,at91sam9260-usart";
1355 reg = <0xfc00c000 0x100>;
1356 dmas = <&dma0
1357 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1358 AT91_XDMAC_DT_PERID(43))>,
1359 <&dma0
1360 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1361 AT91_XDMAC_DT_PERID(44))>;
1362 dma-names = "tx", "rx";
1363 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 7>;
1364 clocks = <&uart4_clk>;
1365 clock-names = "usart";
1366 status = "disabled";
1367 };
1368
1369 flx2: flexcom@fc010000 {
1370 compatible = "atmel,sama5d2-flexcom";
1371 reg = <0xfc010000 0x200>;
1372 clocks = <&flx2_clk>;
1373 #address-cells = <1>;
1374 #size-cells = <1>;
1375 ranges = <0x0 0xfc010000 0x800>;
1376 status = "disabled";
1377 };
1378
1379 flx3: flexcom@fc014000 {
1380 compatible = "atmel,sama5d2-flexcom";
1381 reg = <0xfc014000 0x200>;
1382 clocks = <&flx3_clk>;
1383 #address-cells = <1>;
1384 #size-cells = <1>;
1385 ranges = <0x0 0xfc014000 0x800>;
1386 status = "disabled";
1387 };
1388
1389 flx4: flexcom@fc018000 {
1390 compatible = "atmel,sama5d2-flexcom";
1391 reg = <0xfc018000 0x200>;
1392 clocks = <&flx4_clk>;
1393 #address-cells = <1>;
1394 #size-cells = <1>;
1395 ranges = <0x0 0xfc018000 0x800>;
1396 status = "disabled";
1397 };
1398
1399 trng@fc01c000 {
1400 compatible = "atmel,at91sam9g45-trng";
1401 reg = <0xfc01c000 0x100>;
1402 interrupts = <47 IRQ_TYPE_LEVEL_HIGH 0>;
1403 clocks = <&trng_clk>;
1404 };
1405
1406 aic: interrupt-controller@fc020000 {
1407 #interrupt-cells = <3>;
1408 compatible = "atmel,sama5d2-aic";
1409 interrupt-controller;
1410 reg = <0xfc020000 0x200>;
1411 atmel,external-irqs = <49>;
1412 };
1413
1414 i2c1: i2c@fc028000 {
1415 compatible = "atmel,sama5d2-i2c";
1416 reg = <0xfc028000 0x100>;
1417 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 7>;
1418 dmas = <&dma0
1419 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1420 AT91_XDMAC_DT_PERID(2))>,
1421 <&dma0
1422 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1423 AT91_XDMAC_DT_PERID(3))>;
1424 dma-names = "tx", "rx";
1425 #address-cells = <1>;
1426 #size-cells = <0>;
1427 clocks = <&twi1_clk>;
1428 atmel,fifo-size = <16>;
1429 status = "disabled";
1430 };
1431
1432 adc: adc@fc030000 {
1433 compatible = "atmel,sama5d2-adc";
1434 reg = <0xfc030000 0x100>;
1435 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 7>;
1436 clocks = <&adc_clk>;
1437 clock-names = "adc_clk";
1438 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(25))>;
1439 dma-names = "rx";
1440 atmel,min-sample-rate-hz = <200000>;
1441 atmel,max-sample-rate-hz = <20000000>;
1442 atmel,startup-time-ms = <4>;
1443 atmel,trigger-edge-type = <IRQ_TYPE_EDGE_RISING>;
1444 #io-channel-cells = <1>;
1445 status = "disabled";
1446 };
1447
1448 resistive_touch: resistive-touch {
1449 compatible = "resistive-adc-touch";
1450 io-channels = <&adc AT91_SAMA5D2_ADC_X_CHANNEL>,
1451 <&adc AT91_SAMA5D2_ADC_Y_CHANNEL>,
1452 <&adc AT91_SAMA5D2_ADC_P_CHANNEL>;
1453 io-channel-names = "x", "y", "pressure";
1454 touchscreen-min-pressure = <50000>;
1455 status = "disabled";
1456 };
1457
1458 pioA: pinctrl@fc038000 {
1459 compatible = "atmel,sama5d2-pinctrl";
1460 reg = <0xfc038000 0x600>;
1461 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 7>,
1462 <68 IRQ_TYPE_LEVEL_HIGH 7>,
1463 <69 IRQ_TYPE_LEVEL_HIGH 7>,
1464 <70 IRQ_TYPE_LEVEL_HIGH 7>;
1465 interrupt-controller;
1466 #interrupt-cells = <2>;
1467 gpio-controller;
1468 #gpio-cells = <2>;
1469 clocks = <&pioA_clk>;
1470 };
1471
1472 secumod@fc040000 {
1473 compatible = "atmel,sama5d2-secumod", "syscon";
1474 reg = <0xfc040000 0x100>;
1475 };
1476
1477 tdes@fc044000 {
1478 compatible = "atmel,at91sam9g46-tdes";
1479 reg = <0xfc044000 0x100>;
1480 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
1481 dmas = <&dma0
1482 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1483 AT91_XDMAC_DT_PERID(28))>,
1484 <&dma0
1485 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1486 AT91_XDMAC_DT_PERID(29))>;
1487 dma-names = "tx", "rx";
1488 clocks = <&tdes_clk>;
1489 clock-names = "tdes_clk";
1490 status = "okay";
1491 };
1492
1493 classd: classd@fc048000 {
1494 compatible = "atmel,sama5d2-classd";
1495 reg = <0xfc048000 0x100>;
1496 interrupts = <59 IRQ_TYPE_LEVEL_HIGH 7>;
1497 dmas = <&dma0
1498 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1499 AT91_XDMAC_DT_PERID(47))>;
1500 dma-names = "tx";
1501 clocks = <&classd_clk>, <&classd_gclk>;
1502 clock-names = "pclk", "gclk";
1503 status = "disabled";
1504 };
1505
1506 i2s1: i2s@fc04c000 {
1507 compatible = "atmel,sama5d2-i2s";
1508 reg = <0xfc04c000 0x100>;
1509 interrupts = <55 IRQ_TYPE_LEVEL_HIGH 7>;
1510 dmas = <&dma0
1511 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1512 AT91_XDMAC_DT_PERID(33))>,
1513 <&dma0
1514 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1515 AT91_XDMAC_DT_PERID(34))>;
1516 dma-names = "tx", "rx";
1517 clocks = <&i2s1_clk>, <&i2s1_gclk>;
1518 clock-names = "pclk", "gclk";
1519 assigned-clocks = <&i2s1muxck>;
1520 assigned-parrents = <&i2s1_gclk>;
1521 status = "disabled";
1522 };
1523
1524 can1: can@fc050000 {
1525 compatible = "bosch,m_can";
1526 reg = <0xfc050000 0x4000>, <0x210000 0x4000>;
1527 reg-names = "m_can", "message_ram";
1528 interrupts = <57 IRQ_TYPE_LEVEL_HIGH 7>,
1529 <65 IRQ_TYPE_LEVEL_HIGH 7>;
1530 interrupt-names = "int0", "int1";
1531 clocks = <&can1_clk>, <&can1_gclk>;
1532 clock-names = "hclk", "cclk";
1533 assigned-clocks = <&can1_gclk>;
1534 assigned-clock-parents = <&utmi>;
1535 assigned-clock-rates = <40000000>;
1536 bosch,mram-cfg = <0x1100 0 0 64 0 0 32 32>;
1537 status = "disabled";
1538 };
1539
1540 sfrbu: sfr@fc05c000 {
1541 compatible = "atmel,sama5d2-sfrbu", "syscon";
1542 reg = <0xfc05c000 0x20>;
1543 };
1544
1545 chipid@fc069000 {
1546 compatible = "atmel,sama5d2-chipid";
1547 reg = <0xfc069000 0x8>;
1548 };
1549 };
1550 };
1551 };
Ubuntu Focal Linux kernel mirror