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Merge tag 'omap-for-v5.1/dt-cpsw-phy' of git://git.kernel.org/pub/scm/linux/kernel...
[mirror_ubuntu-hirsute-kernel.git] / arch / arm / boot / dts / sama5d4.dtsi
1 /*
2 * sama5d4.dtsi - Device Tree Include file for SAMA5D4 family SoC
3 *
4 * Copyright (C) 2014 Atmel,
5 * 2014 Nicolas Ferre <nicolas.ferre@atmel.com>
6 *
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
10 * whole.
11 *
12 * a) This file is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
16 *
17 * This file is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * Or, alternatively,
23 *
24 * b) Permission is hereby granted, free of charge, to any person
25 * obtaining a copy of this software and associated documentation
26 * files (the "Software"), to deal in the Software without
27 * restriction, including without limitation the rights to use,
28 * copy, modify, merge, publish, distribute, sublicense, and/or
29 * sell copies of the Software, and to permit persons to whom the
30 * Software is furnished to do so, subject to the following
31 * conditions:
32 *
33 * The above copyright notice and this permission notice shall be
34 * included in all copies or substantial portions of the Software.
35 *
36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 * OTHER DEALINGS IN THE SOFTWARE.
44 */
45
46 #include <dt-bindings/clock/at91.h>
47 #include <dt-bindings/dma/at91.h>
48 #include <dt-bindings/pinctrl/at91.h>
49 #include <dt-bindings/interrupt-controller/irq.h>
50 #include <dt-bindings/gpio/gpio.h>
51
52 / {
53 #address-cells = <1>;
54 #size-cells = <1>;
55 model = "Atmel SAMA5D4 family SoC";
56 compatible = "atmel,sama5d4";
57 interrupt-parent = <&aic>;
58
59 aliases {
60 serial0 = &usart3;
61 serial1 = &usart4;
62 serial2 = &usart2;
63 serial3 = &usart0;
64 serial4 = &usart1;
65 serial5 = &uart0;
66 serial6 = &uart1;
67 gpio0 = &pioA;
68 gpio1 = &pioB;
69 gpio2 = &pioC;
70 gpio3 = &pioD;
71 gpio4 = &pioE;
72 pwm0 = &pwm0;
73 ssc0 = &ssc0;
74 ssc1 = &ssc1;
75 tcb0 = &tcb0;
76 tcb1 = &tcb1;
77 i2c0 = &i2c0;
78 i2c1 = &i2c1;
79 i2c2 = &i2c2;
80 };
81 cpus {
82 #address-cells = <1>;
83 #size-cells = <0>;
84
85 cpu@0 {
86 device_type = "cpu";
87 compatible = "arm,cortex-a5";
88 reg = <0>;
89 next-level-cache = <&L2>;
90 };
91 };
92
93 memory {
94 device_type = "memory";
95 reg = <0x20000000 0x20000000>;
96 };
97
98 clocks {
99 slow_xtal: slow_xtal {
100 compatible = "fixed-clock";
101 #clock-cells = <0>;
102 clock-frequency = <0>;
103 };
104
105 main_xtal: main_xtal {
106 compatible = "fixed-clock";
107 #clock-cells = <0>;
108 clock-frequency = <0>;
109 };
110
111 adc_op_clk: adc_op_clk{
112 compatible = "fixed-clock";
113 #clock-cells = <0>;
114 clock-frequency = <1000000>;
115 };
116 };
117
118 ns_sram: sram@210000 {
119 compatible = "mmio-sram";
120 reg = <0x00210000 0x10000>;
121 };
122
123 ahb {
124 compatible = "simple-bus";
125 #address-cells = <1>;
126 #size-cells = <1>;
127 ranges;
128
129 nfc_sram: sram@100000 {
130 compatible = "mmio-sram";
131 no-memory-wc;
132 reg = <0x100000 0x2400>;
133 };
134
135 usb0: gadget@400000 {
136 #address-cells = <1>;
137 #size-cells = <0>;
138 compatible = "atmel,sama5d3-udc";
139 reg = <0x00400000 0x100000
140 0xfc02c000 0x4000>;
141 interrupts = <47 IRQ_TYPE_LEVEL_HIGH 2>;
142 clocks = <&pmc PMC_TYPE_PERIPHERAL 47>, <&pmc PMC_TYPE_CORE PMC_UTMI>;
143 clock-names = "pclk", "hclk";
144 status = "disabled";
145
146 ep@0 {
147 reg = <0>;
148 atmel,fifo-size = <64>;
149 atmel,nb-banks = <1>;
150 };
151
152 ep@1 {
153 reg = <1>;
154 atmel,fifo-size = <1024>;
155 atmel,nb-banks = <3>;
156 atmel,can-dma;
157 atmel,can-isoc;
158 };
159
160 ep@2 {
161 reg = <2>;
162 atmel,fifo-size = <1024>;
163 atmel,nb-banks = <3>;
164 atmel,can-dma;
165 atmel,can-isoc;
166 };
167
168 ep@3 {
169 reg = <3>;
170 atmel,fifo-size = <1024>;
171 atmel,nb-banks = <2>;
172 atmel,can-dma;
173 atmel,can-isoc;
174 };
175
176 ep@4 {
177 reg = <4>;
178 atmel,fifo-size = <1024>;
179 atmel,nb-banks = <2>;
180 atmel,can-dma;
181 atmel,can-isoc;
182 };
183
184 ep@5 {
185 reg = <5>;
186 atmel,fifo-size = <1024>;
187 atmel,nb-banks = <2>;
188 atmel,can-dma;
189 atmel,can-isoc;
190 };
191
192 ep@6 {
193 reg = <6>;
194 atmel,fifo-size = <1024>;
195 atmel,nb-banks = <2>;
196 atmel,can-dma;
197 atmel,can-isoc;
198 };
199
200 ep@7 {
201 reg = <7>;
202 atmel,fifo-size = <1024>;
203 atmel,nb-banks = <2>;
204 atmel,can-dma;
205 atmel,can-isoc;
206 };
207
208 ep@8 {
209 reg = <8>;
210 atmel,fifo-size = <1024>;
211 atmel,nb-banks = <2>;
212 atmel,can-isoc;
213 };
214
215 ep@9 {
216 reg = <9>;
217 atmel,fifo-size = <1024>;
218 atmel,nb-banks = <2>;
219 atmel,can-isoc;
220 };
221
222 ep@10 {
223 reg = <10>;
224 atmel,fifo-size = <1024>;
225 atmel,nb-banks = <2>;
226 atmel,can-isoc;
227 };
228
229 ep@11 {
230 reg = <11>;
231 atmel,fifo-size = <1024>;
232 atmel,nb-banks = <2>;
233 atmel,can-isoc;
234 };
235
236 ep@12 {
237 reg = <12>;
238 atmel,fifo-size = <1024>;
239 atmel,nb-banks = <2>;
240 atmel,can-isoc;
241 };
242
243 ep@13 {
244 reg = <13>;
245 atmel,fifo-size = <1024>;
246 atmel,nb-banks = <2>;
247 atmel,can-isoc;
248 };
249
250 ep@14 {
251 reg = <14>;
252 atmel,fifo-size = <1024>;
253 atmel,nb-banks = <2>;
254 atmel,can-isoc;
255 };
256
257 ep@15 {
258 reg = <15>;
259 atmel,fifo-size = <1024>;
260 atmel,nb-banks = <2>;
261 atmel,can-isoc;
262 };
263 };
264
265 usb1: ohci@500000 {
266 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
267 reg = <0x00500000 0x100000>;
268 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>;
269 clocks = <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_SYSTEM 6>;
270 clock-names = "ohci_clk", "hclk", "uhpck";
271 status = "disabled";
272 };
273
274 usb2: ehci@600000 {
275 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
276 reg = <0x00600000 0x100000>;
277 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>;
278 clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 46>;
279 clock-names = "usb_clk", "ehci_clk";
280 status = "disabled";
281 };
282
283 L2: cache-controller@a00000 {
284 compatible = "arm,pl310-cache";
285 reg = <0x00a00000 0x1000>;
286 interrupts = <67 IRQ_TYPE_LEVEL_HIGH 4>;
287 cache-unified;
288 cache-level = <2>;
289 };
290
291 ebi: ebi@10000000 {
292 compatible = "atmel,sama5d3-ebi";
293 #address-cells = <2>;
294 #size-cells = <1>;
295 atmel,smc = <&hsmc>;
296 reg = <0x10000000 0x10000000
297 0x60000000 0x28000000>;
298 ranges = <0x0 0x0 0x10000000 0x10000000
299 0x1 0x0 0x60000000 0x10000000
300 0x2 0x0 0x70000000 0x10000000
301 0x3 0x0 0x80000000 0x8000000>;
302 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
303 status = "disabled";
304
305 nand_controller: nand-controller {
306 compatible = "atmel,sama5d3-nand-controller";
307 atmel,nfc-sram = <&nfc_sram>;
308 atmel,nfc-io = <&nfc_io>;
309 ecc-engine = <&pmecc>;
310 #address-cells = <2>;
311 #size-cells = <1>;
312 ranges;
313 status = "disabled";
314 };
315 };
316
317 nfc_io: nfc-io@90000000 {
318 compatible = "atmel,sama5d3-nfc-io", "syscon";
319 reg = <0x90000000 0x8000000>;
320 };
321
322 apb {
323 compatible = "simple-bus";
324 #address-cells = <1>;
325 #size-cells = <1>;
326 ranges;
327
328 hlcdc: hlcdc@f0000000 {
329 compatible = "atmel,sama5d4-hlcdc";
330 reg = <0xf0000000 0x4000>;
331 interrupts = <51 IRQ_TYPE_LEVEL_HIGH 0>;
332 clocks = <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>;
333 clock-names = "periph_clk","sys_clk", "slow_clk";
334 status = "disabled";
335
336 hlcdc-display-controller {
337 compatible = "atmel,hlcdc-display-controller";
338 #address-cells = <1>;
339 #size-cells = <0>;
340
341 port@0 {
342 #address-cells = <1>;
343 #size-cells = <0>;
344 reg = <0>;
345 };
346 };
347
348 hlcdc_pwm: hlcdc-pwm {
349 compatible = "atmel,hlcdc-pwm";
350 pinctrl-names = "default";
351 pinctrl-0 = <&pinctrl_lcd_pwm>;
352 #pwm-cells = <3>;
353 };
354 };
355
356 dma1: dma-controller@f0004000 {
357 compatible = "atmel,sama5d4-dma";
358 reg = <0xf0004000 0x200>;
359 interrupts = <50 IRQ_TYPE_LEVEL_HIGH 0>;
360 #dma-cells = <1>;
361 clocks = <&pmc PMC_TYPE_PERIPHERAL 50>;
362 clock-names = "dma_clk";
363 };
364
365 isi: isi@f0008000 {
366 compatible = "atmel,at91sam9g45-isi";
367 reg = <0xf0008000 0x4000>;
368 interrupts = <52 IRQ_TYPE_LEVEL_HIGH 5>;
369 pinctrl-names = "default";
370 pinctrl-0 = <&pinctrl_isi_data_0_7>;
371 clocks = <&pmc PMC_TYPE_PERIPHERAL 52>;
372 clock-names = "isi_clk";
373 status = "disabled";
374 port {
375 #address-cells = <1>;
376 #size-cells = <0>;
377 };
378 };
379
380 ramc0: ramc@f0010000 {
381 compatible = "atmel,sama5d3-ddramc";
382 reg = <0xf0010000 0x200>;
383 clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_PERIPHERAL 16>;
384 clock-names = "ddrck", "mpddr";
385 };
386
387 dma0: dma-controller@f0014000 {
388 compatible = "atmel,sama5d4-dma";
389 reg = <0xf0014000 0x200>;
390 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 0>;
391 #dma-cells = <1>;
392 clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
393 clock-names = "dma_clk";
394 };
395
396 pmc: pmc@f0018000 {
397 compatible = "atmel,sama5d4-pmc", "syscon";
398 reg = <0xf0018000 0x120>;
399 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
400 #clock-cells = <2>;
401 clocks = <&clk32k>, <&main_xtal>;
402 clock-names = "slow_clk", "main_xtal";
403 };
404
405 mmc0: mmc@f8000000 {
406 compatible = "atmel,hsmci";
407 reg = <0xf8000000 0x600>;
408 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;
409 dmas = <&dma1
410 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
411 | AT91_XDMAC_DT_PERID(0))>;
412 dma-names = "rxtx";
413 pinctrl-names = "default";
414 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3>;
415 status = "disabled";
416 #address-cells = <1>;
417 #size-cells = <0>;
418 clocks = <&pmc PMC_TYPE_PERIPHERAL 35>;
419 clock-names = "mci_clk";
420 };
421
422 uart0: serial@f8004000 {
423 compatible = "atmel,at91sam9260-usart";
424 reg = <0xf8004000 0x100>;
425 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 5>;
426 dmas = <&dma0
427 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
428 | AT91_XDMAC_DT_PERID(22))>,
429 <&dma0
430 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
431 | AT91_XDMAC_DT_PERID(23))>;
432 dma-names = "tx", "rx";
433 pinctrl-names = "default";
434 pinctrl-0 = <&pinctrl_uart0>;
435 clocks = <&pmc PMC_TYPE_PERIPHERAL 27>;
436 clock-names = "usart";
437 status = "disabled";
438 };
439
440 ssc0: ssc@f8008000 {
441 compatible = "atmel,at91sam9g45-ssc";
442 reg = <0xf8008000 0x4000>;
443 interrupts = <48 IRQ_TYPE_LEVEL_HIGH 0>;
444 pinctrl-names = "default";
445 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
446 dmas = <&dma1
447 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
448 | AT91_XDMAC_DT_PERID(26))>,
449 <&dma1
450 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
451 | AT91_XDMAC_DT_PERID(27))>;
452 dma-names = "tx", "rx";
453 clocks = <&pmc PMC_TYPE_PERIPHERAL 48>;
454 clock-names = "pclk";
455 status = "disabled";
456 };
457
458 pwm0: pwm@f800c000 {
459 compatible = "atmel,sama5d3-pwm";
460 reg = <0xf800c000 0x300>;
461 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 4>;
462 #pwm-cells = <3>;
463 clocks = <&pmc PMC_TYPE_PERIPHERAL 43>;
464 status = "disabled";
465 };
466
467 spi0: spi@f8010000 {
468 #address-cells = <1>;
469 #size-cells = <0>;
470 compatible = "atmel,at91rm9200-spi";
471 reg = <0xf8010000 0x100>;
472 interrupts = <37 IRQ_TYPE_LEVEL_HIGH 3>;
473 dmas = <&dma1
474 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
475 | AT91_XDMAC_DT_PERID(10))>,
476 <&dma1
477 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
478 | AT91_XDMAC_DT_PERID(11))>;
479 dma-names = "tx", "rx";
480 pinctrl-names = "default";
481 pinctrl-0 = <&pinctrl_spi0>;
482 clocks = <&pmc PMC_TYPE_PERIPHERAL 37>;
483 clock-names = "spi_clk";
484 status = "disabled";
485 };
486
487 i2c0: i2c@f8014000 {
488 compatible = "atmel,sama5d4-i2c";
489 reg = <0xf8014000 0x4000>;
490 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 6>;
491 dmas = <&dma1
492 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
493 | AT91_XDMAC_DT_PERID(2))>,
494 <&dma1
495 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
496 | AT91_XDMAC_DT_PERID(3))>;
497 dma-names = "tx", "rx";
498 pinctrl-names = "default";
499 pinctrl-0 = <&pinctrl_i2c0>;
500 #address-cells = <1>;
501 #size-cells = <0>;
502 clocks = <&pmc PMC_TYPE_PERIPHERAL 32>;
503 status = "disabled";
504 };
505
506 i2c1: i2c@f8018000 {
507 compatible = "atmel,sama5d4-i2c";
508 reg = <0xf8018000 0x4000>;
509 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 6>;
510 dmas = <&dma0
511 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
512 | AT91_XDMAC_DT_PERID(4))>,
513 <&dma0
514 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
515 | AT91_XDMAC_DT_PERID(5))>;
516 dma-names = "tx", "rx";
517 pinctrl-names = "default";
518 pinctrl-0 = <&pinctrl_i2c1>;
519 #address-cells = <1>;
520 #size-cells = <0>;
521 clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
522 status = "disabled";
523 };
524
525 tcb0: timer@f801c000 {
526 compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
527 #address-cells = <1>;
528 #size-cells = <0>;
529 reg = <0xf801c000 0x100>;
530 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>;
531 clocks = <&pmc PMC_TYPE_PERIPHERAL 40>, <&clk32k>;
532 clock-names = "t0_clk", "slow_clk";
533 };
534
535 macb0: ethernet@f8020000 {
536 compatible = "atmel,sama5d4-gem";
537 reg = <0xf8020000 0x100>;
538 interrupts = <54 IRQ_TYPE_LEVEL_HIGH 3>;
539 pinctrl-names = "default";
540 pinctrl-0 = <&pinctrl_macb0_rmii>;
541 #address-cells = <1>;
542 #size-cells = <0>;
543 clocks = <&pmc PMC_TYPE_PERIPHERAL 54>, <&pmc PMC_TYPE_PERIPHERAL 54>;
544 clock-names = "hclk", "pclk";
545 status = "disabled";
546 };
547
548 i2c2: i2c@f8024000 {
549 compatible = "atmel,sama5d4-i2c";
550 reg = <0xf8024000 0x4000>;
551 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 6>;
552 dmas = <&dma1
553 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
554 | AT91_XDMAC_DT_PERID(6))>,
555 <&dma1
556 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
557 | AT91_XDMAC_DT_PERID(7))>;
558 dma-names = "tx", "rx";
559 pinctrl-names = "default";
560 pinctrl-0 = <&pinctrl_i2c2>;
561 #address-cells = <1>;
562 #size-cells = <0>;
563 clocks = <&pmc PMC_TYPE_PERIPHERAL 34>;
564 status = "disabled";
565 };
566
567 sfr: sfr@f8028000 {
568 compatible = "atmel,sama5d4-sfr", "syscon";
569 reg = <0xf8028000 0x60>;
570 };
571
572 usart0: serial@f802c000 {
573 compatible = "atmel,at91sam9260-usart";
574 reg = <0xf802c000 0x100>;
575 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
576 dmas = <&dma0
577 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
578 | AT91_XDMAC_DT_PERID(36))>,
579 <&dma0
580 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
581 | AT91_XDMAC_DT_PERID(37))>;
582 dma-names = "tx", "rx";
583 pinctrl-names = "default";
584 pinctrl-0 = <&pinctrl_usart0 &pinctrl_usart0_rts &pinctrl_usart0_cts>;
585 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
586 clock-names = "usart";
587 status = "disabled";
588 };
589
590 usart1: serial@f8030000 {
591 compatible = "atmel,at91sam9260-usart";
592 reg = <0xf8030000 0x100>;
593 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
594 dmas = <&dma0
595 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
596 | AT91_XDMAC_DT_PERID(38))>,
597 <&dma0
598 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
599 | AT91_XDMAC_DT_PERID(39))>;
600 dma-names = "tx", "rx";
601 pinctrl-names = "default";
602 pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts &pinctrl_usart1_cts>;
603 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
604 clock-names = "usart";
605 status = "disabled";
606 };
607
608 mmc1: mmc@fc000000 {
609 compatible = "atmel,hsmci";
610 reg = <0xfc000000 0x600>;
611 interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
612 dmas = <&dma1
613 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
614 | AT91_XDMAC_DT_PERID(1))>;
615 dma-names = "rxtx";
616 pinctrl-names = "default";
617 pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
618 status = "disabled";
619 #address-cells = <1>;
620 #size-cells = <0>;
621 clocks = <&pmc PMC_TYPE_PERIPHERAL 36>;
622 clock-names = "mci_clk";
623 };
624
625 uart1: serial@fc004000 {
626 compatible = "atmel,at91sam9260-usart";
627 reg = <0xfc004000 0x100>;
628 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
629 dmas = <&dma0
630 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
631 | AT91_XDMAC_DT_PERID(24))>,
632 <&dma0
633 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
634 | AT91_XDMAC_DT_PERID(25))>;
635 dma-names = "tx", "rx";
636 pinctrl-names = "default";
637 pinctrl-0 = <&pinctrl_uart1>;
638 clocks = <&pmc PMC_TYPE_PERIPHERAL 28>;
639 clock-names = "usart";
640 status = "disabled";
641 };
642
643 usart2: serial@fc008000 {
644 compatible = "atmel,at91sam9260-usart";
645 reg = <0xfc008000 0x100>;
646 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>;
647 dmas = <&dma1
648 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
649 | AT91_XDMAC_DT_PERID(16))>,
650 <&dma1
651 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
652 | AT91_XDMAC_DT_PERID(17))>;
653 dma-names = "tx", "rx";
654 pinctrl-names = "default";
655 pinctrl-0 = <&pinctrl_usart2 &pinctrl_usart2_rts &pinctrl_usart2_cts>;
656 clocks = <&pmc PMC_TYPE_PERIPHERAL 29>;
657 clock-names = "usart";
658 status = "disabled";
659 };
660
661 usart3: serial@fc00c000 {
662 compatible = "atmel,at91sam9260-usart";
663 reg = <0xfc00c000 0x100>;
664 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 5>;
665 dmas = <&dma1
666 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
667 | AT91_XDMAC_DT_PERID(18))>,
668 <&dma1
669 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
670 | AT91_XDMAC_DT_PERID(19))>;
671 dma-names = "tx", "rx";
672 pinctrl-names = "default";
673 pinctrl-0 = <&pinctrl_usart3>;
674 clocks = <&pmc PMC_TYPE_PERIPHERAL 30>;
675 clock-names = "usart";
676 status = "disabled";
677 };
678
679 usart4: serial@fc010000 {
680 compatible = "atmel,at91sam9260-usart";
681 reg = <0xfc010000 0x100>;
682 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 5>;
683 dmas = <&dma1
684 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
685 | AT91_XDMAC_DT_PERID(20))>,
686 <&dma1
687 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
688 | AT91_XDMAC_DT_PERID(21))>;
689 dma-names = "tx", "rx";
690 pinctrl-names = "default";
691 pinctrl-0 = <&pinctrl_usart4>;
692 clocks = <&pmc PMC_TYPE_PERIPHERAL 31>;
693 clock-names = "usart";
694 status = "disabled";
695 };
696
697 ssc1: ssc@fc014000 {
698 compatible = "atmel,at91sam9g45-ssc";
699 reg = <0xfc014000 0x4000>;
700 interrupts = <49 IRQ_TYPE_LEVEL_HIGH 0>;
701 pinctrl-names = "default";
702 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
703 dmas = <&dma1
704 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
705 | AT91_XDMAC_DT_PERID(28))>,
706 <&dma1
707 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
708 | AT91_XDMAC_DT_PERID(29))>;
709 dma-names = "tx", "rx";
710 clocks = <&pmc PMC_TYPE_PERIPHERAL 49>;
711 clock-names = "pclk";
712 status = "disabled";
713 };
714
715 spi1: spi@fc018000 {
716 #address-cells = <1>;
717 #size-cells = <0>;
718 compatible = "atmel,at91rm9200-spi";
719 reg = <0xfc018000 0x100>;
720 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 3>;
721 dmas = <&dma1
722 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
723 | AT91_XDMAC_DT_PERID(12))>,
724 <&dma1
725 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
726 | AT91_XDMAC_DT_PERID(13))>;
727 dma-names = "tx", "rx";
728 pinctrl-names = "default";
729 pinctrl-0 = <&pinctrl_spi1>;
730 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
731 clock-names = "spi_clk";
732 status = "disabled";
733 };
734
735 spi2: spi@fc01c000 {
736 #address-cells = <1>;
737 #size-cells = <0>;
738 compatible = "atmel,at91rm9200-spi";
739 reg = <0xfc01c000 0x100>;
740 interrupts = <39 IRQ_TYPE_LEVEL_HIGH 3>;
741 dmas = <&dma0
742 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
743 | AT91_XDMAC_DT_PERID(14))>,
744 <&dma0
745 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
746 | AT91_XDMAC_DT_PERID(15))>;
747 dma-names = "tx", "rx";
748 pinctrl-names = "default";
749 pinctrl-0 = <&pinctrl_spi2>;
750 clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
751 clock-names = "spi_clk";
752 status = "disabled";
753 };
754
755 tcb1: timer@fc020000 {
756 compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
757 #address-cells = <1>;
758 #size-cells = <0>;
759 reg = <0xfc020000 0x100>;
760 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
761 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>, <&clk32k>;
762 clock-names = "t0_clk", "slow_clk";
763 };
764
765 tcb2: timer@fc024000 {
766 compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
767 #address-cells = <1>;
768 #size-cells = <0>;
769 reg = <0xfc024000 0x100>;
770 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>;
771 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&clk32k>;
772 clock-names = "t0_clk", "slow_clk";
773 };
774
775 macb1: ethernet@fc028000 {
776 compatible = "atmel,sama5d4-gem";
777 reg = <0xfc028000 0x100>;
778 interrupts = <55 IRQ_TYPE_LEVEL_HIGH 3>;
779 pinctrl-names = "default";
780 pinctrl-0 = <&pinctrl_macb1_rmii>;
781 #address-cells = <1>;
782 #size-cells = <0>;
783 clocks = <&pmc PMC_TYPE_PERIPHERAL 55>, <&pmc PMC_TYPE_PERIPHERAL 55>;
784 clock-names = "hclk", "pclk";
785 status = "disabled";
786 };
787
788 trng@fc030000 {
789 compatible = "atmel,at91sam9g45-trng";
790 reg = <0xfc030000 0x100>;
791 interrupts = <53 IRQ_TYPE_LEVEL_HIGH 0>;
792 clocks = <&pmc PMC_TYPE_PERIPHERAL 53>;
793 };
794
795 adc0: adc@fc034000 {
796 compatible = "atmel,at91sam9x5-adc";
797 reg = <0xfc034000 0x100>;
798 interrupts = <44 IRQ_TYPE_LEVEL_HIGH 5>;
799 clocks = <&pmc PMC_TYPE_PERIPHERAL 44>,
800 <&adc_op_clk>;
801 clock-names = "adc_clk", "adc_op_clk";
802 atmel,adc-channels-used = <0x01f>;
803 atmel,adc-startup-time = <40>;
804 atmel,adc-use-external-triggers;
805 atmel,adc-vref = <3000>;
806 atmel,adc-res = <8 10>;
807 atmel,adc-sample-hold-time = <11>;
808 atmel,adc-res-names = "lowres", "highres";
809 atmel,adc-ts-pressure-threshold = <10000>;
810 status = "disabled";
811
812 trigger0 {
813 trigger-name = "external-rising";
814 trigger-value = <0x1>;
815 trigger-external;
816 };
817 trigger1 {
818 trigger-name = "external-falling";
819 trigger-value = <0x2>;
820 trigger-external;
821 };
822 trigger2 {
823 trigger-name = "external-any";
824 trigger-value = <0x3>;
825 trigger-external;
826 };
827 trigger3 {
828 trigger-name = "continuous";
829 trigger-value = <0x6>;
830 };
831 };
832
833 aes@fc044000 {
834 compatible = "atmel,at91sam9g46-aes";
835 reg = <0xfc044000 0x100>;
836 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
837 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
838 | AT91_XDMAC_DT_PERID(41))>,
839 <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
840 | AT91_XDMAC_DT_PERID(40))>;
841 dma-names = "tx", "rx";
842 clocks = <&pmc PMC_TYPE_PERIPHERAL 12>;
843 clock-names = "aes_clk";
844 status = "okay";
845 };
846
847 tdes@fc04c000 {
848 compatible = "atmel,at91sam9g46-tdes";
849 reg = <0xfc04c000 0x100>;
850 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 0>;
851 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
852 | AT91_XDMAC_DT_PERID(42))>,
853 <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
854 | AT91_XDMAC_DT_PERID(43))>;
855 dma-names = "tx", "rx";
856 clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
857 clock-names = "tdes_clk";
858 status = "okay";
859 };
860
861 sha@fc050000 {
862 compatible = "atmel,at91sam9g46-sha";
863 reg = <0xfc050000 0x100>;
864 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 0>;
865 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
866 | AT91_XDMAC_DT_PERID(44))>;
867 dma-names = "tx";
868 clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
869 clock-names = "sha_clk";
870 status = "okay";
871 };
872
873 hsmc: smc@fc05c000 {
874 compatible = "atmel,sama5d3-smc", "syscon", "simple-mfd";
875 reg = <0xfc05c000 0x1000>;
876 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 6>;
877 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>;
878 #address-cells = <1>;
879 #size-cells = <1>;
880 ranges;
881
882 pmecc: ecc-engine@ffffc070 {
883 compatible = "atmel,sama5d4-pmecc";
884 reg = <0xfc05c070 0x490>,
885 <0xfc05c500 0x100>;
886 };
887 };
888
889 reset_controller: rstc@fc068600 {
890 compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc";
891 reg = <0xfc068600 0x10>;
892 clocks = <&clk32k>;
893 };
894
895 shutdown_controller: shdwc@fc068610 {
896 compatible = "atmel,at91sam9x5-shdwc";
897 reg = <0xfc068610 0x10>;
898 clocks = <&clk32k>;
899 };
900
901 pit: timer@fc068630 {
902 compatible = "atmel,at91sam9260-pit";
903 reg = <0xfc068630 0x10>;
904 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
905 clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>;
906 };
907
908 watchdog: watchdog@fc068640 {
909 compatible = "atmel,sama5d4-wdt";
910 reg = <0xfc068640 0x10>;
911 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>;
912 clocks = <&clk32k>;
913 status = "disabled";
914 };
915
916 clk32k: sckc@fc068650 {
917 compatible = "atmel,sama5d4-sckc";
918 reg = <0xfc068650 0x4>;
919 #clock-cells = <0>;
920 clocks = <&slow_xtal>;
921 };
922
923 rtc@fc0686b0 {
924 compatible = "atmel,at91rm9200-rtc";
925 reg = <0xfc0686b0 0x30>;
926 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
927 clocks = <&clk32k>;
928 };
929
930 dbgu: serial@fc069000 {
931 compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
932 reg = <0xfc069000 0x200>;
933 interrupts = <45 IRQ_TYPE_LEVEL_HIGH 7>;
934 pinctrl-names = "default";
935 pinctrl-0 = <&pinctrl_dbgu>;
936 clocks = <&pmc PMC_TYPE_PERIPHERAL 45>;
937 clock-names = "usart";
938 status = "disabled";
939 };
940
941
942 pinctrl: pinctrl@fc06a000 {
943 #address-cells = <1>;
944 #size-cells = <1>;
945 compatible = "atmel,sama5d3-pinctrl", "atmel,at91sam9x5-pinctrl", "simple-bus";
946 ranges = <0xfc068000 0xfc068000 0x100
947 0xfc06a000 0xfc06a000 0x4000>;
948 /* WARNING: revisit as pin spec has changed */
949 atmel,mux-mask = <
950 /* A B C */
951 0xffffffff 0x3ffcfe7c 0x1c010101 /* pioA */
952 0x7fffffff 0xfffccc3a 0x3f00cc3a /* pioB */
953 0xffffffff 0x3ff83fff 0xff00ffff /* pioC */
954 0x0003ff00 0x8002a800 0x00000000 /* pioD */
955 0xffffffff 0x7fffffff 0x76fff1bf /* pioE */
956 >;
957
958 pioA: gpio@fc06a000 {
959 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
960 reg = <0xfc06a000 0x100>;
961 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 1>;
962 #gpio-cells = <2>;
963 gpio-controller;
964 interrupt-controller;
965 #interrupt-cells = <2>;
966 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
967 };
968
969 pioB: gpio@fc06b000 {
970 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
971 reg = <0xfc06b000 0x100>;
972 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 1>;
973 #gpio-cells = <2>;
974 gpio-controller;
975 interrupt-controller;
976 #interrupt-cells = <2>;
977 clocks = <&pmc PMC_TYPE_PERIPHERAL 24>;
978 };
979
980 pioC: gpio@fc06c000 {
981 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
982 reg = <0xfc06c000 0x100>;
983 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 1>;
984 #gpio-cells = <2>;
985 gpio-controller;
986 interrupt-controller;
987 #interrupt-cells = <2>;
988 clocks = <&pmc PMC_TYPE_PERIPHERAL 25>;
989 };
990
991 pioD: gpio@fc068000 {
992 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
993 reg = <0xfc068000 0x100>;
994 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
995 #gpio-cells = <2>;
996 gpio-controller;
997 interrupt-controller;
998 #interrupt-cells = <2>;
999 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
1000 };
1001
1002 pioE: gpio@fc06d000 {
1003 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1004 reg = <0xfc06d000 0x100>;
1005 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 1>;
1006 #gpio-cells = <2>;
1007 gpio-controller;
1008 interrupt-controller;
1009 #interrupt-cells = <2>;
1010 clocks = <&pmc PMC_TYPE_PERIPHERAL 26>;
1011 };
1012
1013 /* pinctrl pin settings */
1014 adc0 {
1015 pinctrl_adc0_adtrg: adc0_adtrg {
1016 atmel,pins =
1017 <AT91_PIOE 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* conflicts with USBA_VBUS */
1018 };
1019 pinctrl_adc0_ad0: adc0_ad0 {
1020 atmel,pins =
1021 <AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1022 };
1023 pinctrl_adc0_ad1: adc0_ad1 {
1024 atmel,pins =
1025 <AT91_PIOC 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1026 };
1027 pinctrl_adc0_ad2: adc0_ad2 {
1028 atmel,pins =
1029 <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1030 };
1031 pinctrl_adc0_ad3: adc0_ad3 {
1032 atmel,pins =
1033 <AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1034 };
1035 pinctrl_adc0_ad4: adc0_ad4 {
1036 atmel,pins =
1037 <AT91_PIOC 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1038 };
1039 };
1040
1041 dbgu {
1042 pinctrl_dbgu: dbgu-0 {
1043 atmel,pins =
1044 <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* conflicts with D14 and TDI */
1045 AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* conflicts with D15 and TDO */
1046 };
1047 };
1048
1049 ebi {
1050 pinctrl_ebi_addr: ebi-addr-0 {
1051 atmel,pins =
1052 <AT91_PIOE 0 AT91_PERIPH_A AT91_PINCTRL_NONE
1053 AT91_PIOE 1 AT91_PERIPH_A AT91_PINCTRL_NONE
1054 AT91_PIOE 2 AT91_PERIPH_A AT91_PINCTRL_NONE
1055 AT91_PIOE 3 AT91_PERIPH_A AT91_PINCTRL_NONE
1056 AT91_PIOE 4 AT91_PERIPH_A AT91_PINCTRL_NONE
1057 AT91_PIOE 5 AT91_PERIPH_A AT91_PINCTRL_NONE
1058 AT91_PIOE 6 AT91_PERIPH_A AT91_PINCTRL_NONE
1059 AT91_PIOE 7 AT91_PERIPH_A AT91_PINCTRL_NONE
1060 AT91_PIOE 8 AT91_PERIPH_A AT91_PINCTRL_NONE
1061 AT91_PIOE 9 AT91_PERIPH_A AT91_PINCTRL_NONE
1062 AT91_PIOE 10 AT91_PERIPH_A AT91_PINCTRL_NONE
1063 AT91_PIOE 11 AT91_PERIPH_A AT91_PINCTRL_NONE
1064 AT91_PIOE 12 AT91_PERIPH_A AT91_PINCTRL_NONE
1065 AT91_PIOE 13 AT91_PERIPH_A AT91_PINCTRL_NONE
1066 AT91_PIOE 14 AT91_PERIPH_A AT91_PINCTRL_NONE
1067 AT91_PIOE 15 AT91_PERIPH_A AT91_PINCTRL_NONE
1068 AT91_PIOE 16 AT91_PERIPH_A AT91_PINCTRL_NONE
1069 AT91_PIOE 17 AT91_PERIPH_A AT91_PINCTRL_NONE
1070 AT91_PIOE 18 AT91_PERIPH_A AT91_PINCTRL_NONE
1071 AT91_PIOE 19 AT91_PERIPH_A AT91_PINCTRL_NONE
1072 AT91_PIOE 20 AT91_PERIPH_A AT91_PINCTRL_NONE
1073 AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE
1074 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE
1075 AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_NONE
1076 AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_NONE
1077 AT91_PIOE 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1078 };
1079
1080 pinctrl_ebi_nand_addr: ebi-addr-1 {
1081 atmel,pins =
1082 <AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE
1083 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1084 };
1085
1086 pinctrl_ebi_cs0: ebi-cs0-0 {
1087 atmel,pins =
1088 <AT91_PIOE 26 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1089 };
1090
1091 pinctrl_ebi_cs1: ebi-cs1-0 {
1092 atmel,pins =
1093 <AT91_PIOE 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1094 };
1095
1096 pinctrl_ebi_cs2: ebi-cs2-0 {
1097 atmel,pins =
1098 <AT91_PIOE 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1099 };
1100
1101 pinctrl_ebi_cs3: ebi-cs3-0 {
1102 atmel,pins =
1103 <AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1104 };
1105
1106 pinctrl_ebi_data_0_7: ebi-data-lsb-0 {
1107 atmel,pins =
1108 <AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE
1109 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE
1110 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE
1111 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE
1112 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE
1113 AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE
1114 AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE
1115 AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1116 };
1117
1118 pinctrl_ebi_data_8_15: ebi-data-msb-0 {
1119 atmel,pins =
1120 <AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_NONE
1121 AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE
1122 AT91_PIOB 20 AT91_PERIPH_B AT91_PINCTRL_NONE
1123 AT91_PIOB 21 AT91_PERIPH_B AT91_PINCTRL_NONE
1124 AT91_PIOB 22 AT91_PERIPH_B AT91_PINCTRL_NONE
1125 AT91_PIOB 23 AT91_PERIPH_B AT91_PINCTRL_NONE
1126 AT91_PIOB 24 AT91_PERIPH_B AT91_PINCTRL_NONE
1127 AT91_PIOB 25 AT91_PERIPH_B AT91_PINCTRL_NONE>;
1128 };
1129
1130 pinctrl_ebi_nandrdy: ebi-nandrdy-0 {
1131 atmel,pins =
1132 <AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1133 };
1134
1135 pinctrl_ebi_nrd_nandoe: ebi-nrd-nandoe-0 {
1136 atmel,pins =
1137 <AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1138 };
1139
1140 pinctrl_ebi_nwait: ebi-nwait-0 {
1141 atmel,pins =
1142 <AT91_PIOE 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1143 };
1144
1145 pinctrl_ebi_nwe_nandwe: ebi-nwe-nandwe-0 {
1146 atmel,pins =
1147 <AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1148 };
1149
1150 pinctrl_ebi_nwr1_nbs1: ebi-nwr1-nbs1-0 {
1151 atmel,pins =
1152 <AT91_PIOE 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1153 };
1154 };
1155
1156 i2c0 {
1157 pinctrl_i2c0: i2c0-0 {
1158 atmel,pins =
1159 <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE
1160 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1161 };
1162 };
1163
1164 i2c1 {
1165 pinctrl_i2c1: i2c1-0 {
1166 atmel,pins =
1167 <AT91_PIOE 29 AT91_PERIPH_C AT91_PINCTRL_NONE /* TWD1, conflicts with UART0 RX and DIBP */
1168 AT91_PIOE 30 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* TWCK1, conflicts with UART0 TX and DIBN */
1169 };
1170 };
1171
1172 i2c2 {
1173 pinctrl_i2c2: i2c2-0 {
1174 atmel,pins =
1175 <AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* TWD2, conflicts with RD0 and PWML1 */
1176 AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* TWCK2, conflicts with RF0 */
1177 };
1178 };
1179
1180 isi {
1181 pinctrl_isi_data_0_7: isi-0-data-0-7 {
1182 atmel,pins =
1183 <AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D0 */
1184 AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D1 */
1185 AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D2 */
1186 AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D3 */
1187 AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D4 */
1188 AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D5 */
1189 AT91_PIOC 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D6 */
1190 AT91_PIOC 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D7 */
1191 AT91_PIOB 1 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_PCK, conflict with G0_RXCK */
1192 AT91_PIOB 3 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_VSYNC */
1193 AT91_PIOB 4 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* ISI_HSYNC */
1194 };
1195 pinctrl_isi_data_8_9: isi-0-data-8-9 {
1196 atmel,pins =
1197 <AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_D8, conflicts with SPI0_MISO, PWMH2 */
1198 AT91_PIOC 1 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* ISI_D9, conflicts with SPI0_MOSI, PWML2 */
1199 };
1200 pinctrl_isi_data_10_11: isi-0-data-10-11 {
1201 atmel,pins =
1202 <AT91_PIOC 2 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_D10, conflicts with SPI0_SPCK, PWMH3 */
1203 AT91_PIOC 3 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* ISI_D11, conflicts with SPI0_NPCS0, PWML3 */
1204 };
1205 };
1206
1207 lcd {
1208 pinctrl_lcd_base: lcd-base-0 {
1209 atmel,pins =
1210 <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDVSYNC */
1211 AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDHSYNC */
1212 AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDDEN */
1213 AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPCK */
1214 };
1215 pinctrl_lcd_pwm: lcd-pwm-0 {
1216 atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPWM */
1217 };
1218 pinctrl_lcd_rgb444: lcd-rgb-0 {
1219 atmel,pins =
1220 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
1221 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
1222 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
1223 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
1224 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
1225 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
1226 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
1227 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
1228 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
1229 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
1230 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
1231 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD11 pin */
1232 };
1233 pinctrl_lcd_rgb565: lcd-rgb-1 {
1234 atmel,pins =
1235 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
1236 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
1237 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
1238 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
1239 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
1240 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
1241 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
1242 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
1243 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
1244 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
1245 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
1246 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
1247 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
1248 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
1249 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
1250 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD15 pin */
1251 };
1252 pinctrl_lcd_rgb666: lcd-rgb-2 {
1253 atmel,pins =
1254 <AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
1255 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
1256 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
1257 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
1258 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
1259 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
1260 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
1261 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
1262 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
1263 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
1264 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
1265 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */
1266 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */
1267 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */
1268 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */
1269 AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */
1270 AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */
1271 AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */
1272 };
1273 pinctrl_lcd_rgb777: lcd-rgb-3 {
1274 atmel,pins =
1275 /* LCDDAT0 conflicts with TMS */
1276 <AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
1277 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
1278 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
1279 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
1280 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
1281 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
1282 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
1283 /* LCDDAT8 conflicts with TCK */
1284 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
1285 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
1286 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
1287 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
1288 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
1289 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
1290 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */
1291 /* LCDDAT16 conflicts with NTRST */
1292 AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD17 pin */
1293 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */
1294 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */
1295 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */
1296 AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */
1297 AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */
1298 AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */
1299 };
1300 pinctrl_lcd_rgb888: lcd-rgb-4 {
1301 atmel,pins =
1302 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
1303 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
1304 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
1305 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
1306 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
1307 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
1308 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
1309 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
1310 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
1311 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
1312 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
1313 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
1314 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
1315 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
1316 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
1317 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */
1318 AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD16 pin */
1319 AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD17 pin */
1320 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */
1321 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */
1322 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */
1323 AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */
1324 AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */
1325 AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */
1326 };
1327 };
1328
1329 macb0 {
1330 pinctrl_macb0_rmii: macb0_rmii-0 {
1331 atmel,pins =
1332 <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TX0 */
1333 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TX1 */
1334 AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RX0 */
1335 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RX1 */
1336 AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RXDV */
1337 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RXER */
1338 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TXEN */
1339 AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TXCK */
1340 AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_MDC */
1341 AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_MDIO */
1342 >;
1343 };
1344 };
1345
1346 macb1 {
1347 pinctrl_macb1_rmii: macb1_rmii-0 {
1348 atmel,pins =
1349 <AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_TX0 */
1350 AT91_PIOA 15 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_TX1 */
1351 AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_RX0 */
1352 AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_RX1 */
1353 AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_RXDV */
1354 AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_RXER */
1355 AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_TXEN */
1356 AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_TXCK */
1357 AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_MDC */
1358 AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_MDIO */
1359 >;
1360 };
1361 };
1362
1363 mmc0 {
1364 pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 {
1365 atmel,pins =
1366 <AT91_PIOC 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* MCI0_CK, conflict with PCK1(ISI_MCK) */
1367 AT91_PIOC 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_CDA, conflict with NAND_D0 */
1368 AT91_PIOC 6 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA0, conflict with NAND_D1 */
1369 >;
1370 };
1371 pinctrl_mmc0_dat1_3: mmc0_dat1_3 {
1372 atmel,pins =
1373 <AT91_PIOC 7 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA1, conflict with NAND_D2 */
1374 AT91_PIOC 8 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA2, conflict with NAND_D3 */
1375 AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA3, conflict with NAND_D4 */
1376 >;
1377 };
1378 pinctrl_mmc0_dat4_7: mmc0_dat4_7 {
1379 atmel,pins =
1380 <AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA4, conflict with NAND_D5 */
1381 AT91_PIOC 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA5, conflict with NAND_D6 */
1382 AT91_PIOC 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA6, conflict with NAND_D7 */
1383 AT91_PIOC 13 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA7, conflict with NAND_OE */
1384 >;
1385 };
1386 };
1387
1388 mmc1 {
1389 pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 {
1390 atmel,pins =
1391 <AT91_PIOE 18 AT91_PERIPH_C AT91_PINCTRL_NONE /* MCI1_CK */
1392 AT91_PIOE 19 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_CDA */
1393 AT91_PIOE 20 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA0 */
1394 >;
1395 };
1396 pinctrl_mmc1_dat1_3: mmc1_dat1_3 {
1397 atmel,pins =
1398 <AT91_PIOE 21 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA1 */
1399 AT91_PIOE 22 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA2 */
1400 AT91_PIOE 23 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA3 */
1401 >;
1402 };
1403 };
1404
1405 nand0 {
1406 pinctrl_nand: nand-0 {
1407 atmel,pins =
1408 <AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC13 periph A Read Enable */
1409 AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC14 periph A Write Enable */
1410
1411 AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC17 ALE */
1412 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC18 CLE */
1413
1414 AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC15 NCS3/Chip Enable */
1415 AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC16 NANDRDY */
1416 AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC5 Data bit 0 */
1417 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC6 Data bit 1 */
1418 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC7 Data bit 2 */
1419 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC8 Data bit 3 */
1420 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC9 Data bit 4 */
1421 AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC10 Data bit 5 */
1422 AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC11 periph A Data bit 6 */
1423 AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC12 periph A Data bit 7 */
1424 };
1425 };
1426
1427 spi0 {
1428 pinctrl_spi0: spi0-0 {
1429 atmel,pins =
1430 <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_MISO */
1431 AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_MOSI */
1432 AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_SPCK */
1433 >;
1434 };
1435 };
1436
1437 ssc0 {
1438 pinctrl_ssc0_tx: ssc0_tx {
1439 atmel,pins =
1440 <AT91_PIOB 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* TK0 */
1441 AT91_PIOB 31 AT91_PERIPH_B AT91_PINCTRL_NONE /* TF0 */
1442 AT91_PIOB 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TD0 */
1443 };
1444
1445 pinctrl_ssc0_rx: ssc0_rx {
1446 atmel,pins =
1447 <AT91_PIOB 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* RK0 */
1448 AT91_PIOB 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* RF0 */
1449 AT91_PIOB 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* RD0 */
1450 };
1451 };
1452
1453 ssc1 {
1454 pinctrl_ssc1_tx: ssc1_tx {
1455 atmel,pins =
1456 <AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* TK1 */
1457 AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* TF1 */
1458 AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TD1 */
1459 };
1460
1461 pinctrl_ssc1_rx: ssc1_rx {
1462 atmel,pins =
1463 <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* RK1 */
1464 AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* RF1 */
1465 AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* RD1 */
1466 };
1467 };
1468
1469 spi1 {
1470 pinctrl_spi1: spi1-0 {
1471 atmel,pins =
1472 <AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI1_MISO */
1473 AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI1_MOSI */
1474 AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI1_SPCK */
1475 >;
1476 };
1477 };
1478
1479 spi2 {
1480 pinctrl_spi2: spi2-0 {
1481 atmel,pins =
1482 <AT91_PIOD 11 AT91_PERIPH_B AT91_PINCTRL_NONE /* SPI2_MISO conflicts with RTS0 */
1483 AT91_PIOD 13 AT91_PERIPH_B AT91_PINCTRL_NONE /* SPI2_MOSI conflicts with TXD0 */
1484 AT91_PIOD 15 AT91_PERIPH_B AT91_PINCTRL_NONE /* SPI2_SPCK conflicts with RTS1 */
1485 >;
1486 };
1487 };
1488
1489 uart0 {
1490 pinctrl_uart0: uart0-0 {
1491 atmel,pins =
1492 <AT91_PIOE 29 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* RXD */
1493 AT91_PIOE 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* TXD */
1494 >;
1495 };
1496 };
1497
1498 uart1 {
1499 pinctrl_uart1: uart1-0 {
1500 atmel,pins =
1501 <AT91_PIOC 25 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* RXD */
1502 AT91_PIOC 26 AT91_PERIPH_C AT91_PINCTRL_NONE /* TXD */
1503 >;
1504 };
1505 };
1506
1507 usart0 {
1508 pinctrl_usart0: usart0-0 {
1509 atmel,pins =
1510 <AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* RXD */
1511 AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* TXD */
1512 >;
1513 };
1514 pinctrl_usart0_rts: usart0_rts-0 {
1515 atmel,pins = <AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1516 };
1517 pinctrl_usart0_cts: usart0_cts-0 {
1518 atmel,pins = <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1519 };
1520 };
1521
1522 usart1 {
1523 pinctrl_usart1: usart1-0 {
1524 atmel,pins =
1525 <AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* RXD */
1526 AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* TXD */
1527 >;
1528 };
1529 pinctrl_usart1_rts: usart1_rts-0 {
1530 atmel,pins = <AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1531 };
1532 pinctrl_usart1_cts: usart1_cts-0 {
1533 atmel,pins = <AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1534 };
1535 };
1536
1537 usart2 {
1538 pinctrl_usart2: usart2-0 {
1539 atmel,pins =
1540 <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* RXD - conflicts with G0_CRS, ISI_HSYNC */
1541 AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_NONE /* TXD - conflicts with G0_COL, PCK2 */
1542 >;
1543 };
1544 pinctrl_usart2_rts: usart2_rts-0 {
1545 atmel,pins = <AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with G0_RX3, PWMH1 */
1546 };
1547 pinctrl_usart2_cts: usart2_cts-0 {
1548 atmel,pins = <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with G0_TXER, ISI_VSYNC */
1549 };
1550 };
1551
1552 usart3 {
1553 pinctrl_usart3: usart3-0 {
1554 atmel,pins =
1555 <AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* RXD */
1556 AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_NONE /* TXD */
1557 >;
1558 };
1559 };
1560
1561 usart4 {
1562 pinctrl_usart4: usart4-0 {
1563 atmel,pins =
1564 <AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* RXD */
1565 AT91_PIOE 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* TXD */
1566 >;
1567 };
1568 pinctrl_usart4_rts: usart4_rts-0 {
1569 atmel,pins = <AT91_PIOE 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with NWAIT, A19 */
1570 };
1571 pinctrl_usart4_cts: usart4_cts-0 {
1572 atmel,pins = <AT91_PIOE 0 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with A0/NBS0, MCI0_CDB */
1573 };
1574 };
1575 };
1576
1577 aic: interrupt-controller@fc06e000 {
1578 #interrupt-cells = <3>;
1579 compatible = "atmel,sama5d4-aic";
1580 interrupt-controller;
1581 reg = <0xfc06e000 0x200>;
1582 atmel,external-irqs = <56>;
1583 };
1584 };
1585 };
1586 };
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