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Merge remote-tracking branch 'mkp-scsi/fixes' into fixes
[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / socfpga.dtsi
1 /*
2 * Copyright (C) 2012 Altera <www.altera.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18 #include "skeleton.dtsi"
19 #include <dt-bindings/reset/altr,rst-mgr.h>
20
21 / {
22 #address-cells = <1>;
23 #size-cells = <1>;
24
25 aliases {
26 ethernet0 = &gmac0;
27 ethernet1 = &gmac1;
28 serial0 = &uart0;
29 serial1 = &uart1;
30 timer0 = &timer0;
31 timer1 = &timer1;
32 timer2 = &timer2;
33 timer3 = &timer3;
34 };
35
36 cpus {
37 #address-cells = <1>;
38 #size-cells = <0>;
39 enable-method = "altr,socfpga-smp";
40
41 cpu@0 {
42 compatible = "arm,cortex-a9";
43 device_type = "cpu";
44 reg = <0>;
45 next-level-cache = <&L2>;
46 };
47 cpu@1 {
48 compatible = "arm,cortex-a9";
49 device_type = "cpu";
50 reg = <1>;
51 next-level-cache = <&L2>;
52 };
53 };
54
55 intc: intc@fffed000 {
56 compatible = "arm,cortex-a9-gic";
57 #interrupt-cells = <3>;
58 interrupt-controller;
59 reg = <0xfffed000 0x1000>,
60 <0xfffec100 0x100>;
61 };
62
63 soc {
64 #address-cells = <1>;
65 #size-cells = <1>;
66 compatible = "simple-bus";
67 device_type = "soc";
68 interrupt-parent = <&intc>;
69 ranges;
70
71 amba {
72 compatible = "simple-bus";
73 #address-cells = <1>;
74 #size-cells = <1>;
75 ranges;
76
77 pdma: pdma@ffe01000 {
78 compatible = "arm,pl330", "arm,primecell";
79 reg = <0xffe01000 0x1000>;
80 interrupts = <0 104 4>,
81 <0 105 4>,
82 <0 106 4>,
83 <0 107 4>,
84 <0 108 4>,
85 <0 109 4>,
86 <0 110 4>,
87 <0 111 4>;
88 #dma-cells = <1>;
89 #dma-channels = <8>;
90 #dma-requests = <32>;
91 clocks = <&l4_main_clk>;
92 clock-names = "apb_pclk";
93 };
94 };
95
96 base_fpga_region {
97 compatible = "fpga-region";
98 fpga-mgr = <&fpgamgr0>;
99
100 #address-cells = <0x1>;
101 #size-cells = <0x1>;
102 };
103
104 can0: can@ffc00000 {
105 compatible = "bosch,d_can";
106 reg = <0xffc00000 0x1000>;
107 interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>;
108 clocks = <&can0_clk>;
109 status = "disabled";
110 };
111
112 can1: can@ffc01000 {
113 compatible = "bosch,d_can";
114 reg = <0xffc01000 0x1000>;
115 interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>;
116 clocks = <&can1_clk>;
117 status = "disabled";
118 };
119
120 clkmgr@ffd04000 {
121 compatible = "altr,clk-mgr";
122 reg = <0xffd04000 0x1000>;
123
124 clocks {
125 #address-cells = <1>;
126 #size-cells = <0>;
127
128 osc1: osc1 {
129 #clock-cells = <0>;
130 compatible = "fixed-clock";
131 };
132
133 osc2: osc2 {
134 #clock-cells = <0>;
135 compatible = "fixed-clock";
136 };
137
138 f2s_periph_ref_clk: f2s_periph_ref_clk {
139 #clock-cells = <0>;
140 compatible = "fixed-clock";
141 };
142
143 f2s_sdram_ref_clk: f2s_sdram_ref_clk {
144 #clock-cells = <0>;
145 compatible = "fixed-clock";
146 };
147
148 main_pll: main_pll {
149 #address-cells = <1>;
150 #size-cells = <0>;
151 #clock-cells = <0>;
152 compatible = "altr,socfpga-pll-clock";
153 clocks = <&osc1>;
154 reg = <0x40>;
155
156 mpuclk: mpuclk {
157 #clock-cells = <0>;
158 compatible = "altr,socfpga-perip-clk";
159 clocks = <&main_pll>;
160 div-reg = <0xe0 0 9>;
161 reg = <0x48>;
162 };
163
164 mainclk: mainclk {
165 #clock-cells = <0>;
166 compatible = "altr,socfpga-perip-clk";
167 clocks = <&main_pll>;
168 div-reg = <0xe4 0 9>;
169 reg = <0x4C>;
170 };
171
172 dbg_base_clk: dbg_base_clk {
173 #clock-cells = <0>;
174 compatible = "altr,socfpga-perip-clk";
175 clocks = <&main_pll>, <&osc1>;
176 div-reg = <0xe8 0 9>;
177 reg = <0x50>;
178 };
179
180 main_qspi_clk: main_qspi_clk {
181 #clock-cells = <0>;
182 compatible = "altr,socfpga-perip-clk";
183 clocks = <&main_pll>;
184 reg = <0x54>;
185 };
186
187 main_nand_sdmmc_clk: main_nand_sdmmc_clk {
188 #clock-cells = <0>;
189 compatible = "altr,socfpga-perip-clk";
190 clocks = <&main_pll>;
191 reg = <0x58>;
192 };
193
194 cfg_h2f_usr0_clk: cfg_h2f_usr0_clk {
195 #clock-cells = <0>;
196 compatible = "altr,socfpga-perip-clk";
197 clocks = <&main_pll>;
198 reg = <0x5C>;
199 };
200 };
201
202 periph_pll: periph_pll {
203 #address-cells = <1>;
204 #size-cells = <0>;
205 #clock-cells = <0>;
206 compatible = "altr,socfpga-pll-clock";
207 clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>;
208 reg = <0x80>;
209
210 emac0_clk: emac0_clk {
211 #clock-cells = <0>;
212 compatible = "altr,socfpga-perip-clk";
213 clocks = <&periph_pll>;
214 reg = <0x88>;
215 };
216
217 emac1_clk: emac1_clk {
218 #clock-cells = <0>;
219 compatible = "altr,socfpga-perip-clk";
220 clocks = <&periph_pll>;
221 reg = <0x8C>;
222 };
223
224 per_qspi_clk: per_qsi_clk {
225 #clock-cells = <0>;
226 compatible = "altr,socfpga-perip-clk";
227 clocks = <&periph_pll>;
228 reg = <0x90>;
229 };
230
231 per_nand_mmc_clk: per_nand_mmc_clk {
232 #clock-cells = <0>;
233 compatible = "altr,socfpga-perip-clk";
234 clocks = <&periph_pll>;
235 reg = <0x94>;
236 };
237
238 per_base_clk: per_base_clk {
239 #clock-cells = <0>;
240 compatible = "altr,socfpga-perip-clk";
241 clocks = <&periph_pll>;
242 reg = <0x98>;
243 };
244
245 h2f_usr1_clk: h2f_usr1_clk {
246 #clock-cells = <0>;
247 compatible = "altr,socfpga-perip-clk";
248 clocks = <&periph_pll>;
249 reg = <0x9C>;
250 };
251 };
252
253 sdram_pll: sdram_pll {
254 #address-cells = <1>;
255 #size-cells = <0>;
256 #clock-cells = <0>;
257 compatible = "altr,socfpga-pll-clock";
258 clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>;
259 reg = <0xC0>;
260
261 ddr_dqs_clk: ddr_dqs_clk {
262 #clock-cells = <0>;
263 compatible = "altr,socfpga-perip-clk";
264 clocks = <&sdram_pll>;
265 reg = <0xC8>;
266 };
267
268 ddr_2x_dqs_clk: ddr_2x_dqs_clk {
269 #clock-cells = <0>;
270 compatible = "altr,socfpga-perip-clk";
271 clocks = <&sdram_pll>;
272 reg = <0xCC>;
273 };
274
275 ddr_dq_clk: ddr_dq_clk {
276 #clock-cells = <0>;
277 compatible = "altr,socfpga-perip-clk";
278 clocks = <&sdram_pll>;
279 reg = <0xD0>;
280 };
281
282 h2f_usr2_clk: h2f_usr2_clk {
283 #clock-cells = <0>;
284 compatible = "altr,socfpga-perip-clk";
285 clocks = <&sdram_pll>;
286 reg = <0xD4>;
287 };
288 };
289
290 mpu_periph_clk: mpu_periph_clk {
291 #clock-cells = <0>;
292 compatible = "altr,socfpga-perip-clk";
293 clocks = <&mpuclk>;
294 fixed-divider = <4>;
295 };
296
297 mpu_l2_ram_clk: mpu_l2_ram_clk {
298 #clock-cells = <0>;
299 compatible = "altr,socfpga-perip-clk";
300 clocks = <&mpuclk>;
301 fixed-divider = <2>;
302 };
303
304 l4_main_clk: l4_main_clk {
305 #clock-cells = <0>;
306 compatible = "altr,socfpga-gate-clk";
307 clocks = <&mainclk>;
308 clk-gate = <0x60 0>;
309 };
310
311 l3_main_clk: l3_main_clk {
312 #clock-cells = <0>;
313 compatible = "altr,socfpga-perip-clk";
314 clocks = <&mainclk>;
315 fixed-divider = <1>;
316 };
317
318 l3_mp_clk: l3_mp_clk {
319 #clock-cells = <0>;
320 compatible = "altr,socfpga-gate-clk";
321 clocks = <&mainclk>;
322 div-reg = <0x64 0 2>;
323 clk-gate = <0x60 1>;
324 };
325
326 l3_sp_clk: l3_sp_clk {
327 #clock-cells = <0>;
328 compatible = "altr,socfpga-gate-clk";
329 clocks = <&l3_mp_clk>;
330 div-reg = <0x64 2 2>;
331 };
332
333 l4_mp_clk: l4_mp_clk {
334 #clock-cells = <0>;
335 compatible = "altr,socfpga-gate-clk";
336 clocks = <&mainclk>, <&per_base_clk>;
337 div-reg = <0x64 4 3>;
338 clk-gate = <0x60 2>;
339 };
340
341 l4_sp_clk: l4_sp_clk {
342 #clock-cells = <0>;
343 compatible = "altr,socfpga-gate-clk";
344 clocks = <&mainclk>, <&per_base_clk>;
345 div-reg = <0x64 7 3>;
346 clk-gate = <0x60 3>;
347 };
348
349 dbg_at_clk: dbg_at_clk {
350 #clock-cells = <0>;
351 compatible = "altr,socfpga-gate-clk";
352 clocks = <&dbg_base_clk>;
353 div-reg = <0x68 0 2>;
354 clk-gate = <0x60 4>;
355 };
356
357 dbg_clk: dbg_clk {
358 #clock-cells = <0>;
359 compatible = "altr,socfpga-gate-clk";
360 clocks = <&dbg_at_clk>;
361 div-reg = <0x68 2 2>;
362 clk-gate = <0x60 5>;
363 };
364
365 dbg_trace_clk: dbg_trace_clk {
366 #clock-cells = <0>;
367 compatible = "altr,socfpga-gate-clk";
368 clocks = <&dbg_base_clk>;
369 div-reg = <0x6C 0 3>;
370 clk-gate = <0x60 6>;
371 };
372
373 dbg_timer_clk: dbg_timer_clk {
374 #clock-cells = <0>;
375 compatible = "altr,socfpga-gate-clk";
376 clocks = <&dbg_base_clk>;
377 clk-gate = <0x60 7>;
378 };
379
380 cfg_clk: cfg_clk {
381 #clock-cells = <0>;
382 compatible = "altr,socfpga-gate-clk";
383 clocks = <&cfg_h2f_usr0_clk>;
384 clk-gate = <0x60 8>;
385 };
386
387 h2f_user0_clk: h2f_user0_clk {
388 #clock-cells = <0>;
389 compatible = "altr,socfpga-gate-clk";
390 clocks = <&cfg_h2f_usr0_clk>;
391 clk-gate = <0x60 9>;
392 };
393
394 emac_0_clk: emac_0_clk {
395 #clock-cells = <0>;
396 compatible = "altr,socfpga-gate-clk";
397 clocks = <&emac0_clk>;
398 clk-gate = <0xa0 0>;
399 };
400
401 emac_1_clk: emac_1_clk {
402 #clock-cells = <0>;
403 compatible = "altr,socfpga-gate-clk";
404 clocks = <&emac1_clk>;
405 clk-gate = <0xa0 1>;
406 };
407
408 usb_mp_clk: usb_mp_clk {
409 #clock-cells = <0>;
410 compatible = "altr,socfpga-gate-clk";
411 clocks = <&per_base_clk>;
412 clk-gate = <0xa0 2>;
413 div-reg = <0xa4 0 3>;
414 };
415
416 spi_m_clk: spi_m_clk {
417 #clock-cells = <0>;
418 compatible = "altr,socfpga-gate-clk";
419 clocks = <&per_base_clk>;
420 clk-gate = <0xa0 3>;
421 div-reg = <0xa4 3 3>;
422 };
423
424 can0_clk: can0_clk {
425 #clock-cells = <0>;
426 compatible = "altr,socfpga-gate-clk";
427 clocks = <&per_base_clk>;
428 clk-gate = <0xa0 4>;
429 div-reg = <0xa4 6 3>;
430 };
431
432 can1_clk: can1_clk {
433 #clock-cells = <0>;
434 compatible = "altr,socfpga-gate-clk";
435 clocks = <&per_base_clk>;
436 clk-gate = <0xa0 5>;
437 div-reg = <0xa4 9 3>;
438 };
439
440 gpio_db_clk: gpio_db_clk {
441 #clock-cells = <0>;
442 compatible = "altr,socfpga-gate-clk";
443 clocks = <&per_base_clk>;
444 clk-gate = <0xa0 6>;
445 div-reg = <0xa8 0 24>;
446 };
447
448 h2f_user1_clk: h2f_user1_clk {
449 #clock-cells = <0>;
450 compatible = "altr,socfpga-gate-clk";
451 clocks = <&h2f_usr1_clk>;
452 clk-gate = <0xa0 7>;
453 };
454
455 sdmmc_clk: sdmmc_clk {
456 #clock-cells = <0>;
457 compatible = "altr,socfpga-gate-clk";
458 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
459 clk-gate = <0xa0 8>;
460 clk-phase = <0 135>;
461 };
462
463 sdmmc_clk_divided: sdmmc_clk_divided {
464 #clock-cells = <0>;
465 compatible = "altr,socfpga-gate-clk";
466 clocks = <&sdmmc_clk>;
467 clk-gate = <0xa0 8>;
468 fixed-divider = <4>;
469 };
470
471 nand_x_clk: nand_x_clk {
472 #clock-cells = <0>;
473 compatible = "altr,socfpga-gate-clk";
474 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
475 clk-gate = <0xa0 9>;
476 };
477
478 nand_clk: nand_clk {
479 #clock-cells = <0>;
480 compatible = "altr,socfpga-gate-clk";
481 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
482 clk-gate = <0xa0 10>;
483 fixed-divider = <4>;
484 };
485
486 qspi_clk: qspi_clk {
487 #clock-cells = <0>;
488 compatible = "altr,socfpga-gate-clk";
489 clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;
490 clk-gate = <0xa0 11>;
491 };
492
493 ddr_dqs_clk_gate: ddr_dqs_clk_gate {
494 #clock-cells = <0>;
495 compatible = "altr,socfpga-gate-clk";
496 clocks = <&ddr_dqs_clk>;
497 clk-gate = <0xd8 0>;
498 };
499
500 ddr_2x_dqs_clk_gate: ddr_2x_dqs_clk_gate {
501 #clock-cells = <0>;
502 compatible = "altr,socfpga-gate-clk";
503 clocks = <&ddr_2x_dqs_clk>;
504 clk-gate = <0xd8 1>;
505 };
506
507 ddr_dq_clk_gate: ddr_dq_clk_gate {
508 #clock-cells = <0>;
509 compatible = "altr,socfpga-gate-clk";
510 clocks = <&ddr_dq_clk>;
511 clk-gate = <0xd8 2>;
512 };
513
514 h2f_user2_clk: h2f_user2_clk {
515 #clock-cells = <0>;
516 compatible = "altr,socfpga-gate-clk";
517 clocks = <&h2f_usr2_clk>;
518 clk-gate = <0xd8 3>;
519 };
520
521 };
522 };
523
524 fpga_bridge0: fpga_bridge@ff400000 {
525 compatible = "altr,socfpga-lwhps2fpga-bridge";
526 reg = <0xff400000 0x100000>;
527 resets = <&rst LWHPS2FPGA_RESET>;
528 clocks = <&l4_main_clk>;
529 };
530
531 fpga_bridge1: fpga_bridge@ff500000 {
532 compatible = "altr,socfpga-hps2fpga-bridge";
533 reg = <0xff500000 0x10000>;
534 resets = <&rst HPS2FPGA_RESET>;
535 clocks = <&l4_main_clk>;
536 };
537
538 fpgamgr0: fpgamgr@ff706000 {
539 compatible = "altr,socfpga-fpga-mgr";
540 reg = <0xff706000 0x1000
541 0xffb90000 0x4>;
542 interrupts = <0 175 4>;
543 };
544
545 gmac0: ethernet@ff700000 {
546 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
547 altr,sysmgr-syscon = <&sysmgr 0x60 0>;
548 reg = <0xff700000 0x2000>;
549 interrupts = <0 115 4>;
550 interrupt-names = "macirq";
551 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
552 clocks = <&emac0_clk>;
553 clock-names = "stmmaceth";
554 resets = <&rst EMAC0_RESET>;
555 reset-names = "stmmaceth";
556 snps,multicast-filter-bins = <256>;
557 snps,perfect-filter-entries = <128>;
558 tx-fifo-depth = <4096>;
559 rx-fifo-depth = <4096>;
560 status = "disabled";
561 };
562
563 gmac1: ethernet@ff702000 {
564 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
565 altr,sysmgr-syscon = <&sysmgr 0x60 2>;
566 reg = <0xff702000 0x2000>;
567 interrupts = <0 120 4>;
568 interrupt-names = "macirq";
569 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
570 clocks = <&emac1_clk>;
571 clock-names = "stmmaceth";
572 resets = <&rst EMAC1_RESET>;
573 reset-names = "stmmaceth";
574 snps,multicast-filter-bins = <256>;
575 snps,perfect-filter-entries = <128>;
576 tx-fifo-depth = <4096>;
577 rx-fifo-depth = <4096>;
578 status = "disabled";
579 };
580
581 gpio0: gpio@ff708000 {
582 #address-cells = <1>;
583 #size-cells = <0>;
584 compatible = "snps,dw-apb-gpio";
585 reg = <0xff708000 0x1000>;
586 clocks = <&l4_mp_clk>;
587 status = "disabled";
588
589 porta: gpio-controller@0 {
590 compatible = "snps,dw-apb-gpio-port";
591 gpio-controller;
592 #gpio-cells = <2>;
593 snps,nr-gpios = <29>;
594 reg = <0>;
595 interrupt-controller;
596 #interrupt-cells = <2>;
597 interrupts = <0 164 4>;
598 };
599 };
600
601 gpio1: gpio@ff709000 {
602 #address-cells = <1>;
603 #size-cells = <0>;
604 compatible = "snps,dw-apb-gpio";
605 reg = <0xff709000 0x1000>;
606 clocks = <&l4_mp_clk>;
607 status = "disabled";
608
609 portb: gpio-controller@0 {
610 compatible = "snps,dw-apb-gpio-port";
611 gpio-controller;
612 #gpio-cells = <2>;
613 snps,nr-gpios = <29>;
614 reg = <0>;
615 interrupt-controller;
616 #interrupt-cells = <2>;
617 interrupts = <0 165 4>;
618 };
619 };
620
621 gpio2: gpio@ff70a000 {
622 #address-cells = <1>;
623 #size-cells = <0>;
624 compatible = "snps,dw-apb-gpio";
625 reg = <0xff70a000 0x1000>;
626 clocks = <&l4_mp_clk>;
627 status = "disabled";
628
629 portc: gpio-controller@0 {
630 compatible = "snps,dw-apb-gpio-port";
631 gpio-controller;
632 #gpio-cells = <2>;
633 snps,nr-gpios = <27>;
634 reg = <0>;
635 interrupt-controller;
636 #interrupt-cells = <2>;
637 interrupts = <0 166 4>;
638 };
639 };
640
641 i2c0: i2c@ffc04000 {
642 #address-cells = <1>;
643 #size-cells = <0>;
644 compatible = "snps,designware-i2c";
645 reg = <0xffc04000 0x1000>;
646 clocks = <&l4_sp_clk>;
647 interrupts = <0 158 0x4>;
648 status = "disabled";
649 };
650
651 i2c1: i2c@ffc05000 {
652 #address-cells = <1>;
653 #size-cells = <0>;
654 compatible = "snps,designware-i2c";
655 reg = <0xffc05000 0x1000>;
656 clocks = <&l4_sp_clk>;
657 interrupts = <0 159 0x4>;
658 status = "disabled";
659 };
660
661 i2c2: i2c@ffc06000 {
662 #address-cells = <1>;
663 #size-cells = <0>;
664 compatible = "snps,designware-i2c";
665 reg = <0xffc06000 0x1000>;
666 clocks = <&l4_sp_clk>;
667 interrupts = <0 160 0x4>;
668 status = "disabled";
669 };
670
671 i2c3: i2c@ffc07000 {
672 #address-cells = <1>;
673 #size-cells = <0>;
674 compatible = "snps,designware-i2c";
675 reg = <0xffc07000 0x1000>;
676 clocks = <&l4_sp_clk>;
677 interrupts = <0 161 0x4>;
678 status = "disabled";
679 };
680
681 eccmgr: eccmgr@ffd08140 {
682 compatible = "altr,socfpga-ecc-manager";
683 #address-cells = <1>;
684 #size-cells = <1>;
685 ranges;
686
687 l2-ecc@ffd08140 {
688 compatible = "altr,socfpga-l2-ecc";
689 reg = <0xffd08140 0x4>;
690 interrupts = <0 36 1>, <0 37 1>;
691 };
692
693 ocram-ecc@ffd08144 {
694 compatible = "altr,socfpga-ocram-ecc";
695 reg = <0xffd08144 0x4>;
696 iram = <&ocram>;
697 interrupts = <0 178 1>, <0 179 1>;
698 };
699 };
700
701 L2: l2-cache@fffef000 {
702 compatible = "arm,pl310-cache";
703 reg = <0xfffef000 0x1000>;
704 interrupts = <0 38 0x04>;
705 cache-unified;
706 cache-level = <2>;
707 arm,tag-latency = <1 1 1>;
708 arm,data-latency = <2 1 1>;
709 prefetch-data = <1>;
710 prefetch-instr = <1>;
711 arm,shared-override;
712 arm,double-linefill = <1>;
713 arm,double-linefill-incr = <0>;
714 arm,double-linefill-wrap = <1>;
715 arm,prefetch-drop = <0>;
716 arm,prefetch-offset = <7>;
717 };
718
719 l3regs@0xff800000 {
720 compatible = "altr,l3regs", "syscon";
721 reg = <0xff800000 0x1000>;
722 };
723
724 mmc: dwmmc0@ff704000 {
725 compatible = "altr,socfpga-dw-mshc";
726 reg = <0xff704000 0x1000>;
727 interrupts = <0 139 4>;
728 fifo-depth = <0x400>;
729 #address-cells = <1>;
730 #size-cells = <0>;
731 clocks = <&l4_mp_clk>, <&sdmmc_clk_divided>;
732 clock-names = "biu", "ciu";
733 status = "disabled";
734 };
735
736 nand0: nand@ff900000 {
737 #address-cells = <0x1>;
738 #size-cells = <0x1>;
739 compatible = "denali,denali-nand-dt";
740 reg = <0xff900000 0x100000>,
741 <0xffb80000 0x10000>;
742 reg-names = "nand_data", "denali_reg";
743 interrupts = <0x0 0x90 0x4>;
744 dma-mask = <0xffffffff>;
745 clocks = <&nand_clk>;
746 status = "disabled";
747 };
748
749 ocram: sram@ffff0000 {
750 compatible = "mmio-sram";
751 reg = <0xffff0000 0x10000>;
752 };
753
754 qspi: spi@ff705000 {
755 compatible = "cdns,qspi-nor";
756 #address-cells = <1>;
757 #size-cells = <0>;
758 reg = <0xff705000 0x1000>,
759 <0xffa00000 0x1000>;
760 interrupts = <0 151 4>;
761 cdns,fifo-depth = <128>;
762 cdns,fifo-width = <4>;
763 cdns,trigger-address = <0x00000000>;
764 clocks = <&qspi_clk>;
765 status = "disabled";
766 };
767
768 rst: rstmgr@ffd05000 {
769 #reset-cells = <1>;
770 compatible = "altr,rst-mgr";
771 reg = <0xffd05000 0x1000>;
772 altr,modrst-offset = <0x10>;
773 };
774
775 scu: snoop-control-unit@fffec000 {
776 compatible = "arm,cortex-a9-scu";
777 reg = <0xfffec000 0x100>;
778 };
779
780 sdr: sdr@ffc25000 {
781 compatible = "altr,sdr-ctl", "syscon";
782 reg = <0xffc25000 0x1000>;
783 };
784
785 sdramedac {
786 compatible = "altr,sdram-edac";
787 altr,sdr-syscon = <&sdr>;
788 interrupts = <0 39 4>;
789 };
790
791 spi0: spi@fff00000 {
792 compatible = "snps,dw-apb-ssi";
793 #address-cells = <1>;
794 #size-cells = <0>;
795 reg = <0xfff00000 0x1000>;
796 interrupts = <0 154 4>;
797 num-cs = <4>;
798 clocks = <&spi_m_clk>;
799 status = "disabled";
800 };
801
802 spi1: spi@fff01000 {
803 compatible = "snps,dw-apb-ssi";
804 #address-cells = <1>;
805 #size-cells = <0>;
806 reg = <0xfff01000 0x1000>;
807 interrupts = <0 155 4>;
808 num-cs = <4>;
809 clocks = <&spi_m_clk>;
810 status = "disabled";
811 };
812
813 sysmgr: sysmgr@ffd08000 {
814 compatible = "altr,sys-mgr", "syscon";
815 reg = <0xffd08000 0x4000>;
816 };
817
818 /* Local timer */
819 timer@fffec600 {
820 compatible = "arm,cortex-a9-twd-timer";
821 reg = <0xfffec600 0x100>;
822 interrupts = <1 13 0xf04>;
823 clocks = <&mpu_periph_clk>;
824 };
825
826 timer0: timer0@ffc08000 {
827 compatible = "snps,dw-apb-timer";
828 interrupts = <0 167 4>;
829 reg = <0xffc08000 0x1000>;
830 clocks = <&l4_sp_clk>;
831 clock-names = "timer";
832 };
833
834 timer1: timer1@ffc09000 {
835 compatible = "snps,dw-apb-timer";
836 interrupts = <0 168 4>;
837 reg = <0xffc09000 0x1000>;
838 clocks = <&l4_sp_clk>;
839 clock-names = "timer";
840 };
841
842 timer2: timer2@ffd00000 {
843 compatible = "snps,dw-apb-timer";
844 interrupts = <0 169 4>;
845 reg = <0xffd00000 0x1000>;
846 clocks = <&osc1>;
847 clock-names = "timer";
848 };
849
850 timer3: timer3@ffd01000 {
851 compatible = "snps,dw-apb-timer";
852 interrupts = <0 170 4>;
853 reg = <0xffd01000 0x1000>;
854 clocks = <&osc1>;
855 clock-names = "timer";
856 };
857
858 uart0: serial0@ffc02000 {
859 compatible = "snps,dw-apb-uart";
860 reg = <0xffc02000 0x1000>;
861 interrupts = <0 162 4>;
862 reg-shift = <2>;
863 reg-io-width = <4>;
864 clocks = <&l4_sp_clk>;
865 dmas = <&pdma 28>,
866 <&pdma 29>;
867 dma-names = "tx", "rx";
868 };
869
870 uart1: serial1@ffc03000 {
871 compatible = "snps,dw-apb-uart";
872 reg = <0xffc03000 0x1000>;
873 interrupts = <0 163 4>;
874 reg-shift = <2>;
875 reg-io-width = <4>;
876 clocks = <&l4_sp_clk>;
877 dmas = <&pdma 30>,
878 <&pdma 31>;
879 dma-names = "tx", "rx";
880 };
881
882 usbphy0: usbphy@0 {
883 #phy-cells = <0>;
884 compatible = "usb-nop-xceiv";
885 status = "okay";
886 };
887
888 usb0: usb@ffb00000 {
889 compatible = "snps,dwc2";
890 reg = <0xffb00000 0xffff>;
891 interrupts = <0 125 4>;
892 clocks = <&usb_mp_clk>;
893 clock-names = "otg";
894 resets = <&rst USB0_RESET>;
895 reset-names = "dwc2";
896 phys = <&usbphy0>;
897 phy-names = "usb2-phy";
898 status = "disabled";
899 };
900
901 usb1: usb@ffb40000 {
902 compatible = "snps,dwc2";
903 reg = <0xffb40000 0xffff>;
904 interrupts = <0 128 4>;
905 clocks = <&usb_mp_clk>;
906 clock-names = "otg";
907 resets = <&rst USB1_RESET>;
908 reset-names = "dwc2";
909 phys = <&usbphy0>;
910 phy-names = "usb2-phy";
911 status = "disabled";
912 };
913
914 watchdog0: watchdog@ffd02000 {
915 compatible = "snps,dw-wdt";
916 reg = <0xffd02000 0x1000>;
917 interrupts = <0 171 4>;
918 clocks = <&osc1>;
919 status = "disabled";
920 };
921
922 watchdog1: watchdog@ffd03000 {
923 compatible = "snps,dw-wdt";
924 reg = <0xffd03000 0x1000>;
925 interrupts = <0 172 4>;
926 clocks = <&osc1>;
927 status = "disabled";
928 };
929 };
930 };
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