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Merge tag 'linux-watchdog-4.17-rc1' of git://www.linux-watchdog.org/linux-watchdog
[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / socfpga.dtsi
1 /*
2 * Copyright (C) 2012 Altera <www.altera.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18 #include <dt-bindings/reset/altr,rst-mgr.h>
19
20 / {
21 #address-cells = <1>;
22 #size-cells = <1>;
23
24 aliases {
25 ethernet0 = &gmac0;
26 ethernet1 = &gmac1;
27 serial0 = &uart0;
28 serial1 = &uart1;
29 timer0 = &timer0;
30 timer1 = &timer1;
31 timer2 = &timer2;
32 timer3 = &timer3;
33 };
34
35 cpus {
36 #address-cells = <1>;
37 #size-cells = <0>;
38 enable-method = "altr,socfpga-smp";
39
40 cpu0: cpu@0 {
41 compatible = "arm,cortex-a9";
42 device_type = "cpu";
43 reg = <0>;
44 next-level-cache = <&L2>;
45 };
46 cpu1: cpu@1 {
47 compatible = "arm,cortex-a9";
48 device_type = "cpu";
49 reg = <1>;
50 next-level-cache = <&L2>;
51 };
52 };
53
54 pmu: pmu@ff111000 {
55 compatible = "arm,cortex-a9-pmu";
56 interrupt-parent = <&intc>;
57 interrupts = <0 176 4>, <0 177 4>;
58 interrupt-affinity = <&cpu0>, <&cpu1>;
59 reg = <0xff111000 0x1000>,
60 <0xff113000 0x1000>;
61 };
62
63 intc: intc@fffed000 {
64 compatible = "arm,cortex-a9-gic";
65 #interrupt-cells = <3>;
66 interrupt-controller;
67 reg = <0xfffed000 0x1000>,
68 <0xfffec100 0x100>;
69 };
70
71 soc {
72 #address-cells = <1>;
73 #size-cells = <1>;
74 compatible = "simple-bus";
75 device_type = "soc";
76 interrupt-parent = <&intc>;
77 ranges;
78
79 amba {
80 compatible = "simple-bus";
81 #address-cells = <1>;
82 #size-cells = <1>;
83 ranges;
84
85 pdma: pdma@ffe01000 {
86 compatible = "arm,pl330", "arm,primecell";
87 reg = <0xffe01000 0x1000>;
88 interrupts = <0 104 4>,
89 <0 105 4>,
90 <0 106 4>,
91 <0 107 4>,
92 <0 108 4>,
93 <0 109 4>,
94 <0 110 4>,
95 <0 111 4>;
96 #dma-cells = <1>;
97 #dma-channels = <8>;
98 #dma-requests = <32>;
99 clocks = <&l4_main_clk>;
100 clock-names = "apb_pclk";
101 };
102 };
103
104 base_fpga_region {
105 compatible = "fpga-region";
106 fpga-mgr = <&fpgamgr0>;
107
108 #address-cells = <0x1>;
109 #size-cells = <0x1>;
110 };
111
112 can0: can@ffc00000 {
113 compatible = "bosch,d_can";
114 reg = <0xffc00000 0x1000>;
115 interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>;
116 clocks = <&can0_clk>;
117 status = "disabled";
118 };
119
120 can1: can@ffc01000 {
121 compatible = "bosch,d_can";
122 reg = <0xffc01000 0x1000>;
123 interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>;
124 clocks = <&can1_clk>;
125 status = "disabled";
126 };
127
128 clkmgr@ffd04000 {
129 compatible = "altr,clk-mgr";
130 reg = <0xffd04000 0x1000>;
131
132 clocks {
133 #address-cells = <1>;
134 #size-cells = <0>;
135
136 osc1: osc1 {
137 #clock-cells = <0>;
138 compatible = "fixed-clock";
139 };
140
141 osc2: osc2 {
142 #clock-cells = <0>;
143 compatible = "fixed-clock";
144 };
145
146 f2s_periph_ref_clk: f2s_periph_ref_clk {
147 #clock-cells = <0>;
148 compatible = "fixed-clock";
149 };
150
151 f2s_sdram_ref_clk: f2s_sdram_ref_clk {
152 #clock-cells = <0>;
153 compatible = "fixed-clock";
154 };
155
156 main_pll: main_pll@40 {
157 #address-cells = <1>;
158 #size-cells = <0>;
159 #clock-cells = <0>;
160 compatible = "altr,socfpga-pll-clock";
161 clocks = <&osc1>;
162 reg = <0x40>;
163
164 mpuclk: mpuclk@48 {
165 #clock-cells = <0>;
166 compatible = "altr,socfpga-perip-clk";
167 clocks = <&main_pll>;
168 div-reg = <0xe0 0 9>;
169 reg = <0x48>;
170 };
171
172 mainclk: mainclk@4c {
173 #clock-cells = <0>;
174 compatible = "altr,socfpga-perip-clk";
175 clocks = <&main_pll>;
176 div-reg = <0xe4 0 9>;
177 reg = <0x4C>;
178 };
179
180 dbg_base_clk: dbg_base_clk@50 {
181 #clock-cells = <0>;
182 compatible = "altr,socfpga-perip-clk";
183 clocks = <&main_pll>, <&osc1>;
184 div-reg = <0xe8 0 9>;
185 reg = <0x50>;
186 };
187
188 main_qspi_clk: main_qspi_clk@54 {
189 #clock-cells = <0>;
190 compatible = "altr,socfpga-perip-clk";
191 clocks = <&main_pll>;
192 reg = <0x54>;
193 };
194
195 main_nand_sdmmc_clk: main_nand_sdmmc_clk@58 {
196 #clock-cells = <0>;
197 compatible = "altr,socfpga-perip-clk";
198 clocks = <&main_pll>;
199 reg = <0x58>;
200 };
201
202 cfg_h2f_usr0_clk: cfg_h2f_usr0_clk@5c {
203 #clock-cells = <0>;
204 compatible = "altr,socfpga-perip-clk";
205 clocks = <&main_pll>;
206 reg = <0x5C>;
207 };
208 };
209
210 periph_pll: periph_pll@80 {
211 #address-cells = <1>;
212 #size-cells = <0>;
213 #clock-cells = <0>;
214 compatible = "altr,socfpga-pll-clock";
215 clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>;
216 reg = <0x80>;
217
218 emac0_clk: emac0_clk@88 {
219 #clock-cells = <0>;
220 compatible = "altr,socfpga-perip-clk";
221 clocks = <&periph_pll>;
222 reg = <0x88>;
223 };
224
225 emac1_clk: emac1_clk@8c {
226 #clock-cells = <0>;
227 compatible = "altr,socfpga-perip-clk";
228 clocks = <&periph_pll>;
229 reg = <0x8C>;
230 };
231
232 per_qspi_clk: per_qsi_clk@90 {
233 #clock-cells = <0>;
234 compatible = "altr,socfpga-perip-clk";
235 clocks = <&periph_pll>;
236 reg = <0x90>;
237 };
238
239 per_nand_mmc_clk: per_nand_mmc_clk@94 {
240 #clock-cells = <0>;
241 compatible = "altr,socfpga-perip-clk";
242 clocks = <&periph_pll>;
243 reg = <0x94>;
244 };
245
246 per_base_clk: per_base_clk@98 {
247 #clock-cells = <0>;
248 compatible = "altr,socfpga-perip-clk";
249 clocks = <&periph_pll>;
250 reg = <0x98>;
251 };
252
253 h2f_usr1_clk: h2f_usr1_clk@9c {
254 #clock-cells = <0>;
255 compatible = "altr,socfpga-perip-clk";
256 clocks = <&periph_pll>;
257 reg = <0x9C>;
258 };
259 };
260
261 sdram_pll: sdram_pll@c0 {
262 #address-cells = <1>;
263 #size-cells = <0>;
264 #clock-cells = <0>;
265 compatible = "altr,socfpga-pll-clock";
266 clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>;
267 reg = <0xC0>;
268
269 ddr_dqs_clk: ddr_dqs_clk@c8 {
270 #clock-cells = <0>;
271 compatible = "altr,socfpga-perip-clk";
272 clocks = <&sdram_pll>;
273 reg = <0xC8>;
274 };
275
276 ddr_2x_dqs_clk: ddr_2x_dqs_clk@cc {
277 #clock-cells = <0>;
278 compatible = "altr,socfpga-perip-clk";
279 clocks = <&sdram_pll>;
280 reg = <0xCC>;
281 };
282
283 ddr_dq_clk: ddr_dq_clk@d0 {
284 #clock-cells = <0>;
285 compatible = "altr,socfpga-perip-clk";
286 clocks = <&sdram_pll>;
287 reg = <0xD0>;
288 };
289
290 h2f_usr2_clk: h2f_usr2_clk@d4 {
291 #clock-cells = <0>;
292 compatible = "altr,socfpga-perip-clk";
293 clocks = <&sdram_pll>;
294 reg = <0xD4>;
295 };
296 };
297
298 mpu_periph_clk: mpu_periph_clk {
299 #clock-cells = <0>;
300 compatible = "altr,socfpga-perip-clk";
301 clocks = <&mpuclk>;
302 fixed-divider = <4>;
303 };
304
305 mpu_l2_ram_clk: mpu_l2_ram_clk {
306 #clock-cells = <0>;
307 compatible = "altr,socfpga-perip-clk";
308 clocks = <&mpuclk>;
309 fixed-divider = <2>;
310 };
311
312 l4_main_clk: l4_main_clk {
313 #clock-cells = <0>;
314 compatible = "altr,socfpga-gate-clk";
315 clocks = <&mainclk>;
316 clk-gate = <0x60 0>;
317 };
318
319 l3_main_clk: l3_main_clk {
320 #clock-cells = <0>;
321 compatible = "altr,socfpga-perip-clk";
322 clocks = <&mainclk>;
323 fixed-divider = <1>;
324 };
325
326 l3_mp_clk: l3_mp_clk {
327 #clock-cells = <0>;
328 compatible = "altr,socfpga-gate-clk";
329 clocks = <&mainclk>;
330 div-reg = <0x64 0 2>;
331 clk-gate = <0x60 1>;
332 };
333
334 l3_sp_clk: l3_sp_clk {
335 #clock-cells = <0>;
336 compatible = "altr,socfpga-gate-clk";
337 clocks = <&l3_mp_clk>;
338 div-reg = <0x64 2 2>;
339 };
340
341 l4_mp_clk: l4_mp_clk {
342 #clock-cells = <0>;
343 compatible = "altr,socfpga-gate-clk";
344 clocks = <&mainclk>, <&per_base_clk>;
345 div-reg = <0x64 4 3>;
346 clk-gate = <0x60 2>;
347 };
348
349 l4_sp_clk: l4_sp_clk {
350 #clock-cells = <0>;
351 compatible = "altr,socfpga-gate-clk";
352 clocks = <&mainclk>, <&per_base_clk>;
353 div-reg = <0x64 7 3>;
354 clk-gate = <0x60 3>;
355 };
356
357 dbg_at_clk: dbg_at_clk {
358 #clock-cells = <0>;
359 compatible = "altr,socfpga-gate-clk";
360 clocks = <&dbg_base_clk>;
361 div-reg = <0x68 0 2>;
362 clk-gate = <0x60 4>;
363 };
364
365 dbg_clk: dbg_clk {
366 #clock-cells = <0>;
367 compatible = "altr,socfpga-gate-clk";
368 clocks = <&dbg_at_clk>;
369 div-reg = <0x68 2 2>;
370 clk-gate = <0x60 5>;
371 };
372
373 dbg_trace_clk: dbg_trace_clk {
374 #clock-cells = <0>;
375 compatible = "altr,socfpga-gate-clk";
376 clocks = <&dbg_base_clk>;
377 div-reg = <0x6C 0 3>;
378 clk-gate = <0x60 6>;
379 };
380
381 dbg_timer_clk: dbg_timer_clk {
382 #clock-cells = <0>;
383 compatible = "altr,socfpga-gate-clk";
384 clocks = <&dbg_base_clk>;
385 clk-gate = <0x60 7>;
386 };
387
388 cfg_clk: cfg_clk {
389 #clock-cells = <0>;
390 compatible = "altr,socfpga-gate-clk";
391 clocks = <&cfg_h2f_usr0_clk>;
392 clk-gate = <0x60 8>;
393 };
394
395 h2f_user0_clk: h2f_user0_clk {
396 #clock-cells = <0>;
397 compatible = "altr,socfpga-gate-clk";
398 clocks = <&cfg_h2f_usr0_clk>;
399 clk-gate = <0x60 9>;
400 };
401
402 emac_0_clk: emac_0_clk {
403 #clock-cells = <0>;
404 compatible = "altr,socfpga-gate-clk";
405 clocks = <&emac0_clk>;
406 clk-gate = <0xa0 0>;
407 };
408
409 emac_1_clk: emac_1_clk {
410 #clock-cells = <0>;
411 compatible = "altr,socfpga-gate-clk";
412 clocks = <&emac1_clk>;
413 clk-gate = <0xa0 1>;
414 };
415
416 usb_mp_clk: usb_mp_clk {
417 #clock-cells = <0>;
418 compatible = "altr,socfpga-gate-clk";
419 clocks = <&per_base_clk>;
420 clk-gate = <0xa0 2>;
421 div-reg = <0xa4 0 3>;
422 };
423
424 spi_m_clk: spi_m_clk {
425 #clock-cells = <0>;
426 compatible = "altr,socfpga-gate-clk";
427 clocks = <&per_base_clk>;
428 clk-gate = <0xa0 3>;
429 div-reg = <0xa4 3 3>;
430 };
431
432 can0_clk: can0_clk {
433 #clock-cells = <0>;
434 compatible = "altr,socfpga-gate-clk";
435 clocks = <&per_base_clk>;
436 clk-gate = <0xa0 4>;
437 div-reg = <0xa4 6 3>;
438 };
439
440 can1_clk: can1_clk {
441 #clock-cells = <0>;
442 compatible = "altr,socfpga-gate-clk";
443 clocks = <&per_base_clk>;
444 clk-gate = <0xa0 5>;
445 div-reg = <0xa4 9 3>;
446 };
447
448 gpio_db_clk: gpio_db_clk {
449 #clock-cells = <0>;
450 compatible = "altr,socfpga-gate-clk";
451 clocks = <&per_base_clk>;
452 clk-gate = <0xa0 6>;
453 div-reg = <0xa8 0 24>;
454 };
455
456 h2f_user1_clk: h2f_user1_clk {
457 #clock-cells = <0>;
458 compatible = "altr,socfpga-gate-clk";
459 clocks = <&h2f_usr1_clk>;
460 clk-gate = <0xa0 7>;
461 };
462
463 sdmmc_clk: sdmmc_clk {
464 #clock-cells = <0>;
465 compatible = "altr,socfpga-gate-clk";
466 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
467 clk-gate = <0xa0 8>;
468 clk-phase = <0 135>;
469 };
470
471 sdmmc_clk_divided: sdmmc_clk_divided {
472 #clock-cells = <0>;
473 compatible = "altr,socfpga-gate-clk";
474 clocks = <&sdmmc_clk>;
475 clk-gate = <0xa0 8>;
476 fixed-divider = <4>;
477 };
478
479 nand_x_clk: nand_x_clk {
480 #clock-cells = <0>;
481 compatible = "altr,socfpga-gate-clk";
482 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
483 clk-gate = <0xa0 9>;
484 };
485
486 nand_clk: nand_clk {
487 #clock-cells = <0>;
488 compatible = "altr,socfpga-gate-clk";
489 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
490 clk-gate = <0xa0 10>;
491 fixed-divider = <4>;
492 };
493
494 qspi_clk: qspi_clk {
495 #clock-cells = <0>;
496 compatible = "altr,socfpga-gate-clk";
497 clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;
498 clk-gate = <0xa0 11>;
499 };
500
501 ddr_dqs_clk_gate: ddr_dqs_clk_gate {
502 #clock-cells = <0>;
503 compatible = "altr,socfpga-gate-clk";
504 clocks = <&ddr_dqs_clk>;
505 clk-gate = <0xd8 0>;
506 };
507
508 ddr_2x_dqs_clk_gate: ddr_2x_dqs_clk_gate {
509 #clock-cells = <0>;
510 compatible = "altr,socfpga-gate-clk";
511 clocks = <&ddr_2x_dqs_clk>;
512 clk-gate = <0xd8 1>;
513 };
514
515 ddr_dq_clk_gate: ddr_dq_clk_gate {
516 #clock-cells = <0>;
517 compatible = "altr,socfpga-gate-clk";
518 clocks = <&ddr_dq_clk>;
519 clk-gate = <0xd8 2>;
520 };
521
522 h2f_user2_clk: h2f_user2_clk {
523 #clock-cells = <0>;
524 compatible = "altr,socfpga-gate-clk";
525 clocks = <&h2f_usr2_clk>;
526 clk-gate = <0xd8 3>;
527 };
528
529 };
530 };
531
532 fpga_bridge0: fpga_bridge@ff400000 {
533 compatible = "altr,socfpga-lwhps2fpga-bridge";
534 reg = <0xff400000 0x100000>;
535 resets = <&rst LWHPS2FPGA_RESET>;
536 clocks = <&l4_main_clk>;
537 };
538
539 fpga_bridge1: fpga_bridge@ff500000 {
540 compatible = "altr,socfpga-hps2fpga-bridge";
541 reg = <0xff500000 0x10000>;
542 resets = <&rst HPS2FPGA_RESET>;
543 clocks = <&l4_main_clk>;
544 };
545
546 fpgamgr0: fpgamgr@ff706000 {
547 compatible = "altr,socfpga-fpga-mgr";
548 reg = <0xff706000 0x1000
549 0xffb90000 0x4>;
550 interrupts = <0 175 4>;
551 };
552
553 gmac0: ethernet@ff700000 {
554 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
555 altr,sysmgr-syscon = <&sysmgr 0x60 0>;
556 reg = <0xff700000 0x2000>;
557 interrupts = <0 115 4>;
558 interrupt-names = "macirq";
559 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
560 clocks = <&emac_0_clk>;
561 clock-names = "stmmaceth";
562 resets = <&rst EMAC0_RESET>;
563 reset-names = "stmmaceth";
564 snps,multicast-filter-bins = <256>;
565 snps,perfect-filter-entries = <128>;
566 tx-fifo-depth = <4096>;
567 rx-fifo-depth = <4096>;
568 status = "disabled";
569 };
570
571 gmac1: ethernet@ff702000 {
572 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
573 altr,sysmgr-syscon = <&sysmgr 0x60 2>;
574 reg = <0xff702000 0x2000>;
575 interrupts = <0 120 4>;
576 interrupt-names = "macirq";
577 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
578 clocks = <&emac_1_clk>;
579 clock-names = "stmmaceth";
580 resets = <&rst EMAC1_RESET>;
581 reset-names = "stmmaceth";
582 snps,multicast-filter-bins = <256>;
583 snps,perfect-filter-entries = <128>;
584 tx-fifo-depth = <4096>;
585 rx-fifo-depth = <4096>;
586 status = "disabled";
587 };
588
589 gpio0: gpio@ff708000 {
590 #address-cells = <1>;
591 #size-cells = <0>;
592 compatible = "snps,dw-apb-gpio";
593 reg = <0xff708000 0x1000>;
594 clocks = <&l4_mp_clk>;
595 status = "disabled";
596
597 porta: gpio-controller@0 {
598 compatible = "snps,dw-apb-gpio-port";
599 gpio-controller;
600 #gpio-cells = <2>;
601 snps,nr-gpios = <29>;
602 reg = <0>;
603 interrupt-controller;
604 #interrupt-cells = <2>;
605 interrupts = <0 164 4>;
606 };
607 };
608
609 gpio1: gpio@ff709000 {
610 #address-cells = <1>;
611 #size-cells = <0>;
612 compatible = "snps,dw-apb-gpio";
613 reg = <0xff709000 0x1000>;
614 clocks = <&l4_mp_clk>;
615 status = "disabled";
616
617 portb: gpio-controller@0 {
618 compatible = "snps,dw-apb-gpio-port";
619 gpio-controller;
620 #gpio-cells = <2>;
621 snps,nr-gpios = <29>;
622 reg = <0>;
623 interrupt-controller;
624 #interrupt-cells = <2>;
625 interrupts = <0 165 4>;
626 };
627 };
628
629 gpio2: gpio@ff70a000 {
630 #address-cells = <1>;
631 #size-cells = <0>;
632 compatible = "snps,dw-apb-gpio";
633 reg = <0xff70a000 0x1000>;
634 clocks = <&l4_mp_clk>;
635 status = "disabled";
636
637 portc: gpio-controller@0 {
638 compatible = "snps,dw-apb-gpio-port";
639 gpio-controller;
640 #gpio-cells = <2>;
641 snps,nr-gpios = <27>;
642 reg = <0>;
643 interrupt-controller;
644 #interrupt-cells = <2>;
645 interrupts = <0 166 4>;
646 };
647 };
648
649 i2c0: i2c@ffc04000 {
650 #address-cells = <1>;
651 #size-cells = <0>;
652 compatible = "snps,designware-i2c";
653 reg = <0xffc04000 0x1000>;
654 resets = <&rst I2C0_RESET>;
655 clocks = <&l4_sp_clk>;
656 interrupts = <0 158 0x4>;
657 status = "disabled";
658 };
659
660 i2c1: i2c@ffc05000 {
661 #address-cells = <1>;
662 #size-cells = <0>;
663 compatible = "snps,designware-i2c";
664 reg = <0xffc05000 0x1000>;
665 resets = <&rst I2C1_RESET>;
666 clocks = <&l4_sp_clk>;
667 interrupts = <0 159 0x4>;
668 status = "disabled";
669 };
670
671 i2c2: i2c@ffc06000 {
672 #address-cells = <1>;
673 #size-cells = <0>;
674 compatible = "snps,designware-i2c";
675 reg = <0xffc06000 0x1000>;
676 resets = <&rst I2C2_RESET>;
677 clocks = <&l4_sp_clk>;
678 interrupts = <0 160 0x4>;
679 status = "disabled";
680 };
681
682 i2c3: i2c@ffc07000 {
683 #address-cells = <1>;
684 #size-cells = <0>;
685 compatible = "snps,designware-i2c";
686 reg = <0xffc07000 0x1000>;
687 resets = <&rst I2C3_RESET>;
688 clocks = <&l4_sp_clk>;
689 interrupts = <0 161 0x4>;
690 status = "disabled";
691 };
692
693 eccmgr: eccmgr {
694 compatible = "altr,socfpga-ecc-manager";
695 #address-cells = <1>;
696 #size-cells = <1>;
697 ranges;
698
699 l2-ecc@ffd08140 {
700 compatible = "altr,socfpga-l2-ecc";
701 reg = <0xffd08140 0x4>;
702 interrupts = <0 36 1>, <0 37 1>;
703 };
704
705 ocram-ecc@ffd08144 {
706 compatible = "altr,socfpga-ocram-ecc";
707 reg = <0xffd08144 0x4>;
708 iram = <&ocram>;
709 interrupts = <0 178 1>, <0 179 1>;
710 };
711 };
712
713 L2: l2-cache@fffef000 {
714 compatible = "arm,pl310-cache";
715 reg = <0xfffef000 0x1000>;
716 interrupts = <0 38 0x04>;
717 cache-unified;
718 cache-level = <2>;
719 arm,tag-latency = <1 1 1>;
720 arm,data-latency = <2 1 1>;
721 prefetch-data = <1>;
722 prefetch-instr = <1>;
723 arm,shared-override;
724 arm,double-linefill = <1>;
725 arm,double-linefill-incr = <0>;
726 arm,double-linefill-wrap = <1>;
727 arm,prefetch-drop = <0>;
728 arm,prefetch-offset = <7>;
729 };
730
731 l3regs@0xff800000 {
732 compatible = "altr,l3regs", "syscon";
733 reg = <0xff800000 0x1000>;
734 };
735
736 mmc: dwmmc0@ff704000 {
737 compatible = "altr,socfpga-dw-mshc";
738 reg = <0xff704000 0x1000>;
739 interrupts = <0 139 4>;
740 fifo-depth = <0x400>;
741 #address-cells = <1>;
742 #size-cells = <0>;
743 clocks = <&l4_mp_clk>, <&sdmmc_clk_divided>;
744 clock-names = "biu", "ciu";
745 status = "disabled";
746 };
747
748 nand0: nand@ff900000 {
749 #address-cells = <0x1>;
750 #size-cells = <0x1>;
751 compatible = "denali,denali-nand-dt";
752 reg = <0xff900000 0x100000>,
753 <0xffb80000 0x10000>;
754 reg-names = "nand_data", "denali_reg";
755 interrupts = <0x0 0x90 0x4>;
756 dma-mask = <0xffffffff>;
757 clocks = <&nand_clk>;
758 status = "disabled";
759 };
760
761 ocram: sram@ffff0000 {
762 compatible = "mmio-sram";
763 reg = <0xffff0000 0x10000>;
764 };
765
766 qspi: spi@ff705000 {
767 compatible = "cdns,qspi-nor";
768 #address-cells = <1>;
769 #size-cells = <0>;
770 reg = <0xff705000 0x1000>,
771 <0xffa00000 0x1000>;
772 interrupts = <0 151 4>;
773 cdns,fifo-depth = <128>;
774 cdns,fifo-width = <4>;
775 cdns,trigger-address = <0x00000000>;
776 clocks = <&qspi_clk>;
777 status = "disabled";
778 };
779
780 rst: rstmgr@ffd05000 {
781 #reset-cells = <1>;
782 compatible = "altr,rst-mgr";
783 reg = <0xffd05000 0x1000>;
784 altr,modrst-offset = <0x10>;
785 };
786
787 scu: snoop-control-unit@fffec000 {
788 compatible = "arm,cortex-a9-scu";
789 reg = <0xfffec000 0x100>;
790 };
791
792 sdr: sdr@ffc25000 {
793 compatible = "altr,sdr-ctl", "syscon";
794 reg = <0xffc25000 0x1000>;
795 };
796
797 sdramedac {
798 compatible = "altr,sdram-edac";
799 altr,sdr-syscon = <&sdr>;
800 interrupts = <0 39 4>;
801 };
802
803 spi0: spi@fff00000 {
804 compatible = "snps,dw-apb-ssi";
805 #address-cells = <1>;
806 #size-cells = <0>;
807 reg = <0xfff00000 0x1000>;
808 interrupts = <0 154 4>;
809 num-cs = <4>;
810 clocks = <&spi_m_clk>;
811 status = "disabled";
812 };
813
814 spi1: spi@fff01000 {
815 compatible = "snps,dw-apb-ssi";
816 #address-cells = <1>;
817 #size-cells = <0>;
818 reg = <0xfff01000 0x1000>;
819 interrupts = <0 155 4>;
820 num-cs = <4>;
821 clocks = <&spi_m_clk>;
822 status = "disabled";
823 };
824
825 sysmgr: sysmgr@ffd08000 {
826 compatible = "altr,sys-mgr", "syscon";
827 reg = <0xffd08000 0x4000>;
828 };
829
830 /* Local timer */
831 timer@fffec600 {
832 compatible = "arm,cortex-a9-twd-timer";
833 reg = <0xfffec600 0x100>;
834 interrupts = <1 13 0xf01>;
835 clocks = <&mpu_periph_clk>;
836 };
837
838 timer0: timer0@ffc08000 {
839 compatible = "snps,dw-apb-timer";
840 interrupts = <0 167 4>;
841 reg = <0xffc08000 0x1000>;
842 clocks = <&l4_sp_clk>;
843 clock-names = "timer";
844 };
845
846 timer1: timer1@ffc09000 {
847 compatible = "snps,dw-apb-timer";
848 interrupts = <0 168 4>;
849 reg = <0xffc09000 0x1000>;
850 clocks = <&l4_sp_clk>;
851 clock-names = "timer";
852 };
853
854 timer2: timer2@ffd00000 {
855 compatible = "snps,dw-apb-timer";
856 interrupts = <0 169 4>;
857 reg = <0xffd00000 0x1000>;
858 clocks = <&osc1>;
859 clock-names = "timer";
860 };
861
862 timer3: timer3@ffd01000 {
863 compatible = "snps,dw-apb-timer";
864 interrupts = <0 170 4>;
865 reg = <0xffd01000 0x1000>;
866 clocks = <&osc1>;
867 clock-names = "timer";
868 };
869
870 uart0: serial0@ffc02000 {
871 compatible = "snps,dw-apb-uart";
872 reg = <0xffc02000 0x1000>;
873 interrupts = <0 162 4>;
874 reg-shift = <2>;
875 reg-io-width = <4>;
876 clocks = <&l4_sp_clk>;
877 dmas = <&pdma 28>,
878 <&pdma 29>;
879 dma-names = "tx", "rx";
880 };
881
882 uart1: serial1@ffc03000 {
883 compatible = "snps,dw-apb-uart";
884 reg = <0xffc03000 0x1000>;
885 interrupts = <0 163 4>;
886 reg-shift = <2>;
887 reg-io-width = <4>;
888 clocks = <&l4_sp_clk>;
889 dmas = <&pdma 30>,
890 <&pdma 31>;
891 dma-names = "tx", "rx";
892 };
893
894 usbphy0: usbphy {
895 #phy-cells = <0>;
896 compatible = "usb-nop-xceiv";
897 status = "okay";
898 };
899
900 usb0: usb@ffb00000 {
901 compatible = "snps,dwc2";
902 reg = <0xffb00000 0xffff>;
903 interrupts = <0 125 4>;
904 clocks = <&usb_mp_clk>;
905 clock-names = "otg";
906 resets = <&rst USB0_RESET>;
907 reset-names = "dwc2";
908 phys = <&usbphy0>;
909 phy-names = "usb2-phy";
910 status = "disabled";
911 };
912
913 usb1: usb@ffb40000 {
914 compatible = "snps,dwc2";
915 reg = <0xffb40000 0xffff>;
916 interrupts = <0 128 4>;
917 clocks = <&usb_mp_clk>;
918 clock-names = "otg";
919 resets = <&rst USB1_RESET>;
920 reset-names = "dwc2";
921 phys = <&usbphy0>;
922 phy-names = "usb2-phy";
923 status = "disabled";
924 };
925
926 watchdog0: watchdog@ffd02000 {
927 compatible = "snps,dw-wdt";
928 reg = <0xffd02000 0x1000>;
929 interrupts = <0 171 4>;
930 clocks = <&osc1>;
931 status = "disabled";
932 };
933
934 watchdog1: watchdog@ffd03000 {
935 compatible = "snps,dw-wdt";
936 reg = <0xffd03000 0x1000>;
937 interrupts = <0 172 4>;
938 clocks = <&osc1>;
939 status = "disabled";
940 };
941 };
942 };
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