2 * Copyright (C) 2012 Altera <www.altera.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 /include/ "skeleton.dtsi"
40 compatible = "arm,cortex-a9";
43 next-level-cache = <&L2>;
46 compatible = "arm,cortex-a9";
49 next-level-cache = <&L2>;
54 compatible = "arm,cortex-a9-gic";
55 #interrupt-cells = <3>;
57 reg = <0xfffed000 0x1000>,
64 compatible = "simple-bus";
66 interrupt-parent = <&intc>;
70 compatible = "arm,amba-bus";
76 compatible = "arm,pl330", "arm,primecell";
77 reg = <0xffe01000 0x1000>;
78 interrupts = <0 180 4>;
82 clocks = <&l4_main_clk>;
83 clock-names = "apb_pclk";
88 compatible = "altr,clk-mgr";
89 reg = <0xffd04000 0x1000>;
97 compatible = "fixed-clock";
102 compatible = "fixed-clock";
105 f2s_periph_ref_clk: f2s_periph_ref_clk {
107 compatible = "fixed-clock";
110 f2s_sdram_ref_clk: f2s_sdram_ref_clk {
112 compatible = "fixed-clock";
116 #address-cells = <1>;
119 compatible = "altr,socfpga-pll-clock";
125 compatible = "altr,socfpga-perip-clk";
126 clocks = <&main_pll>;
133 compatible = "altr,socfpga-perip-clk";
134 clocks = <&main_pll>;
139 dbg_base_clk: dbg_base_clk {
141 compatible = "altr,socfpga-perip-clk";
142 clocks = <&main_pll>;
147 main_qspi_clk: main_qspi_clk {
149 compatible = "altr,socfpga-perip-clk";
150 clocks = <&main_pll>;
154 main_nand_sdmmc_clk: main_nand_sdmmc_clk {
156 compatible = "altr,socfpga-perip-clk";
157 clocks = <&main_pll>;
161 cfg_h2f_usr0_clk: cfg_h2f_usr0_clk {
163 compatible = "altr,socfpga-perip-clk";
164 clocks = <&main_pll>;
169 periph_pll: periph_pll {
170 #address-cells = <1>;
173 compatible = "altr,socfpga-pll-clock";
174 clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>;
177 emac0_clk: emac0_clk {
179 compatible = "altr,socfpga-perip-clk";
180 clocks = <&periph_pll>;
184 emac1_clk: emac1_clk {
186 compatible = "altr,socfpga-perip-clk";
187 clocks = <&periph_pll>;
191 per_qspi_clk: per_qsi_clk {
193 compatible = "altr,socfpga-perip-clk";
194 clocks = <&periph_pll>;
198 per_nand_mmc_clk: per_nand_mmc_clk {
200 compatible = "altr,socfpga-perip-clk";
201 clocks = <&periph_pll>;
205 per_base_clk: per_base_clk {
207 compatible = "altr,socfpga-perip-clk";
208 clocks = <&periph_pll>;
212 h2f_usr1_clk: h2f_usr1_clk {
214 compatible = "altr,socfpga-perip-clk";
215 clocks = <&periph_pll>;
220 sdram_pll: sdram_pll {
221 #address-cells = <1>;
224 compatible = "altr,socfpga-pll-clock";
225 clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>;
228 ddr_dqs_clk: ddr_dqs_clk {
230 compatible = "altr,socfpga-perip-clk";
231 clocks = <&sdram_pll>;
235 ddr_2x_dqs_clk: ddr_2x_dqs_clk {
237 compatible = "altr,socfpga-perip-clk";
238 clocks = <&sdram_pll>;
242 ddr_dq_clk: ddr_dq_clk {
244 compatible = "altr,socfpga-perip-clk";
245 clocks = <&sdram_pll>;
249 h2f_usr2_clk: h2f_usr2_clk {
251 compatible = "altr,socfpga-perip-clk";
252 clocks = <&sdram_pll>;
257 mpu_periph_clk: mpu_periph_clk {
259 compatible = "altr,socfpga-perip-clk";
264 mpu_l2_ram_clk: mpu_l2_ram_clk {
266 compatible = "altr,socfpga-perip-clk";
271 l4_main_clk: l4_main_clk {
273 compatible = "altr,socfpga-gate-clk";
278 l3_main_clk: l3_main_clk {
280 compatible = "altr,socfpga-perip-clk";
285 l3_mp_clk: l3_mp_clk {
287 compatible = "altr,socfpga-gate-clk";
289 div-reg = <0x64 0 2>;
293 l3_sp_clk: l3_sp_clk {
295 compatible = "altr,socfpga-gate-clk";
297 div-reg = <0x64 2 2>;
300 l4_mp_clk: l4_mp_clk {
302 compatible = "altr,socfpga-gate-clk";
303 clocks = <&mainclk>, <&per_base_clk>;
304 div-reg = <0x64 4 3>;
308 l4_sp_clk: l4_sp_clk {
310 compatible = "altr,socfpga-gate-clk";
311 clocks = <&mainclk>, <&per_base_clk>;
312 div-reg = <0x64 7 3>;
316 dbg_at_clk: dbg_at_clk {
318 compatible = "altr,socfpga-gate-clk";
319 clocks = <&dbg_base_clk>;
320 div-reg = <0x68 0 2>;
326 compatible = "altr,socfpga-gate-clk";
327 clocks = <&dbg_base_clk>;
328 div-reg = <0x68 2 2>;
332 dbg_trace_clk: dbg_trace_clk {
334 compatible = "altr,socfpga-gate-clk";
335 clocks = <&dbg_base_clk>;
336 div-reg = <0x6C 0 3>;
340 dbg_timer_clk: dbg_timer_clk {
342 compatible = "altr,socfpga-gate-clk";
343 clocks = <&dbg_base_clk>;
349 compatible = "altr,socfpga-gate-clk";
350 clocks = <&cfg_h2f_usr0_clk>;
354 h2f_user0_clk: h2f_user0_clk {
356 compatible = "altr,socfpga-gate-clk";
357 clocks = <&cfg_h2f_usr0_clk>;
361 emac_0_clk: emac_0_clk {
363 compatible = "altr,socfpga-gate-clk";
364 clocks = <&emac0_clk>;
368 emac_1_clk: emac_1_clk {
370 compatible = "altr,socfpga-gate-clk";
371 clocks = <&emac1_clk>;
375 usb_mp_clk: usb_mp_clk {
377 compatible = "altr,socfpga-gate-clk";
378 clocks = <&per_base_clk>;
380 div-reg = <0xa4 0 3>;
383 spi_m_clk: spi_m_clk {
385 compatible = "altr,socfpga-gate-clk";
386 clocks = <&per_base_clk>;
388 div-reg = <0xa4 3 3>;
393 compatible = "altr,socfpga-gate-clk";
394 clocks = <&per_base_clk>;
396 div-reg = <0xa4 6 3>;
401 compatible = "altr,socfpga-gate-clk";
402 clocks = <&per_base_clk>;
404 div-reg = <0xa4 9 3>;
407 gpio_db_clk: gpio_db_clk {
409 compatible = "altr,socfpga-gate-clk";
410 clocks = <&per_base_clk>;
412 div-reg = <0xa8 0 24>;
415 h2f_user1_clk: h2f_user1_clk {
417 compatible = "altr,socfpga-gate-clk";
418 clocks = <&h2f_usr1_clk>;
422 sdmmc_clk: sdmmc_clk {
424 compatible = "altr,socfpga-gate-clk";
425 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
430 nand_x_clk: nand_x_clk {
432 compatible = "altr,socfpga-gate-clk";
433 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
439 compatible = "altr,socfpga-gate-clk";
440 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
441 clk-gate = <0xa0 10>;
447 compatible = "altr,socfpga-gate-clk";
448 clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;
449 clk-gate = <0xa0 11>;
454 gmac0: ethernet@ff700000 {
455 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
456 altr,sysmgr-syscon = <&sysmgr 0x60 0>;
457 reg = <0xff700000 0x2000>;
458 interrupts = <0 115 4>;
459 interrupt-names = "macirq";
460 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
461 clocks = <&emac0_clk>;
462 clock-names = "stmmaceth";
466 gmac1: ethernet@ff702000 {
467 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
468 altr,sysmgr-syscon = <&sysmgr 0x60 2>;
469 reg = <0xff702000 0x2000>;
470 interrupts = <0 120 4>;
471 interrupt-names = "macirq";
472 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
473 clocks = <&emac1_clk>;
474 clock-names = "stmmaceth";
478 L2: l2-cache@fffef000 {
479 compatible = "arm,pl310-cache";
480 reg = <0xfffef000 0x1000>;
481 interrupts = <0 38 0x04>;
484 arm,tag-latency = <1 1 1>;
485 arm,data-latency = <2 1 1>;
488 mmc: dwmmc0@ff704000 {
489 compatible = "altr,socfpga-dw-mshc";
490 reg = <0xff704000 0x1000>;
491 interrupts = <0 139 4>;
492 fifo-depth = <0x400>;
493 #address-cells = <1>;
495 clocks = <&l4_mp_clk>, <&sdmmc_clk>;
496 clock-names = "biu", "ciu";
501 compatible = "arm,cortex-a9-twd-timer";
502 reg = <0xfffec600 0x100>;
503 interrupts = <1 13 0xf04>;
504 clocks = <&mpu_periph_clk>;
507 timer0: timer0@ffc08000 {
508 compatible = "snps,dw-apb-timer";
509 interrupts = <0 167 4>;
510 reg = <0xffc08000 0x1000>;
513 timer1: timer1@ffc09000 {
514 compatible = "snps,dw-apb-timer";
515 interrupts = <0 168 4>;
516 reg = <0xffc09000 0x1000>;
519 timer2: timer2@ffd00000 {
520 compatible = "snps,dw-apb-timer";
521 interrupts = <0 169 4>;
522 reg = <0xffd00000 0x1000>;
525 timer3: timer3@ffd01000 {
526 compatible = "snps,dw-apb-timer";
527 interrupts = <0 170 4>;
528 reg = <0xffd01000 0x1000>;
531 uart0: serial0@ffc02000 {
532 compatible = "snps,dw-apb-uart";
533 reg = <0xffc02000 0x1000>;
534 interrupts = <0 162 4>;
539 uart1: serial1@ffc03000 {
540 compatible = "snps,dw-apb-uart";
541 reg = <0xffc03000 0x1000>;
542 interrupts = <0 163 4>;
548 compatible = "altr,rst-mgr";
549 reg = <0xffd05000 0x1000>;
552 sysmgr: sysmgr@ffd08000 {
553 compatible = "altr,sys-mgr", "syscon";
554 reg = <0xffd08000 0x4000>;