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[mirror_ubuntu-hirsute-kernel.git] / arch / arm / boot / dts / socfpga_arria10.dtsi
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright Altera Corporation (C) 2014. All rights reserved.
4 */
5
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
8
9 / {
10 #address-cells = <1>;
11 #size-cells = <1>;
12
13 cpus {
14 #address-cells = <1>;
15 #size-cells = <0>;
16 enable-method = "altr,socfpga-a10-smp";
17
18 cpu@0 {
19 compatible = "arm,cortex-a9";
20 device_type = "cpu";
21 reg = <0>;
22 next-level-cache = <&L2>;
23 };
24 cpu@1 {
25 compatible = "arm,cortex-a9";
26 device_type = "cpu";
27 reg = <1>;
28 next-level-cache = <&L2>;
29 };
30 };
31
32 intc: intc@ffffd000 {
33 compatible = "arm,cortex-a9-gic";
34 #interrupt-cells = <3>;
35 interrupt-controller;
36 reg = <0xffffd000 0x1000>,
37 <0xffffc100 0x100>;
38 };
39
40 soc {
41 #address-cells = <1>;
42 #size-cells = <1>;
43 compatible = "simple-bus";
44 device_type = "soc";
45 interrupt-parent = <&intc>;
46 ranges;
47
48 amba {
49 compatible = "simple-bus";
50 #address-cells = <1>;
51 #size-cells = <1>;
52 ranges;
53
54 pdma: pdma@ffda1000 {
55 compatible = "arm,pl330", "arm,primecell";
56 reg = <0xffda1000 0x1000>;
57 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>,
58 <0 84 IRQ_TYPE_LEVEL_HIGH>,
59 <0 85 IRQ_TYPE_LEVEL_HIGH>,
60 <0 86 IRQ_TYPE_LEVEL_HIGH>,
61 <0 87 IRQ_TYPE_LEVEL_HIGH>,
62 <0 88 IRQ_TYPE_LEVEL_HIGH>,
63 <0 89 IRQ_TYPE_LEVEL_HIGH>,
64 <0 90 IRQ_TYPE_LEVEL_HIGH>,
65 <0 91 IRQ_TYPE_LEVEL_HIGH>;
66 #dma-cells = <1>;
67 #dma-channels = <8>;
68 #dma-requests = <32>;
69 clocks = <&l4_main_clk>;
70 clock-names = "apb_pclk";
71 resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>;
72 reset-names = "dma", "dma-ocp";
73 };
74 };
75
76 base_fpga_region {
77 #address-cells = <0x1>;
78 #size-cells = <0x1>;
79
80 compatible = "fpga-region";
81 fpga-mgr = <&fpga_mgr>;
82 };
83
84 clkmgr@ffd04000 {
85 compatible = "altr,clk-mgr";
86 reg = <0xffd04000 0x1000>;
87
88 clocks {
89 #address-cells = <1>;
90 #size-cells = <0>;
91
92 cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk {
93 #clock-cells = <0>;
94 compatible = "fixed-clock";
95 };
96
97 cb_intosc_ls_clk: cb_intosc_ls_clk {
98 #clock-cells = <0>;
99 compatible = "fixed-clock";
100 };
101
102 f2s_free_clk: f2s_free_clk {
103 #clock-cells = <0>;
104 compatible = "fixed-clock";
105 };
106
107 osc1: osc1 {
108 #clock-cells = <0>;
109 compatible = "fixed-clock";
110 };
111
112 main_pll: main_pll@40 {
113 #address-cells = <1>;
114 #size-cells = <0>;
115 #clock-cells = <0>;
116 compatible = "altr,socfpga-a10-pll-clock";
117 clocks = <&osc1>, <&cb_intosc_ls_clk>,
118 <&f2s_free_clk>;
119 reg = <0x40>;
120
121 main_mpu_base_clk: main_mpu_base_clk {
122 #clock-cells = <0>;
123 compatible = "altr,socfpga-a10-perip-clk";
124 clocks = <&main_pll>;
125 div-reg = <0x140 0 11>;
126 };
127
128 main_noc_base_clk: main_noc_base_clk {
129 #clock-cells = <0>;
130 compatible = "altr,socfpga-a10-perip-clk";
131 clocks = <&main_pll>;
132 div-reg = <0x144 0 11>;
133 };
134
135 main_emaca_clk: main_emaca_clk@68 {
136 #clock-cells = <0>;
137 compatible = "altr,socfpga-a10-perip-clk";
138 clocks = <&main_pll>;
139 reg = <0x68>;
140 };
141
142 main_emacb_clk: main_emacb_clk@6c {
143 #clock-cells = <0>;
144 compatible = "altr,socfpga-a10-perip-clk";
145 clocks = <&main_pll>;
146 reg = <0x6C>;
147 };
148
149 main_emac_ptp_clk: main_emac_ptp_clk@70 {
150 #clock-cells = <0>;
151 compatible = "altr,socfpga-a10-perip-clk";
152 clocks = <&main_pll>;
153 reg = <0x70>;
154 };
155
156 main_gpio_db_clk: main_gpio_db_clk@74 {
157 #clock-cells = <0>;
158 compatible = "altr,socfpga-a10-perip-clk";
159 clocks = <&main_pll>;
160 reg = <0x74>;
161 };
162
163 main_sdmmc_clk: main_sdmmc_clk@78 {
164 #clock-cells = <0>;
165 compatible = "altr,socfpga-a10-perip-clk"
166 ;
167 clocks = <&main_pll>;
168 reg = <0x78>;
169 };
170
171 main_s2f_usr0_clk: main_s2f_usr0_clk@7c {
172 #clock-cells = <0>;
173 compatible = "altr,socfpga-a10-perip-clk";
174 clocks = <&main_pll>;
175 reg = <0x7C>;
176 };
177
178 main_s2f_usr1_clk: main_s2f_usr1_clk@80 {
179 #clock-cells = <0>;
180 compatible = "altr,socfpga-a10-perip-clk";
181 clocks = <&main_pll>;
182 reg = <0x80>;
183 };
184
185 main_hmc_pll_ref_clk: main_hmc_pll_ref_clk@84 {
186 #clock-cells = <0>;
187 compatible = "altr,socfpga-a10-perip-clk";
188 clocks = <&main_pll>;
189 reg = <0x84>;
190 };
191
192 main_periph_ref_clk: main_periph_ref_clk@9c {
193 #clock-cells = <0>;
194 compatible = "altr,socfpga-a10-perip-clk";
195 clocks = <&main_pll>;
196 reg = <0x9C>;
197 };
198 };
199
200 periph_pll: periph_pll@c0 {
201 #address-cells = <1>;
202 #size-cells = <0>;
203 #clock-cells = <0>;
204 compatible = "altr,socfpga-a10-pll-clock";
205 clocks = <&osc1>, <&cb_intosc_ls_clk>,
206 <&f2s_free_clk>, <&main_periph_ref_clk>;
207 reg = <0xC0>;
208
209 peri_mpu_base_clk: peri_mpu_base_clk {
210 #clock-cells = <0>;
211 compatible = "altr,socfpga-a10-perip-clk";
212 clocks = <&periph_pll>;
213 div-reg = <0x140 16 11>;
214 };
215
216 peri_noc_base_clk: peri_noc_base_clk {
217 #clock-cells = <0>;
218 compatible = "altr,socfpga-a10-perip-clk";
219 clocks = <&periph_pll>;
220 div-reg = <0x144 16 11>;
221 };
222
223 peri_emaca_clk: peri_emaca_clk@e8 {
224 #clock-cells = <0>;
225 compatible = "altr,socfpga-a10-perip-clk";
226 clocks = <&periph_pll>;
227 reg = <0xE8>;
228 };
229
230 peri_emacb_clk: peri_emacb_clk@ec {
231 #clock-cells = <0>;
232 compatible = "altr,socfpga-a10-perip-clk";
233 clocks = <&periph_pll>;
234 reg = <0xEC>;
235 };
236
237 peri_emac_ptp_clk: peri_emac_ptp_clk@f0 {
238 #clock-cells = <0>;
239 compatible = "altr,socfpga-a10-perip-clk";
240 clocks = <&periph_pll>;
241 reg = <0xF0>;
242 };
243
244 peri_gpio_db_clk: peri_gpio_db_clk@f4 {
245 #clock-cells = <0>;
246 compatible = "altr,socfpga-a10-perip-clk";
247 clocks = <&periph_pll>;
248 reg = <0xF4>;
249 };
250
251 peri_sdmmc_clk: peri_sdmmc_clk@f8 {
252 #clock-cells = <0>;
253 compatible = "altr,socfpga-a10-perip-clk";
254 clocks = <&periph_pll>;
255 reg = <0xF8>;
256 };
257
258 peri_s2f_usr0_clk: peri_s2f_usr0_clk@fc {
259 #clock-cells = <0>;
260 compatible = "altr,socfpga-a10-perip-clk";
261 clocks = <&periph_pll>;
262 reg = <0xFC>;
263 };
264
265 peri_s2f_usr1_clk: peri_s2f_usr1_clk@100 {
266 #clock-cells = <0>;
267 compatible = "altr,socfpga-a10-perip-clk";
268 clocks = <&periph_pll>;
269 reg = <0x100>;
270 };
271
272 peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk@104 {
273 #clock-cells = <0>;
274 compatible = "altr,socfpga-a10-perip-clk";
275 clocks = <&periph_pll>;
276 reg = <0x104>;
277 };
278 };
279
280 mpu_free_clk: mpu_free_clk@60 {
281 #clock-cells = <0>;
282 compatible = "altr,socfpga-a10-perip-clk";
283 clocks = <&main_mpu_base_clk>, <&peri_mpu_base_clk>,
284 <&osc1>, <&cb_intosc_hs_div2_clk>,
285 <&f2s_free_clk>;
286 reg = <0x60>;
287 };
288
289 noc_free_clk: noc_free_clk@64 {
290 #clock-cells = <0>;
291 compatible = "altr,socfpga-a10-perip-clk";
292 clocks = <&main_noc_base_clk>, <&peri_noc_base_clk>,
293 <&osc1>, <&cb_intosc_hs_div2_clk>,
294 <&f2s_free_clk>;
295 reg = <0x64>;
296 };
297
298 s2f_user1_free_clk: s2f_user1_free_clk@104 {
299 #clock-cells = <0>;
300 compatible = "altr,socfpga-a10-perip-clk";
301 clocks = <&main_s2f_usr1_clk>, <&peri_s2f_usr1_clk>,
302 <&osc1>, <&cb_intosc_hs_div2_clk>,
303 <&f2s_free_clk>;
304 reg = <0x104>;
305 };
306
307 sdmmc_free_clk: sdmmc_free_clk@f8 {
308 #clock-cells = <0>;
309 compatible = "altr,socfpga-a10-perip-clk";
310 clocks = <&main_sdmmc_clk>, <&peri_sdmmc_clk>,
311 <&osc1>, <&cb_intosc_hs_div2_clk>,
312 <&f2s_free_clk>;
313 fixed-divider = <4>;
314 reg = <0xF8>;
315 };
316
317 l4_sys_free_clk: l4_sys_free_clk {
318 #clock-cells = <0>;
319 compatible = "altr,socfpga-a10-perip-clk";
320 clocks = <&noc_free_clk>;
321 fixed-divider = <4>;
322 };
323
324 l4_main_clk: l4_main_clk {
325 #clock-cells = <0>;
326 compatible = "altr,socfpga-a10-gate-clk";
327 clocks = <&noc_free_clk>;
328 div-reg = <0xA8 0 2>;
329 clk-gate = <0x48 1>;
330 };
331
332 l4_mp_clk: l4_mp_clk {
333 #clock-cells = <0>;
334 compatible = "altr,socfpga-a10-gate-clk";
335 clocks = <&noc_free_clk>;
336 div-reg = <0xA8 8 2>;
337 clk-gate = <0x48 2>;
338 };
339
340 l4_sp_clk: l4_sp_clk {
341 #clock-cells = <0>;
342 compatible = "altr,socfpga-a10-gate-clk";
343 clocks = <&noc_free_clk>;
344 div-reg = <0xA8 16 2>;
345 clk-gate = <0x48 3>;
346 };
347
348 mpu_periph_clk: mpu_periph_clk {
349 #clock-cells = <0>;
350 compatible = "altr,socfpga-a10-gate-clk";
351 clocks = <&mpu_free_clk>;
352 fixed-divider = <4>;
353 clk-gate = <0x48 0>;
354 };
355
356 sdmmc_clk: sdmmc_clk {
357 #clock-cells = <0>;
358 compatible = "altr,socfpga-a10-gate-clk";
359 clocks = <&sdmmc_free_clk>;
360 clk-gate = <0xC8 5>;
361 clk-phase = <0 135>;
362 };
363
364 qspi_clk: qspi_clk {
365 #clock-cells = <0>;
366 compatible = "altr,socfpga-a10-gate-clk";
367 clocks = <&l4_main_clk>;
368 clk-gate = <0xC8 11>;
369 };
370
371 nand_x_clk: nand_x_clk {
372 #clock-cells = <0>;
373 compatible = "altr,socfpga-a10-gate-clk";
374 clocks = <&l4_mp_clk>;
375 clk-gate = <0xC8 10>;
376 };
377
378 nand_ecc_clk: nand_ecc_clk {
379 #clock-cells = <0>;
380 compatible = "altr,socfpga-a10-gate-clk";
381 clocks = <&nand_x_clk>;
382 clk-gate = <0xC8 10>;
383 };
384
385 nand_clk: nand_clk {
386 #clock-cells = <0>;
387 compatible = "altr,socfpga-a10-gate-clk";
388 clocks = <&nand_x_clk>;
389 fixed-divider = <4>;
390 clk-gate = <0xC8 10>;
391 };
392
393 spi_m_clk: spi_m_clk {
394 #clock-cells = <0>;
395 compatible = "altr,socfpga-a10-gate-clk";
396 clocks = <&l4_main_clk>;
397 clk-gate = <0xC8 9>;
398 };
399
400 usb_clk: usb_clk {
401 #clock-cells = <0>;
402 compatible = "altr,socfpga-a10-gate-clk";
403 clocks = <&l4_mp_clk>;
404 clk-gate = <0xC8 8>;
405 };
406
407 s2f_usr1_clk: s2f_usr1_clk {
408 #clock-cells = <0>;
409 compatible = "altr,socfpga-a10-gate-clk";
410 clocks = <&peri_s2f_usr1_clk>;
411 clk-gate = <0xC8 6>;
412 };
413 };
414 };
415
416 socfpga_axi_setup: stmmac-axi-config {
417 snps,wr_osr_lmt = <0xf>;
418 snps,rd_osr_lmt = <0xf>;
419 snps,blen = <0 0 0 0 16 0 0>;
420 };
421
422 gmac0: ethernet@ff800000 {
423 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";
424 altr,sysmgr-syscon = <&sysmgr 0x44 0>;
425 reg = <0xff800000 0x2000>;
426 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
427 interrupt-names = "macirq";
428 /* Filled in by bootloader */
429 mac-address = [00 00 00 00 00 00];
430 snps,multicast-filter-bins = <256>;
431 snps,perfect-filter-entries = <128>;
432 tx-fifo-depth = <4096>;
433 rx-fifo-depth = <16384>;
434 clocks = <&l4_mp_clk>;
435 clock-names = "stmmaceth";
436 resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
437 reset-names = "stmmaceth", "stmmaceth-ocp";
438 snps,axi-config = <&socfpga_axi_setup>;
439 status = "disabled";
440 };
441
442 gmac1: ethernet@ff802000 {
443 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";
444 altr,sysmgr-syscon = <&sysmgr 0x48 8>;
445 reg = <0xff802000 0x2000>;
446 interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
447 interrupt-names = "macirq";
448 /* Filled in by bootloader */
449 mac-address = [00 00 00 00 00 00];
450 snps,multicast-filter-bins = <256>;
451 snps,perfect-filter-entries = <128>;
452 tx-fifo-depth = <4096>;
453 rx-fifo-depth = <16384>;
454 clocks = <&l4_mp_clk>;
455 clock-names = "stmmaceth";
456 resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
457 reset-names = "stmmaceth", "stmmaceth-ocp";
458 snps,axi-config = <&socfpga_axi_setup>;
459 status = "disabled";
460 };
461
462 gmac2: ethernet@ff804000 {
463 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";
464 altr,sysmgr-syscon = <&sysmgr 0x4C 16>;
465 reg = <0xff804000 0x2000>;
466 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
467 interrupt-names = "macirq";
468 /* Filled in by bootloader */
469 mac-address = [00 00 00 00 00 00];
470 snps,multicast-filter-bins = <256>;
471 snps,perfect-filter-entries = <128>;
472 tx-fifo-depth = <4096>;
473 rx-fifo-depth = <16384>;
474 clocks = <&l4_mp_clk>;
475 clock-names = "stmmaceth";
476 resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
477 reset-names = "stmmaceth", "stmmaceth-ocp";
478 snps,axi-config = <&socfpga_axi_setup>;
479 status = "disabled";
480 };
481
482 gpio0: gpio@ffc02900 {
483 #address-cells = <1>;
484 #size-cells = <0>;
485 compatible = "snps,dw-apb-gpio";
486 reg = <0xffc02900 0x100>;
487 resets = <&rst GPIO0_RESET>;
488 status = "disabled";
489
490 porta: gpio-controller@0 {
491 compatible = "snps,dw-apb-gpio-port";
492 gpio-controller;
493 #gpio-cells = <2>;
494 snps,nr-gpios = <29>;
495 reg = <0>;
496 interrupt-controller;
497 #interrupt-cells = <2>;
498 interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
499 };
500 };
501
502 gpio1: gpio@ffc02a00 {
503 #address-cells = <1>;
504 #size-cells = <0>;
505 compatible = "snps,dw-apb-gpio";
506 reg = <0xffc02a00 0x100>;
507 resets = <&rst GPIO1_RESET>;
508 status = "disabled";
509
510 portb: gpio-controller@0 {
511 compatible = "snps,dw-apb-gpio-port";
512 gpio-controller;
513 #gpio-cells = <2>;
514 snps,nr-gpios = <29>;
515 reg = <0>;
516 interrupt-controller;
517 #interrupt-cells = <2>;
518 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
519 };
520 };
521
522 gpio2: gpio@ffc02b00 {
523 #address-cells = <1>;
524 #size-cells = <0>;
525 compatible = "snps,dw-apb-gpio";
526 reg = <0xffc02b00 0x100>;
527 resets = <&rst GPIO2_RESET>;
528 status = "disabled";
529
530 portc: gpio-controller@0 {
531 compatible = "snps,dw-apb-gpio-port";
532 gpio-controller;
533 #gpio-cells = <2>;
534 snps,nr-gpios = <27>;
535 reg = <0>;
536 interrupt-controller;
537 #interrupt-cells = <2>;
538 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
539 };
540 };
541
542 fpga_mgr: fpga-mgr@ffd03000 {
543 compatible = "altr,socfpga-a10-fpga-mgr";
544 reg = <0xffd03000 0x100
545 0xffcfe400 0x20>;
546 clocks = <&l4_mp_clk>;
547 resets = <&rst FPGAMGR_RESET>;
548 reset-names = "fpgamgr";
549 };
550
551 i2c0: i2c@ffc02200 {
552 #address-cells = <1>;
553 #size-cells = <0>;
554 compatible = "snps,designware-i2c";
555 reg = <0xffc02200 0x100>;
556 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
557 clocks = <&l4_sp_clk>;
558 resets = <&rst I2C0_RESET>;
559 status = "disabled";
560 };
561
562 i2c1: i2c@ffc02300 {
563 #address-cells = <1>;
564 #size-cells = <0>;
565 compatible = "snps,designware-i2c";
566 reg = <0xffc02300 0x100>;
567 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
568 clocks = <&l4_sp_clk>;
569 resets = <&rst I2C1_RESET>;
570 status = "disabled";
571 };
572
573 i2c2: i2c@ffc02400 {
574 #address-cells = <1>;
575 #size-cells = <0>;
576 compatible = "snps,designware-i2c";
577 reg = <0xffc02400 0x100>;
578 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
579 clocks = <&l4_sp_clk>;
580 resets = <&rst I2C2_RESET>;
581 status = "disabled";
582 };
583
584 i2c3: i2c@ffc02500 {
585 #address-cells = <1>;
586 #size-cells = <0>;
587 compatible = "snps,designware-i2c";
588 reg = <0xffc02500 0x100>;
589 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
590 clocks = <&l4_sp_clk>;
591 resets = <&rst I2C3_RESET>;
592 status = "disabled";
593 };
594
595 i2c4: i2c@ffc02600 {
596 #address-cells = <1>;
597 #size-cells = <0>;
598 compatible = "snps,designware-i2c";
599 reg = <0xffc02600 0x100>;
600 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
601 clocks = <&l4_sp_clk>;
602 resets = <&rst I2C4_RESET>;
603 status = "disabled";
604 };
605
606 spi0: spi@ffda4000 {
607 compatible = "snps,dw-apb-ssi";
608 #address-cells = <1>;
609 #size-cells = <0>;
610 reg = <0xffda4000 0x100>;
611 interrupts = <0 101 4>;
612 num-cs = <4>;
613 /*32bit_access;*/
614 clocks = <&spi_m_clk>;
615 resets = <&rst SPIM0_RESET>;
616 status = "disabled";
617 };
618
619 spi1: spi@ffda5000 {
620 compatible = "snps,dw-apb-ssi";
621 #address-cells = <1>;
622 #size-cells = <0>;
623 reg = <0xffda5000 0x100>;
624 interrupts = <0 102 4>;
625 num-cs = <4>;
626 /*32bit_access;*/
627 tx-dma-channel = <&pdma 16>;
628 rx-dma-channel = <&pdma 17>;
629 clocks = <&spi_m_clk>;
630 resets = <&rst SPIM1_RESET>;
631 status = "disabled";
632 };
633
634 sdr: sdr@ffcfb100 {
635 compatible = "altr,sdr-ctl", "syscon";
636 reg = <0xffcfb100 0x80>;
637 };
638
639 L2: l2-cache@fffff000 {
640 compatible = "arm,pl310-cache";
641 reg = <0xfffff000 0x1000>;
642 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
643 cache-unified;
644 cache-level = <2>;
645 prefetch-data = <1>;
646 prefetch-instr = <1>;
647 arm,shared-override;
648 };
649
650 mmc: dwmmc0@ff808000 {
651 #address-cells = <1>;
652 #size-cells = <0>;
653 compatible = "altr,socfpga-dw-mshc";
654 reg = <0xff808000 0x1000>;
655 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
656 fifo-depth = <0x400>;
657 clocks = <&l4_mp_clk>, <&sdmmc_clk>;
658 clock-names = "biu", "ciu";
659 resets = <&rst SDMMC_RESET>;
660 status = "disabled";
661 };
662
663 nand: nand@ffb90000 {
664 #address-cells = <1>;
665 #size-cells = <0>;
666 compatible = "altr,socfpga-denali-nand";
667 reg = <0xffb90000 0x72000>,
668 <0xffb80000 0x10000>;
669 reg-names = "nand_data", "denali_reg";
670 interrupts = <0 99 4>;
671 clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;
672 clock-names = "nand", "nand_x", "ecc";
673 resets = <&rst NAND_RESET>;
674 status = "disabled";
675 };
676
677 ocram: sram@ffe00000 {
678 compatible = "mmio-sram";
679 reg = <0xffe00000 0x40000>;
680 };
681
682 eccmgr: eccmgr {
683 compatible = "altr,socfpga-a10-ecc-manager";
684 altr,sysmgr-syscon = <&sysmgr>;
685 #address-cells = <1>;
686 #size-cells = <1>;
687 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,
688 <0 0 IRQ_TYPE_LEVEL_HIGH>;
689 interrupt-controller;
690 #interrupt-cells = <2>;
691 ranges;
692
693 sdramedac {
694 compatible = "altr,sdram-edac-a10";
695 altr,sdr-syscon = <&sdr>;
696 interrupts = <17 IRQ_TYPE_LEVEL_HIGH>,
697 <49 IRQ_TYPE_LEVEL_HIGH>;
698 };
699
700 l2-ecc@ffd06010 {
701 compatible = "altr,socfpga-a10-l2-ecc";
702 reg = <0xffd06010 0x4>;
703 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>,
704 <32 IRQ_TYPE_LEVEL_HIGH>;
705 };
706
707 ocram-ecc@ff8c3000 {
708 compatible = "altr,socfpga-a10-ocram-ecc";
709 reg = <0xff8c3000 0x400>;
710 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>,
711 <33 IRQ_TYPE_LEVEL_HIGH>;
712 };
713
714 emac0-rx-ecc@ff8c0800 {
715 compatible = "altr,socfpga-eth-mac-ecc";
716 reg = <0xff8c0800 0x400>;
717 altr,ecc-parent = <&gmac0>;
718 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>,
719 <36 IRQ_TYPE_LEVEL_HIGH>;
720 };
721
722 emac0-tx-ecc@ff8c0c00 {
723 compatible = "altr,socfpga-eth-mac-ecc";
724 reg = <0xff8c0c00 0x400>;
725 altr,ecc-parent = <&gmac0>;
726 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>,
727 <37 IRQ_TYPE_LEVEL_HIGH>;
728 };
729
730 dma-ecc@ff8c8000 {
731 compatible = "altr,socfpga-dma-ecc";
732 reg = <0xff8c8000 0x400>;
733 altr,ecc-parent = <&pdma>;
734 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
735 <42 IRQ_TYPE_LEVEL_HIGH>;
736 };
737
738 usb0-ecc@ff8c8800 {
739 compatible = "altr,socfpga-usb-ecc";
740 reg = <0xff8c8800 0x400>;
741 altr,ecc-parent = <&usb0>;
742 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>,
743 <34 IRQ_TYPE_LEVEL_HIGH>;
744 };
745 };
746
747 qspi: spi@ff809000 {
748 compatible = "cdns,qspi-nor";
749 #address-cells = <1>;
750 #size-cells = <0>;
751 reg = <0xff809000 0x100>,
752 <0xffa00000 0x100000>;
753 interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
754 cdns,fifo-depth = <128>;
755 cdns,fifo-width = <4>;
756 cdns,trigger-address = <0x00000000>;
757 clocks = <&qspi_clk>;
758 resets = <&rst QSPI_RESET>, <&rst QSPI_OCP_RESET>;
759 reset-names = "qspi", "qspi-ocp";
760 status = "disabled";
761 };
762
763 rst: rstmgr@ffd05000 {
764 #reset-cells = <1>;
765 compatible = "altr,rst-mgr";
766 reg = <0xffd05000 0x100>;
767 altr,modrst-offset = <0x20>;
768 };
769
770 scu: snoop-control-unit@ffffc000 {
771 compatible = "arm,cortex-a9-scu";
772 reg = <0xffffc000 0x100>;
773 };
774
775 sysmgr: sysmgr@ffd06000 {
776 compatible = "altr,sys-mgr", "syscon";
777 reg = <0xffd06000 0x300>;
778 cpu1-start-addr = <0xffd06230>;
779 };
780
781 /* Local timer */
782 timer@ffffc600 {
783 compatible = "arm,cortex-a9-twd-timer";
784 reg = <0xffffc600 0x100>;
785 interrupts = <1 13 0xf01>;
786 clocks = <&mpu_periph_clk>;
787 };
788
789 timer0: timer0@ffc02700 {
790 compatible = "snps,dw-apb-timer";
791 interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>;
792 reg = <0xffc02700 0x100>;
793 clocks = <&l4_sp_clk>;
794 clock-names = "timer";
795 resets = <&rst SPTIMER0_RESET>;
796 reset-names = "timer";
797 };
798
799 timer1: timer1@ffc02800 {
800 compatible = "snps,dw-apb-timer";
801 interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>;
802 reg = <0xffc02800 0x100>;
803 clocks = <&l4_sp_clk>;
804 clock-names = "timer";
805 resets = <&rst SPTIMER1_RESET>;
806 reset-names = "timer";
807 };
808
809 timer2: timer2@ffd00000 {
810 compatible = "snps,dw-apb-timer";
811 interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>;
812 reg = <0xffd00000 0x100>;
813 clocks = <&l4_sys_free_clk>;
814 clock-names = "timer";
815 resets = <&rst L4SYSTIMER0_RESET>;
816 reset-names = "timer";
817 };
818
819 timer3: timer3@ffd00100 {
820 compatible = "snps,dw-apb-timer";
821 interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>;
822 reg = <0xffd01000 0x100>;
823 clocks = <&l4_sys_free_clk>;
824 clock-names = "timer";
825 resets = <&rst L4SYSTIMER1_RESET>;
826 reset-names = "timer";
827 };
828
829 uart0: serial0@ffc02000 {
830 compatible = "snps,dw-apb-uart";
831 reg = <0xffc02000 0x100>;
832 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
833 reg-shift = <2>;
834 reg-io-width = <4>;
835 clocks = <&l4_sp_clk>;
836 resets = <&rst UART0_RESET>;
837 status = "disabled";
838 };
839
840 uart1: serial1@ffc02100 {
841 compatible = "snps,dw-apb-uart";
842 reg = <0xffc02100 0x100>;
843 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
844 reg-shift = <2>;
845 reg-io-width = <4>;
846 clocks = <&l4_sp_clk>;
847 resets = <&rst UART1_RESET>;
848 status = "disabled";
849 };
850
851 usbphy0: usbphy {
852 #phy-cells = <0>;
853 compatible = "usb-nop-xceiv";
854 status = "okay";
855 };
856
857 usb0: usb@ffb00000 {
858 compatible = "snps,dwc2";
859 reg = <0xffb00000 0xffff>;
860 interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
861 clocks = <&usb_clk>;
862 clock-names = "otg";
863 resets = <&rst USB0_RESET>;
864 reset-names = "dwc2";
865 phys = <&usbphy0>;
866 phy-names = "usb2-phy";
867 status = "disabled";
868 };
869
870 usb1: usb@ffb40000 {
871 compatible = "snps,dwc2";
872 reg = <0xffb40000 0xffff>;
873 interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
874 clocks = <&usb_clk>;
875 clock-names = "otg";
876 resets = <&rst USB1_RESET>;
877 reset-names = "dwc2";
878 phys = <&usbphy0>;
879 phy-names = "usb2-phy";
880 status = "disabled";
881 };
882
883 watchdog0: watchdog@ffd00200 {
884 compatible = "snps,dw-wdt";
885 reg = <0xffd00200 0x100>;
886 interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
887 clocks = <&l4_sys_free_clk>;
888 resets = <&rst L4WD0_RESET>;
889 status = "disabled";
890 };
891
892 watchdog1: watchdog@ffd00300 {
893 compatible = "snps,dw-wdt";
894 reg = <0xffd00300 0x100>;
895 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
896 clocks = <&l4_sys_free_clk>;
897 resets = <&rst L4WD1_RESET>;
898 status = "disabled";
899 };
900 };
901 };
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