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Merge tag 'xfs-for-linus-3.17-rc1' of git://oss.sgi.com/xfs/xfs
[mirror_ubuntu-bionic-kernel.git] / arch / arm / boot / dts / ste-dbx5x0.dtsi
1 /*
2 * Copyright 2012 Linaro Ltd
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/mfd/dbx500-prcmu.h>
14 #include "skeleton.dtsi"
15
16 / {
17 soc {
18 #address-cells = <1>;
19 #size-cells = <1>;
20 compatible = "stericsson,db8500";
21 interrupt-parent = <&intc>;
22 ranges;
23
24 intc: interrupt-controller@a0411000 {
25 compatible = "arm,cortex-a9-gic";
26 #interrupt-cells = <3>;
27 #address-cells = <1>;
28 interrupt-controller;
29 reg = <0xa0411000 0x1000>,
30 <0xa0410100 0x100>;
31 };
32
33 L2: l2-cache {
34 compatible = "arm,pl310-cache";
35 reg = <0xa0412000 0x1000>;
36 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>;
37 cache-unified;
38 cache-level = <2>;
39 };
40
41 pmu {
42 compatible = "arm,cortex-a9-pmu";
43 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
44 };
45
46
47 clocks {
48 compatible = "stericsson,u8500-clks";
49
50 prcmu_clk: prcmu-clock {
51 #clock-cells = <1>;
52 };
53
54 prcc_pclk: prcc-periph-clock {
55 #clock-cells = <2>;
56 };
57
58 prcc_kclk: prcc-kernel-clock {
59 #clock-cells = <2>;
60 };
61
62 rtc_clk: rtc32k-clock {
63 #clock-cells = <0>;
64 };
65
66 smp_twd_clk: smp-twd-clock {
67 #clock-cells = <0>;
68 };
69 };
70
71 mtu@a03c6000 {
72 /* Nomadik System Timer */
73 compatible = "st,nomadik-mtu";
74 reg = <0xa03c6000 0x1000>;
75 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
76
77 clocks = <&prcmu_clk PRCMU_TIMCLK>, <&prcc_pclk 6 6>;
78 clock-names = "timclk", "apb_pclk";
79 };
80
81 timer@a0410600 {
82 compatible = "arm,cortex-a9-twd-timer";
83 reg = <0xa0410600 0x20>;
84 interrupts = <1 13 0x304>; /* IRQ level high per-CPU */
85
86 clocks = <&smp_twd_clk>;
87 };
88
89 rtc@80154000 {
90 compatible = "arm,rtc-pl031", "arm,primecell";
91 reg = <0x80154000 0x1000>;
92 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
93
94 clocks = <&rtc_clk>;
95 clock-names = "apb_pclk";
96 };
97
98 gpio0: gpio@8012e000 {
99 compatible = "stericsson,db8500-gpio",
100 "st,nomadik-gpio";
101 reg = <0x8012e000 0x80>;
102 interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
103 interrupt-controller;
104 #interrupt-cells = <2>;
105 st,supports-sleepmode;
106 gpio-controller;
107 #gpio-cells = <2>;
108 gpio-bank = <0>;
109
110 clocks = <&prcc_pclk 1 9>;
111 };
112
113 gpio1: gpio@8012e080 {
114 compatible = "stericsson,db8500-gpio",
115 "st,nomadik-gpio";
116 reg = <0x8012e080 0x80>;
117 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
118 interrupt-controller;
119 #interrupt-cells = <2>;
120 st,supports-sleepmode;
121 gpio-controller;
122 #gpio-cells = <2>;
123 gpio-bank = <1>;
124
125 clocks = <&prcc_pclk 1 9>;
126 };
127
128 gpio2: gpio@8000e000 {
129 compatible = "stericsson,db8500-gpio",
130 "st,nomadik-gpio";
131 reg = <0x8000e000 0x80>;
132 interrupts = <0 121 IRQ_TYPE_LEVEL_HIGH>;
133 interrupt-controller;
134 #interrupt-cells = <2>;
135 st,supports-sleepmode;
136 gpio-controller;
137 #gpio-cells = <2>;
138 gpio-bank = <2>;
139
140 clocks = <&prcc_pclk 3 8>;
141 };
142
143 gpio3: gpio@8000e080 {
144 compatible = "stericsson,db8500-gpio",
145 "st,nomadik-gpio";
146 reg = <0x8000e080 0x80>;
147 interrupts = <0 122 IRQ_TYPE_LEVEL_HIGH>;
148 interrupt-controller;
149 #interrupt-cells = <2>;
150 st,supports-sleepmode;
151 gpio-controller;
152 #gpio-cells = <2>;
153 gpio-bank = <3>;
154
155 clocks = <&prcc_pclk 3 8>;
156 };
157
158 gpio4: gpio@8000e100 {
159 compatible = "stericsson,db8500-gpio",
160 "st,nomadik-gpio";
161 reg = <0x8000e100 0x80>;
162 interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>;
163 interrupt-controller;
164 #interrupt-cells = <2>;
165 st,supports-sleepmode;
166 gpio-controller;
167 #gpio-cells = <2>;
168 gpio-bank = <4>;
169
170 clocks = <&prcc_pclk 3 8>;
171 };
172
173 gpio5: gpio@8000e180 {
174 compatible = "stericsson,db8500-gpio",
175 "st,nomadik-gpio";
176 reg = <0x8000e180 0x80>;
177 interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
178 interrupt-controller;
179 #interrupt-cells = <2>;
180 st,supports-sleepmode;
181 gpio-controller;
182 #gpio-cells = <2>;
183 gpio-bank = <5>;
184
185 clocks = <&prcc_pclk 3 8>;
186 };
187
188 gpio6: gpio@8011e000 {
189 compatible = "stericsson,db8500-gpio",
190 "st,nomadik-gpio";
191 reg = <0x8011e000 0x80>;
192 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
193 interrupt-controller;
194 #interrupt-cells = <2>;
195 st,supports-sleepmode;
196 gpio-controller;
197 #gpio-cells = <2>;
198 gpio-bank = <6>;
199
200 clocks = <&prcc_pclk 2 11>;
201 };
202
203 gpio7: gpio@8011e080 {
204 compatible = "stericsson,db8500-gpio",
205 "st,nomadik-gpio";
206 reg = <0x8011e080 0x80>;
207 interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>;
208 interrupt-controller;
209 #interrupt-cells = <2>;
210 st,supports-sleepmode;
211 gpio-controller;
212 #gpio-cells = <2>;
213 gpio-bank = <7>;
214
215 clocks = <&prcc_pclk 2 11>;
216 };
217
218 gpio8: gpio@a03fe000 {
219 compatible = "stericsson,db8500-gpio",
220 "st,nomadik-gpio";
221 reg = <0xa03fe000 0x80>;
222 interrupts = <0 127 IRQ_TYPE_LEVEL_HIGH>;
223 interrupt-controller;
224 #interrupt-cells = <2>;
225 st,supports-sleepmode;
226 gpio-controller;
227 #gpio-cells = <2>;
228 gpio-bank = <8>;
229
230 clocks = <&prcc_pclk 5 1>;
231 };
232
233 pinctrl {
234 compatible = "stericsson,db8500-pinctrl";
235 prcm = <&prcmu>;
236 };
237
238 usb_per5@a03e0000 {
239 compatible = "stericsson,db8500-musb";
240 reg = <0xa03e0000 0x10000>;
241 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
242 interrupt-names = "mc";
243
244 dr_mode = "otg";
245
246 dmas = <&dma 38 0 0x2>, /* Logical - DevToMem */
247 <&dma 38 0 0x0>, /* Logical - MemToDev */
248 <&dma 37 0 0x2>, /* Logical - DevToMem */
249 <&dma 37 0 0x0>, /* Logical - MemToDev */
250 <&dma 36 0 0x2>, /* Logical - DevToMem */
251 <&dma 36 0 0x0>, /* Logical - MemToDev */
252 <&dma 19 0 0x2>, /* Logical - DevToMem */
253 <&dma 19 0 0x0>, /* Logical - MemToDev */
254 <&dma 18 0 0x2>, /* Logical - DevToMem */
255 <&dma 18 0 0x0>, /* Logical - MemToDev */
256 <&dma 17 0 0x2>, /* Logical - DevToMem */
257 <&dma 17 0 0x0>, /* Logical - MemToDev */
258 <&dma 16 0 0x2>, /* Logical - DevToMem */
259 <&dma 16 0 0x0>, /* Logical - MemToDev */
260 <&dma 39 0 0x2>, /* Logical - DevToMem */
261 <&dma 39 0 0x0>; /* Logical - MemToDev */
262
263 dma-names = "iep_1_9", "oep_1_9",
264 "iep_2_10", "oep_2_10",
265 "iep_3_11", "oep_3_11",
266 "iep_4_12", "oep_4_12",
267 "iep_5_13", "oep_5_13",
268 "iep_6_14", "oep_6_14",
269 "iep_7_15", "oep_7_15",
270 "iep_8", "oep_8";
271
272 clocks = <&prcc_pclk 5 0>;
273 };
274
275 dma: dma-controller@801C0000 {
276 compatible = "stericsson,db8500-dma40", "stericsson,dma40";
277 reg = <0x801C0000 0x1000 0x40010000 0x800>;
278 reg-names = "base", "lcpa";
279 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
280
281 #dma-cells = <3>;
282 memcpy-channels = <56 57 58 59 60>;
283
284 clocks = <&prcmu_clk PRCMU_DMACLK>;
285 };
286
287 prcmu: prcmu@80157000 {
288 compatible = "stericsson,db8500-prcmu";
289 reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>;
290 reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm";
291 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
292 #address-cells = <1>;
293 #size-cells = <1>;
294 interrupt-controller;
295 #interrupt-cells = <2>;
296 ranges;
297
298 prcmu-timer-4@80157450 {
299 compatible = "stericsson,db8500-prcmu-timer-4";
300 reg = <0x80157450 0xC>;
301 };
302
303 cpufreq {
304 compatible = "stericsson,cpufreq-ux500";
305 clocks = <&prcmu_clk PRCMU_ARMSS>;
306 clock-names = "armss";
307 status = "disabled";
308 };
309
310 thermal@801573c0 {
311 compatible = "stericsson,db8500-thermal";
312 reg = <0x801573c0 0x40>;
313 interrupts = <21 IRQ_TYPE_LEVEL_HIGH>,
314 <22 IRQ_TYPE_LEVEL_HIGH>;
315 interrupt-names = "IRQ_HOTMON_LOW", "IRQ_HOTMON_HIGH";
316 status = "disabled";
317 };
318
319 db8500-prcmu-regulators {
320 compatible = "stericsson,db8500-prcmu-regulator";
321
322 // DB8500_REGULATOR_VAPE
323 db8500_vape_reg: db8500_vape {
324 regulator-compatible = "db8500_vape";
325 regulator-always-on;
326 };
327
328 // DB8500_REGULATOR_VARM
329 db8500_varm_reg: db8500_varm {
330 regulator-compatible = "db8500_varm";
331 };
332
333 // DB8500_REGULATOR_VMODEM
334 db8500_vmodem_reg: db8500_vmodem {
335 regulator-compatible = "db8500_vmodem";
336 };
337
338 // DB8500_REGULATOR_VPLL
339 db8500_vpll_reg: db8500_vpll {
340 regulator-compatible = "db8500_vpll";
341 };
342
343 // DB8500_REGULATOR_VSMPS1
344 db8500_vsmps1_reg: db8500_vsmps1 {
345 regulator-compatible = "db8500_vsmps1";
346 };
347
348 // DB8500_REGULATOR_VSMPS2
349 db8500_vsmps2_reg: db8500_vsmps2 {
350 regulator-compatible = "db8500_vsmps2";
351 };
352
353 // DB8500_REGULATOR_VSMPS3
354 db8500_vsmps3_reg: db8500_vsmps3 {
355 regulator-compatible = "db8500_vsmps3";
356 };
357
358 // DB8500_REGULATOR_VRF1
359 db8500_vrf1_reg: db8500_vrf1 {
360 regulator-compatible = "db8500_vrf1";
361 };
362
363 // DB8500_REGULATOR_SWITCH_SVAMMDSP
364 db8500_sva_mmdsp_reg: db8500_sva_mmdsp {
365 regulator-compatible = "db8500_sva_mmdsp";
366 };
367
368 // DB8500_REGULATOR_SWITCH_SVAMMDSPRET
369 db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret {
370 regulator-compatible = "db8500_sva_mmdsp_ret";
371 };
372
373 // DB8500_REGULATOR_SWITCH_SVAPIPE
374 db8500_sva_pipe_reg: db8500_sva_pipe {
375 regulator-compatible = "db8500_sva_pipe";
376 };
377
378 // DB8500_REGULATOR_SWITCH_SIAMMDSP
379 db8500_sia_mmdsp_reg: db8500_sia_mmdsp {
380 regulator-compatible = "db8500_sia_mmdsp";
381 };
382
383 // DB8500_REGULATOR_SWITCH_SIAMMDSPRET
384 db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret {
385 };
386
387 // DB8500_REGULATOR_SWITCH_SIAPIPE
388 db8500_sia_pipe_reg: db8500_sia_pipe {
389 regulator-compatible = "db8500_sia_pipe";
390 };
391
392 // DB8500_REGULATOR_SWITCH_SGA
393 db8500_sga_reg: db8500_sga {
394 regulator-compatible = "db8500_sga";
395 vin-supply = <&db8500_vape_reg>;
396 };
397
398 // DB8500_REGULATOR_SWITCH_B2R2_MCDE
399 db8500_b2r2_mcde_reg: db8500_b2r2_mcde {
400 regulator-compatible = "db8500_b2r2_mcde";
401 vin-supply = <&db8500_vape_reg>;
402 };
403
404 // DB8500_REGULATOR_SWITCH_ESRAM12
405 db8500_esram12_reg: db8500_esram12 {
406 regulator-compatible = "db8500_esram12";
407 };
408
409 // DB8500_REGULATOR_SWITCH_ESRAM12RET
410 db8500_esram12_ret_reg: db8500_esram12_ret {
411 regulator-compatible = "db8500_esram12_ret";
412 };
413
414 // DB8500_REGULATOR_SWITCH_ESRAM34
415 db8500_esram34_reg: db8500_esram34 {
416 regulator-compatible = "db8500_esram34";
417 };
418
419 // DB8500_REGULATOR_SWITCH_ESRAM34RET
420 db8500_esram34_ret_reg: db8500_esram34_ret {
421 regulator-compatible = "db8500_esram34_ret";
422 };
423 };
424
425 ab8500 {
426 compatible = "stericsson,ab8500";
427 interrupt-parent = <&intc>;
428 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
429 interrupt-controller;
430 #interrupt-cells = <2>;
431
432 ab8500_gpio: ab8500-gpio {
433 gpio-controller;
434 #gpio-cells = <2>;
435 };
436
437 ab8500-rtc {
438 compatible = "stericsson,ab8500-rtc";
439 interrupts = <17 IRQ_TYPE_LEVEL_HIGH
440 18 IRQ_TYPE_LEVEL_HIGH>;
441 interrupt-names = "60S", "ALARM";
442 };
443
444 ab8500-gpadc {
445 compatible = "stericsson,ab8500-gpadc";
446 interrupts = <32 IRQ_TYPE_LEVEL_HIGH
447 39 IRQ_TYPE_LEVEL_HIGH>;
448 interrupt-names = "HW_CONV_END", "SW_CONV_END";
449 vddadc-supply = <&ab8500_ldo_tvout_reg>;
450 };
451
452 ab8500_battery: ab8500_battery {
453 stericsson,battery-type = "LIPO";
454 thermistor-on-batctrl;
455 };
456
457 ab8500_fg {
458 compatible = "stericsson,ab8500-fg";
459 battery = <&ab8500_battery>;
460 };
461
462 ab8500_btemp {
463 compatible = "stericsson,ab8500-btemp";
464 battery = <&ab8500_battery>;
465 };
466
467 ab8500_charger {
468 compatible = "stericsson,ab8500-charger";
469 battery = <&ab8500_battery>;
470 vddadc-supply = <&ab8500_ldo_tvout_reg>;
471 };
472
473 ab8500_chargalg {
474 compatible = "stericsson,ab8500-chargalg";
475 battery = <&ab8500_battery>;
476 };
477
478 ab8500_usb {
479 compatible = "stericsson,ab8500-usb";
480 interrupts = < 90 IRQ_TYPE_LEVEL_HIGH
481 96 IRQ_TYPE_LEVEL_HIGH
482 14 IRQ_TYPE_LEVEL_HIGH
483 15 IRQ_TYPE_LEVEL_HIGH
484 79 IRQ_TYPE_LEVEL_HIGH
485 74 IRQ_TYPE_LEVEL_HIGH
486 75 IRQ_TYPE_LEVEL_HIGH>;
487 interrupt-names = "ID_WAKEUP_R",
488 "ID_WAKEUP_F",
489 "VBUS_DET_F",
490 "VBUS_DET_R",
491 "USB_LINK_STATUS",
492 "USB_ADP_PROBE_PLUG",
493 "USB_ADP_PROBE_UNPLUG";
494 vddulpivio18-supply = <&ab8500_ldo_intcore_reg>;
495 v-ape-supply = <&db8500_vape_reg>;
496 musb_1v8-supply = <&db8500_vsmps2_reg>;
497 };
498
499 ab8500-ponkey {
500 compatible = "stericsson,ab8500-poweron-key";
501 interrupts = <6 IRQ_TYPE_LEVEL_HIGH
502 7 IRQ_TYPE_LEVEL_HIGH>;
503 interrupt-names = "ONKEY_DBF", "ONKEY_DBR";
504 };
505
506 ab8500-sysctrl {
507 compatible = "stericsson,ab8500-sysctrl";
508 };
509
510 ab8500-pwm {
511 compatible = "stericsson,ab8500-pwm";
512 };
513
514 ab8500-debugfs {
515 compatible = "stericsson,ab8500-debug";
516 };
517
518 codec: ab8500-codec {
519 compatible = "stericsson,ab8500-codec";
520
521 V-AUD-supply = <&ab8500_ldo_audio_reg>;
522 V-AMIC1-supply = <&ab8500_ldo_anamic1_reg>;
523 V-AMIC2-supply = <&ab8500_ldo_anamic2_reg>;
524 V-DMIC-supply = <&ab8500_ldo_dmic_reg>;
525
526 stericsson,earpeice-cmv = <950>; /* Units in mV. */
527 };
528
529 ext_regulators: ab8500-ext-regulators {
530 compatible = "stericsson,ab8500-ext-regulator";
531
532 ab8500_ext1_reg: ab8500_ext1 {
533 regulator-compatible = "ab8500_ext1";
534 regulator-min-microvolt = <1800000>;
535 regulator-max-microvolt = <1800000>;
536 regulator-boot-on;
537 regulator-always-on;
538 };
539
540 ab8500_ext2_reg: ab8500_ext2 {
541 regulator-compatible = "ab8500_ext2";
542 regulator-min-microvolt = <1360000>;
543 regulator-max-microvolt = <1360000>;
544 regulator-boot-on;
545 regulator-always-on;
546 };
547
548 ab8500_ext3_reg: ab8500_ext3 {
549 regulator-compatible = "ab8500_ext3";
550 regulator-min-microvolt = <3400000>;
551 regulator-max-microvolt = <3400000>;
552 regulator-boot-on;
553 };
554 };
555
556 ab8500-regulators {
557 compatible = "stericsson,ab8500-regulator";
558 vin-supply = <&ab8500_ext3_reg>;
559
560 // supplies to the display/camera
561 ab8500_ldo_aux1_reg: ab8500_ldo_aux1 {
562 regulator-compatible = "ab8500_ldo_aux1";
563 regulator-min-microvolt = <2500000>;
564 regulator-max-microvolt = <2900000>;
565 regulator-boot-on;
566 /* BUG: If turned off MMC will be affected. */
567 regulator-always-on;
568 };
569
570 // supplies to the on-board eMMC
571 ab8500_ldo_aux2_reg: ab8500_ldo_aux2 {
572 regulator-compatible = "ab8500_ldo_aux2";
573 regulator-min-microvolt = <1100000>;
574 regulator-max-microvolt = <3300000>;
575 };
576
577 // supply for VAUX3; SDcard slots
578 ab8500_ldo_aux3_reg: ab8500_ldo_aux3 {
579 regulator-compatible = "ab8500_ldo_aux3";
580 regulator-min-microvolt = <1100000>;
581 regulator-max-microvolt = <3300000>;
582 };
583
584 // supply for v-intcore12; VINTCORE12 LDO
585 ab8500_ldo_intcore_reg: ab8500_ldo_intcore {
586 regulator-compatible = "ab8500_ldo_intcore";
587 };
588
589 // supply for tvout; gpadc; TVOUT LDO
590 ab8500_ldo_tvout_reg: ab8500_ldo_tvout {
591 regulator-compatible = "ab8500_ldo_tvout";
592 };
593
594 // supply for ab8500-usb; USB LDO
595 ab8500_ldo_usb_reg: ab8500_ldo_usb {
596 regulator-compatible = "ab8500_ldo_usb";
597 };
598
599 // supply for ab8500-vaudio; VAUDIO LDO
600 ab8500_ldo_audio_reg: ab8500_ldo_audio {
601 regulator-compatible = "ab8500_ldo_audio";
602 };
603
604 // supply for v-anamic1 VAMIC1 LDO
605 ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 {
606 regulator-compatible = "ab8500_ldo_anamic1";
607 };
608
609 // supply for v-amic2; VAMIC2 LDO; reuse constants for AMIC1
610 ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 {
611 regulator-compatible = "ab8500_ldo_anamic2";
612 };
613
614 // supply for v-dmic; VDMIC LDO
615 ab8500_ldo_dmic_reg: ab8500_ldo_dmic {
616 regulator-compatible = "ab8500_ldo_dmic";
617 };
618
619 // supply for U8500 CSI/DSI; VANA LDO
620 ab8500_ldo_ana_reg: ab8500_ldo_ana {
621 regulator-compatible = "ab8500_ldo_ana";
622 };
623 };
624 };
625 };
626
627 i2c@80004000 {
628 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
629 reg = <0x80004000 0x1000>;
630 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
631
632 #address-cells = <1>;
633 #size-cells = <0>;
634 v-i2c-supply = <&db8500_vape_reg>;
635
636 clock-frequency = <400000>;
637 clocks = <&prcc_kclk 3 3>, <&prcc_pclk 3 3>;
638 clock-names = "i2cclk", "apb_pclk";
639 };
640
641 i2c@80122000 {
642 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
643 reg = <0x80122000 0x1000>;
644 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
645
646 #address-cells = <1>;
647 #size-cells = <0>;
648 v-i2c-supply = <&db8500_vape_reg>;
649
650 clock-frequency = <400000>;
651
652 clocks = <&prcc_kclk 1 2>, <&prcc_pclk 1 2>;
653 clock-names = "i2cclk", "apb_pclk";
654 };
655
656 i2c@80128000 {
657 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
658 reg = <0x80128000 0x1000>;
659 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
660
661 #address-cells = <1>;
662 #size-cells = <0>;
663 v-i2c-supply = <&db8500_vape_reg>;
664
665 clock-frequency = <400000>;
666
667 clocks = <&prcc_kclk 1 6>, <&prcc_pclk 1 6>;
668 clock-names = "i2cclk", "apb_pclk";
669 };
670
671 i2c@80110000 {
672 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
673 reg = <0x80110000 0x1000>;
674 interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>;
675
676 #address-cells = <1>;
677 #size-cells = <0>;
678 v-i2c-supply = <&db8500_vape_reg>;
679
680 clock-frequency = <400000>;
681
682 clocks = <&prcc_kclk 2 0>, <&prcc_pclk 2 0>;
683 clock-names = "i2cclk", "apb_pclk";
684 };
685
686 i2c@8012a000 {
687 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
688 reg = <0x8012a000 0x1000>;
689 interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
690
691 #address-cells = <1>;
692 #size-cells = <0>;
693 v-i2c-supply = <&db8500_vape_reg>;
694
695 clock-frequency = <400000>;
696
697 clocks = <&prcc_kclk 1 9>, <&prcc_pclk 1 10>;
698 clock-names = "i2cclk", "apb_pclk";
699 };
700
701 ssp@80002000 {
702 compatible = "arm,pl022", "arm,primecell";
703 reg = <0x80002000 0x1000>;
704 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
705 #address-cells = <1>;
706 #size-cells = <0>;
707 clocks = <&prcc_kclk 3 1>, <&prcc_pclk 3 1>;
708 clock-names = "SSPCLK", "apb_pclk";
709 dmas = <&dma 8 0 0x2>, /* Logical - DevToMem */
710 <&dma 8 0 0x0>; /* Logical - MemToDev */
711 dma-names = "rx", "tx";
712 };
713
714 ssp@80003000 {
715 compatible = "arm,pl022", "arm,primecell";
716 reg = <0x80003000 0x1000>;
717 interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
718 #address-cells = <1>;
719 #size-cells = <0>;
720 clocks = <&prcc_kclk 3 2>, <&prcc_pclk 3 2>;
721 clock-names = "SSPCLK", "apb_pclk";
722 dmas = <&dma 9 0 0x2>, /* Logical - DevToMem */
723 <&dma 9 0 0x0>; /* Logical - MemToDev */
724 dma-names = "rx", "tx";
725 };
726
727 spi@8011a000 {
728 compatible = "arm,pl022", "arm,primecell";
729 reg = <0x8011a000 0x1000>;
730 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
731 #address-cells = <1>;
732 #size-cells = <0>;
733 /* Same clock wired to kernel and pclk */
734 clocks = <&prcc_pclk 2 8>, <&prcc_pclk 2 8>;
735 clock-names = "SSPCLK", "apb_pclk";
736 dmas = <&dma 0 0 0x2>, /* Logical - DevToMem */
737 <&dma 0 0 0x0>; /* Logical - MemToDev */
738 dma-names = "rx", "tx";
739 };
740
741 spi@80112000 {
742 compatible = "arm,pl022", "arm,primecell";
743 reg = <0x80112000 0x1000>;
744 interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
745 #address-cells = <1>;
746 #size-cells = <0>;
747 /* Same clock wired to kernel and pclk */
748 clocks = <&prcc_pclk 2 2>, <&prcc_pclk 2 2>;
749 clock-names = "SSPCLK", "apb_pclk";
750 dmas = <&dma 35 0 0x2>, /* Logical - DevToMem */
751 <&dma 35 0 0x0>; /* Logical - MemToDev */
752 dma-names = "rx", "tx";
753 };
754
755 spi@80111000 {
756 compatible = "arm,pl022", "arm,primecell";
757 reg = <0x80111000 0x1000>;
758 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
759 #address-cells = <1>;
760 #size-cells = <0>;
761 /* Same clock wired to kernel and pclk */
762 clocks = <&prcc_pclk 2 1>, <&prcc_pclk 2 1>;
763 clock-names = "SSPCLK", "apb_pclk";
764 dmas = <&dma 33 0 0x2>, /* Logical - DevToMem */
765 <&dma 33 0 0x0>; /* Logical - MemToDev */
766 dma-names = "rx", "tx";
767 };
768
769 spi@80129000 {
770 compatible = "arm,pl022", "arm,primecell";
771 reg = <0x80129000 0x1000>;
772 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
773 #address-cells = <1>;
774 #size-cells = <0>;
775 /* Same clock wired to kernel and pclk */
776 clocks = <&prcc_pclk 1 7>, <&prcc_pclk 1 7>;
777 clock-names = "SSPCLK", "apb_pclk";
778 dmas = <&dma 40 0 0x2>, /* Logical - DevToMem */
779 <&dma 40 0 0x0>; /* Logical - MemToDev */
780 dma-names = "rx", "tx";
781 };
782
783 uart@80120000 {
784 compatible = "arm,pl011", "arm,primecell";
785 reg = <0x80120000 0x1000>;
786 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
787
788 dmas = <&dma 13 0 0x2>, /* Logical - DevToMem */
789 <&dma 13 0 0x0>; /* Logical - MemToDev */
790 dma-names = "rx", "tx";
791
792 clocks = <&prcc_kclk 1 0>, <&prcc_pclk 1 0>;
793 clock-names = "uart", "apb_pclk";
794
795 status = "disabled";
796 };
797
798 uart@80121000 {
799 compatible = "arm,pl011", "arm,primecell";
800 reg = <0x80121000 0x1000>;
801 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
802
803 dmas = <&dma 12 0 0x2>, /* Logical - DevToMem */
804 <&dma 12 0 0x0>; /* Logical - MemToDev */
805 dma-names = "rx", "tx";
806
807 clocks = <&prcc_kclk 1 1>, <&prcc_pclk 1 1>;
808 clock-names = "uart", "apb_pclk";
809
810 status = "disabled";
811 };
812
813 uart@80007000 {
814 compatible = "arm,pl011", "arm,primecell";
815 reg = <0x80007000 0x1000>;
816 interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
817
818 dmas = <&dma 11 0 0x2>, /* Logical - DevToMem */
819 <&dma 11 0 0x0>; /* Logical - MemToDev */
820 dma-names = "rx", "tx";
821
822 clocks = <&prcc_kclk 3 6>, <&prcc_pclk 3 6>;
823 clock-names = "uart", "apb_pclk";
824
825 status = "disabled";
826 };
827
828 sdi0_per1@80126000 {
829 compatible = "arm,pl18x", "arm,primecell";
830 reg = <0x80126000 0x1000>;
831 interrupts = <0 60 IRQ_TYPE_LEVEL_HIGH>;
832
833 dmas = <&dma 29 0 0x2>, /* Logical - DevToMem */
834 <&dma 29 0 0x0>; /* Logical - MemToDev */
835 dma-names = "rx", "tx";
836
837 clocks = <&prcc_kclk 1 5>, <&prcc_pclk 1 5>;
838 clock-names = "sdi", "apb_pclk";
839
840 status = "disabled";
841 };
842
843 sdi1_per2@80118000 {
844 compatible = "arm,pl18x", "arm,primecell";
845 reg = <0x80118000 0x1000>;
846 interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
847
848 dmas = <&dma 32 0 0x2>, /* Logical - DevToMem */
849 <&dma 32 0 0x0>; /* Logical - MemToDev */
850 dma-names = "rx", "tx";
851
852 clocks = <&prcc_kclk 2 4>, <&prcc_pclk 2 6>;
853 clock-names = "sdi", "apb_pclk";
854
855 status = "disabled";
856 };
857
858 sdi2_per3@80005000 {
859 compatible = "arm,pl18x", "arm,primecell";
860 reg = <0x80005000 0x1000>;
861 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
862
863 dmas = <&dma 28 0 0x2>, /* Logical - DevToMem */
864 <&dma 28 0 0x0>; /* Logical - MemToDev */
865 dma-names = "rx", "tx";
866
867 clocks = <&prcc_kclk 3 4>, <&prcc_pclk 3 4>;
868 clock-names = "sdi", "apb_pclk";
869
870 status = "disabled";
871 };
872
873 sdi3_per2@80119000 {
874 compatible = "arm,pl18x", "arm,primecell";
875 reg = <0x80119000 0x1000>;
876 interrupts = <0 59 IRQ_TYPE_LEVEL_HIGH>;
877
878 dmas = <&dma 41 0 0x2>, /* Logical - DevToMem */
879 <&dma 41 0 0x0>; /* Logical - MemToDev */
880 dma-names = "rx", "tx";
881
882 clocks = <&prcc_kclk 2 5>, <&prcc_pclk 2 7>;
883 clock-names = "sdi", "apb_pclk";
884
885 status = "disabled";
886 };
887
888 sdi4_per2@80114000 {
889 compatible = "arm,pl18x", "arm,primecell";
890 reg = <0x80114000 0x1000>;
891 interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>;
892
893 dmas = <&dma 42 0 0x2>, /* Logical - DevToMem */
894 <&dma 42 0 0x0>; /* Logical - MemToDev */
895 dma-names = "rx", "tx";
896
897 clocks = <&prcc_kclk 2 2>, <&prcc_pclk 2 4>;
898 clock-names = "sdi", "apb_pclk";
899
900 status = "disabled";
901 };
902
903 sdi5_per3@80008000 {
904 compatible = "arm,pl18x", "arm,primecell";
905 reg = <0x80008000 0x1000>;
906 interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
907
908 dmas = <&dma 43 0 0x2>, /* Logical - DevToMem */
909 <&dma 43 0 0x0>; /* Logical - MemToDev */
910 dma-names = "rx", "tx";
911
912 clocks = <&prcc_kclk 3 7>, <&prcc_pclk 3 7>;
913 clock-names = "sdi", "apb_pclk";
914
915 status = "disabled";
916 };
917
918 msp0: msp@80123000 {
919 compatible = "stericsson,ux500-msp-i2s";
920 reg = <0x80123000 0x1000>;
921 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
922 v-ape-supply = <&db8500_vape_reg>;
923
924 dmas = <&dma 31 0 0x12>, /* Logical - DevToMem - HighPrio */
925 <&dma 31 0 0x10>; /* Logical - MemToDev - HighPrio */
926 dma-names = "rx", "tx";
927
928 clocks = <&prcc_kclk 1 3>, <&prcc_pclk 1 3>;
929 clock-names = "msp", "apb_pclk";
930
931 status = "disabled";
932 };
933
934 msp1: msp@80124000 {
935 compatible = "stericsson,ux500-msp-i2s";
936 reg = <0x80124000 0x1000>;
937 interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>;
938 v-ape-supply = <&db8500_vape_reg>;
939
940 /* This DMA channel only exist on DB8500 v1 */
941 dmas = <&dma 30 0 0x10>; /* Logical - MemToDev - HighPrio */
942 dma-names = "tx";
943
944 clocks = <&prcc_kclk 1 4>, <&prcc_pclk 1 4>;
945 clock-names = "msp", "apb_pclk";
946
947 status = "disabled";
948 };
949
950 // HDMI sound
951 msp2: msp@80117000 {
952 compatible = "stericsson,ux500-msp-i2s";
953 reg = <0x80117000 0x1000>;
954 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
955 v-ape-supply = <&db8500_vape_reg>;
956
957 dmas = <&dma 14 0 0x12>, /* Logical - DevToMem - HighPrio */
958 <&dma 14 1 0x19>; /* Physical Chan 1 - MemToDev
959 HighPrio - Fixed */
960 dma-names = "rx", "tx";
961
962 clocks = <&prcc_kclk 2 3>, <&prcc_pclk 2 5>;
963 clock-names = "msp", "apb_pclk";
964
965 status = "disabled";
966 };
967
968 msp3: msp@80125000 {
969 compatible = "stericsson,ux500-msp-i2s";
970 reg = <0x80125000 0x1000>;
971 interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>;
972 v-ape-supply = <&db8500_vape_reg>;
973
974 /* This DMA channel only exist on DB8500 v2 */
975 dmas = <&dma 30 0 0x12>; /* Logical - DevToMem - HighPrio */
976 dma-names = "rx";
977
978 clocks = <&prcc_kclk 1 10>, <&prcc_pclk 1 11>;
979 clock-names = "msp", "apb_pclk";
980
981 status = "disabled";
982 };
983
984 external-bus@50000000 {
985 compatible = "simple-bus";
986 reg = <0x50000000 0x4000000>;
987 #address-cells = <1>;
988 #size-cells = <1>;
989 ranges = <0 0x50000000 0x4000000>;
990 status = "disabled";
991 };
992
993 cpufreq-cooling {
994 compatible = "stericsson,db8500-cpufreq-cooling";
995 status = "disabled";
996 };
997
998 vmmci: regulator-gpio {
999 compatible = "regulator-gpio";
1000
1001 regulator-min-microvolt = <1800000>;
1002 regulator-max-microvolt = <2900000>;
1003 regulator-name = "mmci-reg";
1004 regulator-type = "voltage";
1005
1006 startup-delay-us = <100>;
1007 enable-active-high;
1008
1009 states = <1800000 0x1
1010 2900000 0x0>;
1011
1012 status = "disabled";
1013 };
1014
1015 mcde@a0350000 {
1016 compatible = "stericsson,mcde";
1017 reg = <0xa0350000 0x1000>, /* MCDE */
1018 <0xa0351000 0x1000>, /* DSI link 1 */
1019 <0xa0352000 0x1000>, /* DSI link 2 */
1020 <0xa0353000 0x1000>; /* DSI link 3 */
1021 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
1022 clocks = <&prcmu_clk PRCMU_MCDECLK>, /* Main MCDE clock */
1023 <&prcmu_clk PRCMU_LCDCLK>, /* LCD clock */
1024 <&prcmu_clk PRCMU_PLLDSI>, /* HDMI clock */
1025 <&prcmu_clk PRCMU_DSI0CLK>, /* DSI 0 */
1026 <&prcmu_clk PRCMU_DSI1CLK>, /* DSI 1 */
1027 <&prcmu_clk PRCMU_DSI0ESCCLK>, /* TVout clock 0 */
1028 <&prcmu_clk PRCMU_DSI1ESCCLK>, /* TVout clock 1 */
1029 <&prcmu_clk PRCMU_DSI2ESCCLK>; /* TVout clock 2 */
1030 };
1031
1032 cryp@a03cb000 {
1033 compatible = "stericsson,ux500-cryp";
1034 reg = <0xa03cb000 0x1000>;
1035 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
1036
1037 v-ape-supply = <&db8500_vape_reg>;
1038 clocks = <&prcc_pclk 6 1>;
1039 };
1040
1041 hash@a03c2000 {
1042 compatible = "stericsson,ux500-hash";
1043 reg = <0xa03c2000 0x1000>;
1044
1045 v-ape-supply = <&db8500_vape_reg>;
1046 clocks = <&prcc_pclk 6 2>;
1047 };
1048 };
1049 };
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