2 * Copyright (C) 2014 STMicroelectronics R&D Limited
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 #include <dt-bindings/clock/stih407-clks.h>
16 * Fixed 30MHz oscillator inputs to SoC
18 clk_sysin: clk-sysin {
20 compatible = "fixed-clock";
21 clock-frequency = <30000000>;
25 * ARM Peripheral clock for timers
27 arm_periph_clk: arm-periph-clk {
29 compatible = "fixed-clock";
30 clock-frequency = <600000000>;
34 * Bootloader initialized system infrastructure clock for
37 clk_ext2f_a9: clockgen-c0@13 {
39 compatible = "fixed-clock";
40 clock-frequency = <200000000>;
41 clock-output-names = "clk-s-icn-reg-0";
45 compatible = "st,clkgen-c32";
46 reg = <0x90ff000 0x1000>;
48 clk_s_a0_pll: clk-s-a0-pll {
50 compatible = "st,stih407-plls-c32-a0", "st,clkgen-plls-c32";
52 clocks = <&clk_sysin>;
54 clock-output-names = "clk-s-a0-pll-ofd-0";
57 clk_s_a0_flexgen: clk-s-a0-flexgen {
58 compatible = "st,flexgen";
62 clocks = <&clk_s_a0_pll 0>,
65 clock-output-names = "clk-ic-lmi0";
69 clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
71 compatible = "st,stih407-quadfs660-C", "st,quadfs";
72 reg = <0x9103000 0x1000>;
74 clocks = <&clk_sysin>;
76 clock-output-names = "clk-s-c0-fs0-ch0",
82 clk_s_c0: clockgen-c@09103000 {
83 compatible = "st,clkgen-c32";
84 reg = <0x9103000 0x1000>;
86 clk_s_c0_pll0: clk-s-c0-pll0 {
88 compatible = "st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32";
90 clocks = <&clk_sysin>;
92 clock-output-names = "clk-s-c0-pll0-odf-0";
95 clk_s_c0_pll1: clk-s-c0-pll1 {
97 compatible = "st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32";
99 clocks = <&clk_sysin>;
101 clock-output-names = "clk-s-c0-pll1-odf-0";
104 clk_s_c0_flexgen: clk-s-c0-flexgen {
106 compatible = "st,flexgen";
108 clocks = <&clk_s_c0_pll0 0>,
110 <&clk_s_c0_quadfs 0>,
111 <&clk_s_c0_quadfs 1>,
112 <&clk_s_c0_quadfs 2>,
113 <&clk_s_c0_quadfs 3>,
116 clock-output-names = "clk-icn-gpu",
143 "clk-eth-ref-phyclk",
151 clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
153 compatible = "st,stih407-quadfs660-D", "st,quadfs";
154 reg = <0x9104000 0x1000>;
156 clocks = <&clk_sysin>;
158 clock-output-names = "clk-s-d0-fs0-ch0",
164 clockgen-d0@09104000 {
165 compatible = "st,clkgen-c32";
166 reg = <0x9104000 0x1000>;
168 clk_s_d0_flexgen: clk-s-d0-flexgen {
170 compatible = "st,flexgen";
172 clocks = <&clk_s_d0_quadfs 0>,
173 <&clk_s_d0_quadfs 1>,
174 <&clk_s_d0_quadfs 2>,
175 <&clk_s_d0_quadfs 3>,
178 clock-output-names = "clk-pcm-0",
185 clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
187 compatible = "st,stih407-quadfs660-D", "st,quadfs";
188 reg = <0x9106000 0x1000>;
190 clocks = <&clk_sysin>;
192 clock-output-names = "clk-s-d2-fs0-ch0",
198 clk_tmdsout_hdmi: clk-tmdsout-hdmi {
200 compatible = "fixed-clock";
201 clock-frequency = <0>;
204 clockgen-d2@x9106000 {
205 compatible = "st,clkgen-c32";
206 reg = <0x9106000 0x1000>;
208 clk_s_d2_flexgen: clk-s-d2-flexgen {
210 compatible = "st,flexgen";
212 clocks = <&clk_s_d2_quadfs 0>,
213 <&clk_s_d2_quadfs 1>,
214 <&clk_s_d2_quadfs 2>,
215 <&clk_s_d2_quadfs 3>,
220 clock-output-names = "clk-pix-main-disp",
239 clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
241 compatible = "st,stih407-quadfs660-D", "st,quadfs";
242 reg = <0x9107000 0x1000>;
244 clocks = <&clk_sysin>;
246 clock-output-names = "clk-s-d3-fs0-ch0",
252 clockgen-d3@9107000 {
253 compatible = "st,clkgen-c32";
254 reg = <0x9107000 0x1000>;
256 clk_s_d3_flexgen: clk-s-d3-flexgen {
258 compatible = "st,flexgen";
260 clocks = <&clk_s_d3_quadfs 0>,
261 <&clk_s_d3_quadfs 1>,
262 <&clk_s_d3_quadfs 2>,
263 <&clk_s_d3_quadfs 3>,
266 clock-output-names = "clk-stfe-frc1",