arch/arm/boot/dts/stih407-clock.dtsi

   1 /*
   2  * Copyright (C) 2014 STMicroelectronics R&D Limited
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8 #include <dt-bindings/clock/stih407-clks.h>
   9 / {
  10         /*
  11          * Fixed 30MHz oscillator inputs to SoC
  12          */
  13         clk_sysin: clk-sysin {
  14                 #clock-cells = <0>;
  15                 compatible = "fixed-clock";
  16                 clock-frequency = <30000000>;
  17         };
  18
  19         clk_tmdsout_hdmi: clk-tmdsout-hdmi {
  20                 #clock-cells = <0>;
  21                 compatible = "fixed-clock";
  22                 clock-frequency = <0>;
  23         };
  24
  25         clocks {
  26                 #address-cells = <1>;
  27                 #size-cells = <1>;
  28                 ranges;
  29
  30                 /*
  31                  * A9 PLL.
  32                  */
  33                 clockgen-a9@92b0000 {
  34                         compatible = "st,clkgen-c32";
  35                         reg = <0x92b0000 0xffff>;
  36
  37                         clockgen_a9_pll: clockgen-a9-pll {
  38                                 #clock-cells = <1>;
  39                                 compatible = "st,stih407-clkgen-plla9";
  40
  41                                 clocks = <&clk_sysin>;
  42
  43                                 clock-output-names = "clockgen-a9-pll-odf";
  44                         };
  45                 };
  46
  47                 /*
  48                  * ARM CPU related clocks.
  49                  */
  50                 clk_m_a9: clk-m-a9@92b0000 {
  51                         #clock-cells = <0>;
  52                         compatible = "st,stih407-clkgen-a9-mux";
  53                         reg = <0x92b0000 0x10000>;
  54
  55                         clocks = <&clockgen_a9_pll 0>,
  56                                  <&clockgen_a9_pll 0>,
  57                                  <&clk_s_c0_flexgen 13>,
  58                                  <&clk_m_a9_ext2f_div2>;
  59
  60
  61                         /*
  62                          * ARM Peripheral clock for timers
  63                          */
  64                         arm_periph_clk: clk-m-a9-periphs {
  65                                 #clock-cells = <0>;
  66                                 compatible = "fixed-factor-clock";
  67
  68                                 clocks = <&clk_m_a9>;
  69                                 clock-div = <2>;
  70                                 clock-mult = <1>;
  71                         };
  72                 };
  73
  74                 clockgen-a@90ff000 {
  75                         compatible = "st,clkgen-c32";
  76                         reg = <0x90ff000 0x1000>;
  77
  78                         clk_s_a0_pll: clk-s-a0-pll {
  79                                 #clock-cells = <1>;
  80                                 compatible = "st,clkgen-pll0";
  81
  82                                 clocks = <&clk_sysin>;
  83
  84                                 clock-output-names = "clk-s-a0-pll-ofd-0";
  85                                 clock-critical = <0>; /* clk-s-a0-pll-ofd-0 */
  86                         };
  87
  88                         clk_s_a0_flexgen: clk-s-a0-flexgen {
  89                                 compatible = "st,flexgen";
  90
  91                                 #clock-cells = <1>;
  92
  93                                 clocks = <&clk_s_a0_pll 0>,
  94                                          <&clk_sysin>;
  95
  96                                 clock-output-names = "clk-ic-lmi0";
  97                                 clock-critical = <CLK_IC_LMI0>;
  98                         };
  99                 };
 100
 101                 clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
 102                         #clock-cells = <1>;
 103                         compatible = "st,quadfs-pll";
 104                         reg = <0x9103000 0x1000>;
 105
 106                         clocks = <&clk_sysin>;
 107
 108                         clock-output-names = "clk-s-c0-fs0-ch0",
 109                                              "clk-s-c0-fs0-ch1",
 110                                              "clk-s-c0-fs0-ch2",
 111                                              "clk-s-c0-fs0-ch3";
 112                         clock-critical = <0>; /* clk-s-c0-fs0-ch0 */
 113                 };
 114
 115                 clk_s_c0: clockgen-c@9103000 {
 116                         compatible = "st,clkgen-c32";
 117                         reg = <0x9103000 0x1000>;
 118
 119                         clk_s_c0_pll0: clk-s-c0-pll0 {
 120                                 #clock-cells = <1>;
 121                                 compatible = "st,clkgen-pll0";
 122
 123                                 clocks = <&clk_sysin>;
 124
 125                                 clock-output-names = "clk-s-c0-pll0-odf-0";
 126                                 clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */
 127                         };
 128
 129                         clk_s_c0_pll1: clk-s-c0-pll1 {
 130                                 #clock-cells = <1>;
 131                                 compatible = "st,clkgen-pll1";
 132
 133                                 clocks = <&clk_sysin>;
 134
 135                                 clock-output-names = "clk-s-c0-pll1-odf-0";
 136                         };
 137
 138                         clk_s_c0_flexgen: clk-s-c0-flexgen {
 139                                 #clock-cells = <1>;
 140                                 compatible = "st,flexgen";
 141
 142                                 clocks = <&clk_s_c0_pll0 0>,
 143                                          <&clk_s_c0_pll1 0>,
 144                                          <&clk_s_c0_quadfs 0>,
 145                                          <&clk_s_c0_quadfs 1>,
 146                                          <&clk_s_c0_quadfs 2>,
 147                                          <&clk_s_c0_quadfs 3>,
 148                                          <&clk_sysin>;
 149
 150                                 clock-output-names = "clk-icn-gpu",
 151                                                      "clk-fdma",
 152                                                      "clk-nand",
 153                                                      "clk-hva",
 154                                                      "clk-proc-stfe",
 155                                                      "clk-proc-tp",
 156                                                      "clk-rx-icn-dmu",
 157                                                      "clk-rx-icn-hva",
 158                                                      "clk-icn-cpu",
 159                                                      "clk-tx-icn-dmu",
 160                                                      "clk-mmc-0",
 161                                                      "clk-mmc-1",
 162                                                      "clk-jpegdec",
 163                                                      "clk-ext2fa9",
 164                                                      "clk-ic-bdisp-0",
 165                                                      "clk-ic-bdisp-1",
 166                                                      "clk-pp-dmu",
 167                                                      "clk-vid-dmu",
 168                                                      "clk-dss-lpc",
 169                                                      "clk-st231-aud-0",
 170                                                      "clk-st231-gp-1",
 171                                                      "clk-st231-dmu",
 172                                                      "clk-icn-lmi",
 173                                                      "clk-tx-icn-disp-1",
 174                                                      "clk-icn-sbc",
 175                                                      "clk-stfe-frc2",
 176                                                      "clk-eth-phy",
 177                                                      "clk-eth-ref-phyclk",
 178                                                      "clk-flash-promip",
 179                                                      "clk-main-disp",
 180                                                      "clk-aux-disp",
 181                                                      "clk-compo-dvp";
 182                                 clock-critical = <CLK_PROC_STFE>,
 183                                                  <CLK_ICN_CPU>,
 184                                                  <CLK_TX_ICN_DMU>,
 185                                                  <CLK_EXT2F_A9>,
 186                                                  <CLK_ICN_LMI>,
 187                                                  <CLK_ICN_SBC>;
 188
 189                                 /*
 190                                  * ARM Peripheral clock for timers
 191                                  */
 192                                 clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
 193                                         #clock-cells = <0>;
 194                                         compatible = "fixed-factor-clock";
 195
 196                                         clocks = <&clk_s_c0_flexgen 13>;
 197
 198                                         clock-output-names = "clk-m-a9-ext2f-div2";
 199
 200                                         clock-div = <2>;
 201                                         clock-mult = <1>;
 202                                 };
 203                         };
 204                 };
 205
 206                 clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
 207                         #clock-cells = <1>;
 208                         compatible = "st,quadfs";
 209                         reg = <0x9104000 0x1000>;
 210
 211                         clocks = <&clk_sysin>;
 212
 213                         clock-output-names = "clk-s-d0-fs0-ch0",
 214                                              "clk-s-d0-fs0-ch1",
 215                                              "clk-s-d0-fs0-ch2",
 216                                              "clk-s-d0-fs0-ch3";
 217                 };
 218
 219                 clockgen-d0@9104000 {
 220                         compatible = "st,clkgen-c32";
 221                         reg = <0x9104000 0x1000>;
 222
 223                         clk_s_d0_flexgen: clk-s-d0-flexgen {
 224                                 #clock-cells = <1>;
 225                                 compatible = "st,flexgen-audio", "st,flexgen";
 226
 227                                 clocks = <&clk_s_d0_quadfs 0>,
 228                                          <&clk_s_d0_quadfs 1>,
 229                                          <&clk_s_d0_quadfs 2>,
 230                                          <&clk_s_d0_quadfs 3>,
 231                                          <&clk_sysin>;
 232
 233                                 clock-output-names = "clk-pcm-0",
 234                                                      "clk-pcm-1",
 235                                                      "clk-pcm-2",
 236                                                      "clk-spdiff";
 237                         };
 238                 };
 239
 240                 clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
 241                         #clock-cells = <1>;
 242                         compatible = "st,quadfs";
 243                         reg = <0x9106000 0x1000>;
 244
 245                         clocks = <&clk_sysin>;
 246
 247                         clock-output-names = "clk-s-d2-fs0-ch0",
 248                                              "clk-s-d2-fs0-ch1",
 249                                              "clk-s-d2-fs0-ch2",
 250                                              "clk-s-d2-fs0-ch3";
 251                 };
 252
 253                 clockgen-d2@9106000 {
 254                         compatible = "st,clkgen-c32";
 255                         reg = <0x9106000 0x1000>;
 256
 257                         clk_s_d2_flexgen: clk-s-d2-flexgen {
 258                                 #clock-cells = <1>;
 259                                 compatible = "st,flexgen-video", "st,flexgen";
 260
 261                                 clocks = <&clk_s_d2_quadfs 0>,
 262                                          <&clk_s_d2_quadfs 1>,
 263                                          <&clk_s_d2_quadfs 2>,
 264                                          <&clk_s_d2_quadfs 3>,
 265                                          <&clk_sysin>,
 266                                          <&clk_sysin>,
 267                                          <&clk_tmdsout_hdmi>;
 268
 269                                 clock-output-names = "clk-pix-main-disp",
 270                                                      "clk-pix-pip",
 271                                                      "clk-pix-gdp1",
 272                                                      "clk-pix-gdp2",
 273                                                      "clk-pix-gdp3",
 274                                                      "clk-pix-gdp4",
 275                                                      "clk-pix-aux-disp",
 276                                                      "clk-denc",
 277                                                      "clk-pix-hddac",
 278                                                      "clk-hddac",
 279                                                      "clk-sddac",
 280                                                      "clk-pix-dvo",
 281                                                      "clk-dvo",
 282                                                      "clk-pix-hdmi",
 283                                                      "clk-tmds-hdmi",
 284                                                      "clk-ref-hdmiphy";
 285                                                      };
 286                 };
 287
 288                 clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
 289                         #clock-cells = <1>;
 290                         compatible = "st,quadfs";
 291                         reg = <0x9107000 0x1000>;
 292
 293                         clocks = <&clk_sysin>;
 294
 295                         clock-output-names = "clk-s-d3-fs0-ch0",
 296                                              "clk-s-d3-fs0-ch1",
 297                                              "clk-s-d3-fs0-ch2",
 298                                              "clk-s-d3-fs0-ch3";
 299                 };
 300
 301                 clockgen-d3@9107000 {
 302                         compatible = "st,clkgen-c32";
 303                         reg = <0x9107000 0x1000>;
 304
 305                         clk_s_d3_flexgen: clk-s-d3-flexgen {
 306                                 #clock-cells = <1>;
 307                                 compatible = "st,flexgen";
 308
 309                                 clocks = <&clk_s_d3_quadfs 0>,
 310                                          <&clk_s_d3_quadfs 1>,
 311                                          <&clk_s_d3_quadfs 2>,
 312                                          <&clk_s_d3_quadfs 3>,
 313                                          <&clk_sysin>;
 314
 315                                 clock-output-names = "clk-stfe-frc1",
 316                                                      "clk-tsout-0",
 317                                                      "clk-tsout-1",
 318                                                      "clk-mchi",
 319                                                      "clk-vsens-compo",
 320                                                      "clk-frc1-remote",
 321                                                      "clk-lpc-0",
 322                                                      "clk-lpc-1";
 323                         };
 324                 };
 325         };
 326 };