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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
[mirror_ubuntu-zesty-kernel.git] / arch / arm / boot / dts / stih407-family.dtsi
1 /*
2 * Copyright (C) 2014 STMicroelectronics Limited.
3 * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9 #include "stih407-pinctrl.dtsi"
10 #include <dt-bindings/mfd/st-lpc.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/reset/stih407-resets.h>
13 #include <dt-bindings/interrupt-controller/irq-st.h>
14 / {
15 #address-cells = <1>;
16 #size-cells = <1>;
17
18 reserved-memory {
19 #address-cells = <1>;
20 #size-cells = <1>;
21 ranges;
22
23 gp0_reserved: rproc@40000000 {
24 compatible = "shared-dma-pool";
25 reg = <0x40000000 0x01000000>;
26 no-map;
27 status = "disabled";
28 };
29
30 gp1_reserved: rproc@41000000 {
31 compatible = "shared-dma-pool";
32 reg = <0x41000000 0x01000000>;
33 no-map;
34 status = "disabled";
35 };
36
37 audio_reserved: rproc@42000000 {
38 compatible = "shared-dma-pool";
39 reg = <0x42000000 0x01000000>;
40 no-map;
41 status = "disabled";
42 };
43
44 dmu_reserved: rproc@43000000 {
45 compatible = "shared-dma-pool";
46 reg = <0x43000000 0x01000000>;
47 no-map;
48 };
49 };
50
51 cpus {
52 #address-cells = <1>;
53 #size-cells = <0>;
54 cpu@0 {
55 device_type = "cpu";
56 compatible = "arm,cortex-a9";
57 reg = <0>;
58
59 /* u-boot puts hpen in SBC dmem at 0xa4 offset */
60 cpu-release-addr = <0x94100A4>;
61
62 /* kHz uV */
63 operating-points = <1500000 0
64 1200000 0
65 800000 0
66 500000 0>;
67
68 clocks = <&clk_m_a9>;
69 clock-names = "cpu";
70 clock-latency = <100000>;
71 cpu0-supply = <&pwm_regulator>;
72 st,syscfg = <&syscfg_core 0x8e0>;
73 };
74 cpu@1 {
75 device_type = "cpu";
76 compatible = "arm,cortex-a9";
77 reg = <1>;
78
79 /* u-boot puts hpen in SBC dmem at 0xa4 offset */
80 cpu-release-addr = <0x94100A4>;
81
82 /* kHz uV */
83 operating-points = <1500000 0
84 1200000 0
85 800000 0
86 500000 0>;
87 };
88 };
89
90 intc: interrupt-controller@08761000 {
91 compatible = "arm,cortex-a9-gic";
92 #interrupt-cells = <3>;
93 interrupt-controller;
94 reg = <0x08761000 0x1000>, <0x08760100 0x100>;
95 };
96
97 scu@08760000 {
98 compatible = "arm,cortex-a9-scu";
99 reg = <0x08760000 0x1000>;
100 };
101
102 timer@08760200 {
103 interrupt-parent = <&intc>;
104 compatible = "arm,cortex-a9-global-timer";
105 reg = <0x08760200 0x100>;
106 interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
107 clocks = <&arm_periph_clk>;
108 };
109
110 l2: cache-controller {
111 compatible = "arm,pl310-cache";
112 reg = <0x08762000 0x1000>;
113 arm,data-latency = <3 3 3>;
114 arm,tag-latency = <2 2 2>;
115 cache-unified;
116 cache-level = <2>;
117 };
118
119 arm-pmu {
120 interrupt-parent = <&intc>;
121 compatible = "arm,cortex-a9-pmu";
122 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
123 };
124
125 pwm_regulator: pwm-regulator {
126 compatible = "pwm-regulator";
127 pwms = <&pwm1 3 8448>;
128 regulator-name = "CPU_1V0_AVS";
129 regulator-min-microvolt = <784000>;
130 regulator-max-microvolt = <1299000>;
131 regulator-always-on;
132 max-duty-cycle = <255>;
133 status = "okay";
134 };
135
136 soc {
137 #address-cells = <1>;
138 #size-cells = <1>;
139 interrupt-parent = <&intc>;
140 ranges;
141 compatible = "simple-bus";
142
143 restart {
144 compatible = "st,stih407-restart";
145 st,syscfg = <&syscfg_sbc_reg>;
146 status = "okay";
147 };
148
149 powerdown: powerdown-controller {
150 compatible = "st,stih407-powerdown";
151 #reset-cells = <1>;
152 };
153
154 softreset: softreset-controller {
155 compatible = "st,stih407-softreset";
156 #reset-cells = <1>;
157 };
158
159 picophyreset: picophyreset-controller {
160 compatible = "st,stih407-picophyreset";
161 #reset-cells = <1>;
162 };
163
164 syscfg_sbc: sbc-syscfg@9620000 {
165 compatible = "st,stih407-sbc-syscfg", "syscon";
166 reg = <0x9620000 0x1000>;
167 };
168
169 syscfg_front: front-syscfg@9280000 {
170 compatible = "st,stih407-front-syscfg", "syscon";
171 reg = <0x9280000 0x1000>;
172 };
173
174 syscfg_rear: rear-syscfg@9290000 {
175 compatible = "st,stih407-rear-syscfg", "syscon";
176 reg = <0x9290000 0x1000>;
177 };
178
179 syscfg_flash: flash-syscfg@92a0000 {
180 compatible = "st,stih407-flash-syscfg", "syscon";
181 reg = <0x92a0000 0x1000>;
182 };
183
184 syscfg_sbc_reg: fvdp-lite-syscfg@9600000 {
185 compatible = "st,stih407-sbc-reg-syscfg", "syscon";
186 reg = <0x9600000 0x1000>;
187 };
188
189 syscfg_core: core-syscfg@92b0000 {
190 compatible = "st,stih407-core-syscfg", "syscon";
191 reg = <0x92b0000 0x1000>;
192 };
193
194 syscfg_lpm: lpm-syscfg@94b5100 {
195 compatible = "st,stih407-lpm-syscfg", "syscon";
196 reg = <0x94b5100 0x1000>;
197 };
198
199 irq-syscfg {
200 compatible = "st,stih407-irq-syscfg";
201 st,syscfg = <&syscfg_core>;
202 st,irq-device = <ST_IRQ_SYSCFG_PMU_0>,
203 <ST_IRQ_SYSCFG_PMU_1>;
204 st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>,
205 <ST_IRQ_SYSCFG_DISABLED>;
206 };
207
208 /* Display */
209 vtg_main: sti-vtg-main@8d02800 {
210 compatible = "st,vtg";
211 reg = <0x8d02800 0x200>;
212 interrupts = <GIC_SPI 108 IRQ_TYPE_NONE>;
213 };
214
215 vtg_aux: sti-vtg-aux@8d00200 {
216 compatible = "st,vtg";
217 reg = <0x8d00200 0x100>;
218 interrupts = <GIC_SPI 109 IRQ_TYPE_NONE>;
219 };
220
221 serial@9830000 {
222 compatible = "st,asc";
223 reg = <0x9830000 0x2c>;
224 interrupts = <GIC_SPI 122 IRQ_TYPE_NONE>;
225 pinctrl-names = "default";
226 pinctrl-0 = <&pinctrl_serial0>;
227 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
228
229 status = "disabled";
230 };
231
232 serial@9831000 {
233 compatible = "st,asc";
234 reg = <0x9831000 0x2c>;
235 interrupts = <GIC_SPI 123 IRQ_TYPE_NONE>;
236 pinctrl-names = "default";
237 pinctrl-0 = <&pinctrl_serial1>;
238 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
239
240 status = "disabled";
241 };
242
243 serial@9832000 {
244 compatible = "st,asc";
245 reg = <0x9832000 0x2c>;
246 interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>;
247 pinctrl-names = "default";
248 pinctrl-0 = <&pinctrl_serial2>;
249 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
250
251 status = "disabled";
252 };
253
254 /* SBC_ASC0 - UART10 */
255 sbc_serial0: serial@9530000 {
256 compatible = "st,asc";
257 reg = <0x9530000 0x2c>;
258 interrupts = <GIC_SPI 138 IRQ_TYPE_NONE>;
259 pinctrl-names = "default";
260 pinctrl-0 = <&pinctrl_sbc_serial0>;
261 clocks = <&clk_sysin>;
262
263 status = "disabled";
264 };
265
266 serial@9531000 {
267 compatible = "st,asc";
268 reg = <0x9531000 0x2c>;
269 interrupts = <GIC_SPI 139 IRQ_TYPE_NONE>;
270 pinctrl-names = "default";
271 pinctrl-0 = <&pinctrl_sbc_serial1>;
272 clocks = <&clk_sysin>;
273
274 status = "disabled";
275 };
276
277 i2c@9840000 {
278 compatible = "st,comms-ssc4-i2c";
279 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
280 reg = <0x9840000 0x110>;
281 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
282 clock-names = "ssc";
283 clock-frequency = <400000>;
284 pinctrl-names = "default";
285 pinctrl-0 = <&pinctrl_i2c0_default>;
286 #address-cells = <1>;
287 #size-cells = <0>;
288
289 status = "disabled";
290 };
291
292 i2c@9841000 {
293 compatible = "st,comms-ssc4-i2c";
294 reg = <0x9841000 0x110>;
295 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
296 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
297 clock-names = "ssc";
298 clock-frequency = <400000>;
299 pinctrl-names = "default";
300 pinctrl-0 = <&pinctrl_i2c1_default>;
301 #address-cells = <1>;
302 #size-cells = <0>;
303
304 status = "disabled";
305 };
306
307 i2c@9842000 {
308 compatible = "st,comms-ssc4-i2c";
309 reg = <0x9842000 0x110>;
310 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
311 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
312 clock-names = "ssc";
313 clock-frequency = <400000>;
314 pinctrl-names = "default";
315 pinctrl-0 = <&pinctrl_i2c2_default>;
316 #address-cells = <1>;
317 #size-cells = <0>;
318
319 status = "disabled";
320 };
321
322 i2c@9843000 {
323 compatible = "st,comms-ssc4-i2c";
324 reg = <0x9843000 0x110>;
325 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
326 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
327 clock-names = "ssc";
328 clock-frequency = <400000>;
329 pinctrl-names = "default";
330 pinctrl-0 = <&pinctrl_i2c3_default>;
331 #address-cells = <1>;
332 #size-cells = <0>;
333
334 status = "disabled";
335 };
336
337 i2c@9844000 {
338 compatible = "st,comms-ssc4-i2c";
339 reg = <0x9844000 0x110>;
340 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
341 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
342 clock-names = "ssc";
343 clock-frequency = <400000>;
344 pinctrl-names = "default";
345 pinctrl-0 = <&pinctrl_i2c4_default>;
346 #address-cells = <1>;
347 #size-cells = <0>;
348
349 status = "disabled";
350 };
351
352 i2c@9845000 {
353 compatible = "st,comms-ssc4-i2c";
354 reg = <0x9845000 0x110>;
355 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
356 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
357 clock-names = "ssc";
358 clock-frequency = <400000>;
359 pinctrl-names = "default";
360 pinctrl-0 = <&pinctrl_i2c5_default>;
361 #address-cells = <1>;
362 #size-cells = <0>;
363
364 status = "disabled";
365 };
366
367
368 /* SSCs on SBC */
369 i2c@9540000 {
370 compatible = "st,comms-ssc4-i2c";
371 reg = <0x9540000 0x110>;
372 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
373 clocks = <&clk_sysin>;
374 clock-names = "ssc";
375 clock-frequency = <400000>;
376 pinctrl-names = "default";
377 pinctrl-0 = <&pinctrl_i2c10_default>;
378 #address-cells = <1>;
379 #size-cells = <0>;
380
381 status = "disabled";
382 };
383
384 i2c@9541000 {
385 compatible = "st,comms-ssc4-i2c";
386 reg = <0x9541000 0x110>;
387 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
388 clocks = <&clk_sysin>;
389 clock-names = "ssc";
390 clock-frequency = <400000>;
391 pinctrl-names = "default";
392 pinctrl-0 = <&pinctrl_i2c11_default>;
393 #address-cells = <1>;
394 #size-cells = <0>;
395
396 status = "disabled";
397 };
398
399 usb2_picophy0: phy1 {
400 compatible = "st,stih407-usb2-phy";
401 #phy-cells = <0>;
402 st,syscfg = <&syscfg_core 0x100 0xf4>;
403 resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
404 <&picophyreset STIH407_PICOPHY2_RESET>;
405 reset-names = "global", "port";
406 };
407
408 miphy28lp_phy: miphy28lp@9b22000 {
409 compatible = "st,miphy28lp-phy";
410 st,syscfg = <&syscfg_core>;
411 #address-cells = <1>;
412 #size-cells = <1>;
413 ranges;
414
415 phy_port0: port@9b22000 {
416 reg = <0x9b22000 0xff>,
417 <0x9b09000 0xff>,
418 <0x9b04000 0xff>;
419 reg-names = "sata-up",
420 "pcie-up",
421 "pipew";
422
423 st,syscfg = <0x114 0x818 0xe0 0xec>;
424 #phy-cells = <1>;
425
426 reset-names = "miphy-sw-rst";
427 resets = <&softreset STIH407_MIPHY0_SOFTRESET>;
428 };
429
430 phy_port1: port@9b2a000 {
431 reg = <0x9b2a000 0xff>,
432 <0x9b19000 0xff>,
433 <0x9b14000 0xff>;
434 reg-names = "sata-up",
435 "pcie-up",
436 "pipew";
437
438 st,syscfg = <0x118 0x81c 0xe4 0xf0>;
439
440 #phy-cells = <1>;
441
442 reset-names = "miphy-sw-rst";
443 resets = <&softreset STIH407_MIPHY1_SOFTRESET>;
444 };
445
446 phy_port2: port@8f95000 {
447 reg = <0x8f95000 0xff>,
448 <0x8f90000 0xff>;
449 reg-names = "pipew",
450 "usb3-up";
451
452 st,syscfg = <0x11c 0x820>;
453
454 #phy-cells = <1>;
455
456 reset-names = "miphy-sw-rst";
457 resets = <&softreset STIH407_MIPHY2_SOFTRESET>;
458 };
459 };
460
461 spi@9840000 {
462 compatible = "st,comms-ssc4-spi";
463 reg = <0x9840000 0x110>;
464 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
465 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
466 clock-names = "ssc";
467 pinctrl-0 = <&pinctrl_spi0_default>;
468 pinctrl-names = "default";
469 #address-cells = <1>;
470 #size-cells = <0>;
471
472 status = "disabled";
473 };
474
475 spi@9841000 {
476 compatible = "st,comms-ssc4-spi";
477 reg = <0x9841000 0x110>;
478 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
479 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
480 clock-names = "ssc";
481 pinctrl-names = "default";
482 pinctrl-0 = <&pinctrl_spi1_default>;
483
484 status = "disabled";
485 };
486
487 spi@9842000 {
488 compatible = "st,comms-ssc4-spi";
489 reg = <0x9842000 0x110>;
490 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
491 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
492 clock-names = "ssc";
493 pinctrl-names = "default";
494 pinctrl-0 = <&pinctrl_spi2_default>;
495
496 status = "disabled";
497 };
498
499 spi@9843000 {
500 compatible = "st,comms-ssc4-spi";
501 reg = <0x9843000 0x110>;
502 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
503 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
504 clock-names = "ssc";
505 pinctrl-names = "default";
506 pinctrl-0 = <&pinctrl_spi3_default>;
507
508 status = "disabled";
509 };
510
511 spi@9844000 {
512 compatible = "st,comms-ssc4-spi";
513 reg = <0x9844000 0x110>;
514 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
515 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
516 clock-names = "ssc";
517 pinctrl-names = "default";
518 pinctrl-0 = <&pinctrl_spi4_default>;
519
520 status = "disabled";
521 };
522
523 /* SBC SSC */
524 spi@9540000 {
525 compatible = "st,comms-ssc4-spi";
526 reg = <0x9540000 0x110>;
527 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
528 clocks = <&clk_sysin>;
529 clock-names = "ssc";
530 pinctrl-names = "default";
531 pinctrl-0 = <&pinctrl_spi10_default>;
532
533 status = "disabled";
534 };
535
536 spi@9541000 {
537 compatible = "st,comms-ssc4-spi";
538 reg = <0x9541000 0x110>;
539 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
540 clocks = <&clk_sysin>;
541 clock-names = "ssc";
542 pinctrl-names = "default";
543 pinctrl-0 = <&pinctrl_spi11_default>;
544
545 status = "disabled";
546 };
547
548 spi@9542000 {
549 compatible = "st,comms-ssc4-spi";
550 reg = <0x9542000 0x110>;
551 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
552 clocks = <&clk_sysin>;
553 clock-names = "ssc";
554 pinctrl-names = "default";
555 pinctrl-0 = <&pinctrl_spi12_default>;
556
557 status = "disabled";
558 };
559
560 mmc0: sdhci@09060000 {
561 compatible = "st,sdhci-stih407", "st,sdhci";
562 status = "disabled";
563 reg = <0x09060000 0x7ff>, <0x9061008 0x20>;
564 reg-names = "mmc", "top-mmc-delay";
565 interrupts = <GIC_SPI 92 IRQ_TYPE_NONE>;
566 interrupt-names = "mmcirq";
567 pinctrl-names = "default";
568 pinctrl-0 = <&pinctrl_mmc0>;
569 clock-names = "mmc", "icn";
570 clocks = <&clk_s_c0_flexgen CLK_MMC_0>,
571 <&clk_s_c0_flexgen CLK_RX_ICN_HVA>;
572 bus-width = <8>;
573 };
574
575 mmc1: sdhci@09080000 {
576 compatible = "st,sdhci-stih407", "st,sdhci";
577 status = "disabled";
578 reg = <0x09080000 0x7ff>;
579 reg-names = "mmc";
580 interrupts = <GIC_SPI 90 IRQ_TYPE_NONE>;
581 interrupt-names = "mmcirq";
582 pinctrl-names = "default";
583 pinctrl-0 = <&pinctrl_sd1>;
584 clock-names = "mmc", "icn";
585 clocks = <&clk_s_c0_flexgen CLK_MMC_1>,
586 <&clk_s_c0_flexgen CLK_RX_ICN_HVA>;
587 resets = <&softreset STIH407_MMC1_SOFTRESET>;
588 bus-width = <4>;
589 };
590
591 /* Watchdog and Real-Time Clock */
592 lpc@8787000 {
593 compatible = "st,stih407-lpc";
594 reg = <0x8787000 0x1000>;
595 interrupts = <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>;
596 clocks = <&clk_s_d3_flexgen CLK_LPC_0>;
597 timeout-sec = <120>;
598 st,syscfg = <&syscfg_core>;
599 st,lpc-mode = <ST_LPC_MODE_WDT>;
600 };
601
602 lpc@8788000 {
603 compatible = "st,stih407-lpc";
604 reg = <0x8788000 0x1000>;
605 interrupts = <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>;
606 clocks = <&clk_s_d3_flexgen CLK_LPC_1>;
607 st,lpc-mode = <ST_LPC_MODE_CLKSRC>;
608 };
609
610 sata0: sata@9b20000 {
611 compatible = "st,ahci";
612 reg = <0x9b20000 0x1000>;
613
614 interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>;
615 interrupt-names = "hostc";
616
617 phys = <&phy_port0 PHY_TYPE_SATA>;
618 phy-names = "ahci_phy";
619
620 resets = <&powerdown STIH407_SATA0_POWERDOWN>,
621 <&softreset STIH407_SATA0_SOFTRESET>,
622 <&softreset STIH407_SATA0_PWR_SOFTRESET>;
623 reset-names = "pwr-dwn", "sw-rst", "pwr-rst";
624
625 clock-names = "ahci_clk";
626 clocks = <&clk_s_c0_flexgen CLK_ICN_REG>;
627
628 ports-implemented = <0x1>;
629
630 status = "disabled";
631 };
632
633 sata1: sata@9b28000 {
634 compatible = "st,ahci";
635 reg = <0x9b28000 0x1000>;
636
637 interrupts = <GIC_SPI 170 IRQ_TYPE_NONE>;
638 interrupt-names = "hostc";
639
640 phys = <&phy_port1 PHY_TYPE_SATA>;
641 phy-names = "ahci_phy";
642
643 resets = <&powerdown STIH407_SATA1_POWERDOWN>,
644 <&softreset STIH407_SATA1_SOFTRESET>,
645 <&softreset STIH407_SATA1_PWR_SOFTRESET>;
646 reset-names = "pwr-dwn",
647 "sw-rst",
648 "pwr-rst";
649
650 clock-names = "ahci_clk";
651 clocks = <&clk_s_c0_flexgen CLK_ICN_REG>;
652
653 ports-implemented = <0x1>;
654
655 status = "disabled";
656 };
657
658
659 st_dwc3: dwc3@8f94000 {
660 compatible = "st,stih407-dwc3";
661 reg = <0x08f94000 0x1000>, <0x110 0x4>;
662 reg-names = "reg-glue", "syscfg-reg";
663 st,syscfg = <&syscfg_core>;
664 resets = <&powerdown STIH407_USB3_POWERDOWN>,
665 <&softreset STIH407_MIPHY2_SOFTRESET>;
666 reset-names = "powerdown", "softreset";
667 #address-cells = <1>;
668 #size-cells = <1>;
669 pinctrl-names = "default";
670 pinctrl-0 = <&pinctrl_usb3>;
671 ranges;
672
673 status = "disabled";
674
675 dwc3: dwc3@9900000 {
676 compatible = "snps,dwc3";
677 reg = <0x09900000 0x100000>;
678 interrupts = <GIC_SPI 155 IRQ_TYPE_NONE>;
679 dr_mode = "host";
680 phy-names = "usb2-phy", "usb3-phy";
681 phys = <&usb2_picophy0>,
682 <&phy_port2 PHY_TYPE_USB3>;
683 };
684 };
685
686 /* COMMS PWM Module */
687 pwm0: pwm@9810000 {
688 compatible = "st,sti-pwm";
689 #pwm-cells = <2>;
690 reg = <0x9810000 0x68>;
691 interrupts = <GIC_SPI 128 IRQ_TYPE_NONE>;
692 pinctrl-names = "default";
693 pinctrl-0 = <&pinctrl_pwm0_chan0_default>;
694 clock-names = "pwm";
695 clocks = <&clk_sysin>;
696 st,pwm-num-chan = <1>;
697
698 status = "disabled";
699 };
700
701 /* SBC PWM Module */
702 pwm1: pwm@9510000 {
703 compatible = "st,sti-pwm";
704 #pwm-cells = <2>;
705 reg = <0x9510000 0x68>;
706 pinctrl-names = "default";
707 pinctrl-0 = <&pinctrl_pwm1_chan0_default
708 &pinctrl_pwm1_chan1_default
709 &pinctrl_pwm1_chan2_default
710 &pinctrl_pwm1_chan3_default>;
711 clock-names = "pwm";
712 clocks = <&clk_sysin>;
713 st,pwm-num-chan = <4>;
714
715 status = "disabled";
716 };
717
718 rng10: rng@08a89000 {
719 compatible = "st,rng";
720 reg = <0x08a89000 0x1000>;
721 clocks = <&clk_sysin>;
722 status = "okay";
723 };
724
725 rng11: rng@08a8a000 {
726 compatible = "st,rng";
727 reg = <0x08a8a000 0x1000>;
728 clocks = <&clk_sysin>;
729 status = "okay";
730 };
731
732 ethernet0: dwmac@9630000 {
733 device_type = "network";
734 status = "disabled";
735 compatible = "st,stih407-dwmac", "snps,dwmac", "snps,dwmac-3.710";
736 reg = <0x9630000 0x8000>, <0x80 0x4>;
737 reg-names = "stmmaceth", "sti-ethconf";
738
739 st,syscon = <&syscfg_sbc_reg 0x80>;
740 st,gmac_en;
741 resets = <&softreset STIH407_ETH1_SOFTRESET>;
742 reset-names = "stmmaceth";
743
744 interrupts = <GIC_SPI 98 IRQ_TYPE_NONE>,
745 <GIC_SPI 99 IRQ_TYPE_NONE>;
746 interrupt-names = "macirq", "eth_wake_irq";
747
748 /* DMA Bus Mode */
749 snps,pbl = <8>;
750
751 pinctrl-names = "default";
752 pinctrl-0 = <&pinctrl_rgmii1>;
753
754 clock-names = "stmmaceth", "sti-ethclk";
755 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>,
756 <&clk_s_c0_flexgen CLK_ETH_PHY>;
757 };
758
759 cec: sti-cec@094a087c {
760 compatible = "st,stih-cec";
761 reg = <0x94a087c 0x64>;
762 clocks = <&clk_sysin>;
763 clock-names = "cec-clk";
764 interrupts = <GIC_SPI 140 IRQ_TYPE_NONE>;
765 interrupt-names = "cec-irq";
766 pinctrl-names = "default";
767 pinctrl-0 = <&pinctrl_cec0_default>;
768 resets = <&softreset STIH407_LPM_SOFTRESET>;
769 };
770
771 rng10: rng@08a89000 {
772 compatible = "st,rng";
773 reg = <0x08a89000 0x1000>;
774 clocks = <&clk_sysin>;
775 status = "okay";
776 };
777
778 rng11: rng@08a8a000 {
779 compatible = "st,rng";
780 reg = <0x08a8a000 0x1000>;
781 clocks = <&clk_sysin>;
782 status = "okay";
783 };
784
785 mailbox0: mailbox@8f00000 {
786 compatible = "st,stih407-mailbox";
787 reg = <0x8f00000 0x1000>;
788 interrupts = <GIC_SPI 1 IRQ_TYPE_NONE>;
789 #mbox-cells = <2>;
790 mbox-name = "a9";
791 status = "okay";
792 };
793
794 mailbox1: mailbox@8f01000 {
795 compatible = "st,stih407-mailbox";
796 reg = <0x8f01000 0x1000>;
797 #mbox-cells = <2>;
798 mbox-name = "st231_gp_1";
799 status = "okay";
800 };
801
802 mailbox2: mailbox@8f02000 {
803 compatible = "st,stih407-mailbox";
804 reg = <0x8f02000 0x1000>;
805 #mbox-cells = <2>;
806 mbox-name = "st231_gp_0";
807 status = "okay";
808 };
809
810 mailbox3: mailbox@8f03000 {
811 compatible = "st,stih407-mailbox";
812 reg = <0x8f03000 0x1000>;
813 #mbox-cells = <2>;
814 mbox-name = "st231_audio_video";
815 status = "okay";
816 };
817
818 st231_gp0: remote-processor {
819 compatible = "st,st231-rproc";
820 memory-region = <&gp0_reserved>;
821 resets = <&softreset STIH407_ST231_GP0_SOFTRESET>;
822 reset-names = "sw_reset";
823 clocks = <&clk_s_c0_flexgen CLK_ST231_GP_0>;
824 clock-frequency = <600000000>;
825 st,syscfg = <&syscfg_core 0x22c>;
826 };
827
828
829 st231_gp1: remote-processor {
830 compatible = "st,st231-rproc";
831 memory-region = <&gp1_reserved>;
832 resets = <&softreset STIH407_ST231_GP1_SOFTRESET>;
833 reset-names = "sw_reset";
834 clocks = <&clk_s_c0_flexgen CLK_ST231_GP_1>;
835 clock-frequency = <600000000>;
836 st,syscfg = <&syscfg_core 0x220>;
837 };
838
839 st231_audio: remote-processor {
840 compatible = "st,st231-rproc";
841 memory-region = <&audio_reserved>;
842 resets = <&softreset STIH407_ST231_AUD_SOFTRESET>;
843 reset-names = "sw_reset";
844 clocks = <&clk_s_c0_flexgen CLK_ST231_AUD_0>;
845 clock-frequency = <600000000>;
846 st,syscfg = <&syscfg_core 0x228>;
847 };
848
849 st231_dmu: remote-processor {
850 compatible = "st,st231-rproc";
851 memory-region = <&dmu_reserved>;
852 resets = <&softreset STIH407_ST231_DMU_SOFTRESET>;
853 reset-names = "sw_reset";
854 clocks = <&clk_s_c0_flexgen CLK_ST231_DMU>;
855 clock-frequency = <600000000>;
856 st,syscfg = <&syscfg_core 0x224>;
857 };
858
859 /* fdma audio */
860 fdma0: dma-controller@8e20000 {
861 compatible = "st,stih407-fdma-mpe31-11", "st,slim-rproc";
862 reg = <0x8e20000 0x8000>,
863 <0x8e30000 0x3000>,
864 <0x8e37000 0x1000>,
865 <0x8e38000 0x8000>;
866 reg-names = "slimcore", "dmem", "peripherals", "imem";
867 clocks = <&clk_s_c0_flexgen CLK_FDMA>,
868 <&clk_s_c0_flexgen CLK_EXT2F_A9>,
869 <&clk_s_c0_flexgen CLK_EXT2F_A9>,
870 <&clk_s_c0_flexgen CLK_EXT2F_A9>;
871 interrupts = <GIC_SPI 5 IRQ_TYPE_NONE>;
872 dma-channels = <16>;
873 #dma-cells = <3>;
874 };
875
876 /* fdma app */
877 fdma1: dma-controller@8e40000 {
878 compatible = "st,stih407-fdma-mpe31-12", "st,slim-rproc";
879 reg = <0x8e40000 0x8000>,
880 <0x8e50000 0x3000>,
881 <0x8e57000 0x1000>,
882 <0x8e58000 0x8000>;
883 reg-names = "slimcore", "dmem", "peripherals", "imem";
884 clocks = <&clk_s_c0_flexgen CLK_FDMA>,
885 <&clk_s_c0_flexgen CLK_TX_ICN_DMU>,
886 <&clk_s_c0_flexgen CLK_TX_ICN_DMU>,
887 <&clk_s_c0_flexgen CLK_EXT2F_A9>;
888
889 interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>;
890 dma-channels = <16>;
891 #dma-cells = <3>;
892 };
893
894 /* fdma free running */
895 fdma2: dma-controller@8e60000 {
896 compatible = "st,stih407-fdma-mpe31-13", "st,slim-rproc";
897 reg = <0x8e60000 0x8000>,
898 <0x8e70000 0x3000>,
899 <0x8e77000 0x1000>,
900 <0x8e78000 0x8000>;
901 reg-names = "slimcore", "dmem", "peripherals", "imem";
902 interrupts = <GIC_SPI 9 IRQ_TYPE_NONE>;
903 dma-channels = <16>;
904 #dma-cells = <3>;
905 clocks = <&clk_s_c0_flexgen CLK_FDMA>,
906 <&clk_s_c0_flexgen CLK_EXT2F_A9>,
907 <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
908 <&clk_s_c0_flexgen CLK_EXT2F_A9>;
909 };
910
911 sti_sasg_codec: sti-sasg-codec {
912 compatible = "st,stih407-sas-codec";
913 #sound-dai-cells = <1>;
914 status = "disabled";
915 st,syscfg = <&syscfg_core>;
916 };
917
918 sti_uni_player0: sti-uni-player@8d80000 {
919 compatible = "st,stih407-uni-player-hdmi";
920 #sound-dai-cells = <0>;
921 st,syscfg = <&syscfg_core>;
922 clocks = <&clk_s_d0_flexgen CLK_PCM_0>;
923 assigned-clocks = <&clk_s_d0_quadfs 0>, <&clk_s_d0_flexgen CLK_PCM_0>;
924 assigned-clock-parents = <0>, <&clk_s_d0_quadfs 0>;
925 assigned-clock-rates = <50000000>;
926 reg = <0x8d80000 0x158>;
927 interrupts = <GIC_SPI 84 IRQ_TYPE_NONE>;
928 dmas = <&fdma0 2 0 1>;
929 dma-names = "tx";
930
931 status = "disabled";
932 };
933
934 sti_uni_player1: sti-uni-player@8d81000 {
935 compatible = "st,stih407-uni-player-pcm-out";
936 #sound-dai-cells = <0>;
937 st,syscfg = <&syscfg_core>;
938 clocks = <&clk_s_d0_flexgen CLK_PCM_1>;
939 assigned-clocks = <&clk_s_d0_quadfs 1>, <&clk_s_d0_flexgen CLK_PCM_1>;
940 assigned-clock-parents = <0>, <&clk_s_d0_quadfs 1>;
941 assigned-clock-rates = <50000000>;
942 reg = <0x8d81000 0x158>;
943 interrupts = <GIC_SPI 85 IRQ_TYPE_NONE>;
944 dmas = <&fdma0 3 0 1>;
945 dma-names = "tx";
946
947 status = "disabled";
948 };
949
950 sti_uni_player2: sti-uni-player@8d82000 {
951 compatible = "st,stih407-uni-player-dac";
952 #sound-dai-cells = <0>;
953 st,syscfg = <&syscfg_core>;
954 clocks = <&clk_s_d0_flexgen CLK_PCM_2>;
955 assigned-clocks = <&clk_s_d0_quadfs 2>, <&clk_s_d0_flexgen CLK_PCM_2>;
956 assigned-clock-parents = <0>, <&clk_s_d0_quadfs 2>;
957 assigned-clock-rates = <50000000>;
958 reg = <0x8d82000 0x158>;
959 interrupts = <GIC_SPI 86 IRQ_TYPE_NONE>;
960 dmas = <&fdma0 4 0 1>;
961 dma-names = "tx";
962
963 status = "disabled";
964 };
965
966 sti_uni_player3: sti-uni-player@8d85000 {
967 compatible = "st,stih407-uni-player-spdif";
968 #sound-dai-cells = <0>;
969 st,syscfg = <&syscfg_core>;
970 clocks = <&clk_s_d0_flexgen CLK_SPDIFF>;
971 assigned-clocks = <&clk_s_d0_quadfs 3>, <&clk_s_d0_flexgen CLK_SPDIFF>;
972 assigned-clock-parents = <0>, <&clk_s_d0_quadfs 3>;
973 assigned-clock-rates = <50000000>;
974 reg = <0x8d85000 0x158>;
975 interrupts = <GIC_SPI 89 IRQ_TYPE_NONE>;
976 dmas = <&fdma0 7 0 1>;
977 dma-names = "tx";
978
979 status = "disabled";
980 };
981
982 sti_uni_reader0: sti-uni-reader@8d83000 {
983 compatible = "st,stih407-uni-reader-pcm_in";
984 #sound-dai-cells = <0>;
985 st,syscfg = <&syscfg_core>;
986 reg = <0x8d83000 0x158>;
987 interrupts = <GIC_SPI 87 IRQ_TYPE_NONE>;
988 dmas = <&fdma0 5 0 1>;
989 dma-names = "rx";
990
991 status = "disabled";
992 };
993
994 sti_uni_reader1: sti-uni-reader@8d84000 {
995 compatible = "st,stih407-uni-reader-hdmi";
996 #sound-dai-cells = <0>;
997 st,syscfg = <&syscfg_core>;
998 reg = <0x8d84000 0x158>;
999 interrupts = <GIC_SPI 88 IRQ_TYPE_NONE>;
1000 dmas = <&fdma0 6 0 1>;
1001 dma-names = "rx";
1002
1003 status = "disabled";
1004 };
1005 };
1006 };
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