2 * Copyright (C) 2014 STMicroelectronics Limited.
3 * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
9 #include "stih407-pinctrl.dtsi"
10 #include <dt-bindings/mfd/st-lpc.h>
11 #include <dt-bindings/reset-controller/stih407-resets.h>
21 compatible = "arm,cortex-a9";
26 compatible = "arm,cortex-a9";
31 intc: interrupt-controller@08761000 {
32 compatible = "arm,cortex-a9-gic";
33 #interrupt-cells = <3>;
35 reg = <0x08761000 0x1000>, <0x08760100 0x100>;
39 compatible = "arm,cortex-a9-scu";
40 reg = <0x08760000 0x1000>;
44 interrupt-parent = <&intc>;
45 compatible = "arm,cortex-a9-global-timer";
46 reg = <0x08760200 0x100>;
47 interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
48 clocks = <&arm_periph_clk>;
51 l2: cache-controller {
52 compatible = "arm,pl310-cache";
53 reg = <0x08762000 0x1000>;
54 arm,data-latency = <3 3 3>;
55 arm,tag-latency = <2 2 2>;
63 interrupt-parent = <&intc>;
65 compatible = "simple-bus";
67 powerdown: powerdown-controller {
68 compatible = "st,stih407-powerdown";
72 softreset: softreset-controller {
73 compatible = "st,stih407-softreset";
77 picophyreset: picophyreset-controller {
78 compatible = "st,stih407-picophyreset";
82 syscfg_sbc: sbc-syscfg@9620000 {
83 compatible = "st,stih407-sbc-syscfg", "syscon";
84 reg = <0x9620000 0x1000>;
87 syscfg_front: front-syscfg@9280000 {
88 compatible = "st,stih407-front-syscfg", "syscon";
89 reg = <0x9280000 0x1000>;
92 syscfg_rear: rear-syscfg@9290000 {
93 compatible = "st,stih407-rear-syscfg", "syscon";
94 reg = <0x9290000 0x1000>;
97 syscfg_flash: flash-syscfg@92a0000 {
98 compatible = "st,stih407-flash-syscfg", "syscon";
99 reg = <0x92a0000 0x1000>;
102 syscfg_sbc_reg: fvdp-lite-syscfg@9600000 {
103 compatible = "st,stih407-sbc-reg-syscfg", "syscon";
104 reg = <0x9600000 0x1000>;
107 syscfg_core: core-syscfg@92b0000 {
108 compatible = "st,stih407-core-syscfg", "syscon";
109 reg = <0x92b0000 0x1000>;
112 syscfg_lpm: lpm-syscfg@94b5100 {
113 compatible = "st,stih407-lpm-syscfg", "syscon";
114 reg = <0x94b5100 0x1000>;
118 compatible = "st,asc";
119 reg = <0x9830000 0x2c>;
120 interrupts = <GIC_SPI 122 IRQ_TYPE_NONE>;
121 pinctrl-names = "default";
122 pinctrl-0 = <&pinctrl_serial0>;
123 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
129 compatible = "st,asc";
130 reg = <0x9831000 0x2c>;
131 interrupts = <GIC_SPI 123 IRQ_TYPE_NONE>;
132 pinctrl-names = "default";
133 pinctrl-0 = <&pinctrl_serial1>;
134 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
140 compatible = "st,asc";
141 reg = <0x9832000 0x2c>;
142 interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>;
143 pinctrl-names = "default";
144 pinctrl-0 = <&pinctrl_serial2>;
145 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
150 /* SBC_ASC0 - UART10 */
151 sbc_serial0: serial@9530000 {
152 compatible = "st,asc";
153 reg = <0x9530000 0x2c>;
154 interrupts = <GIC_SPI 138 IRQ_TYPE_NONE>;
155 pinctrl-names = "default";
156 pinctrl-0 = <&pinctrl_sbc_serial0>;
157 clocks = <&clk_sysin>;
163 compatible = "st,asc";
164 reg = <0x9531000 0x2c>;
165 interrupts = <GIC_SPI 139 IRQ_TYPE_NONE>;
166 pinctrl-names = "default";
167 pinctrl-0 = <&pinctrl_sbc_serial1>;
168 clocks = <&clk_sysin>;
174 compatible = "st,comms-ssc4-i2c";
175 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
176 reg = <0x9840000 0x110>;
177 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
179 clock-frequency = <400000>;
180 pinctrl-names = "default";
181 pinctrl-0 = <&pinctrl_i2c0_default>;
187 compatible = "st,comms-ssc4-i2c";
188 reg = <0x9841000 0x110>;
189 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
190 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
192 clock-frequency = <400000>;
193 pinctrl-names = "default";
194 pinctrl-0 = <&pinctrl_i2c1_default>;
200 compatible = "st,comms-ssc4-i2c";
201 reg = <0x9842000 0x110>;
202 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
203 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
205 clock-frequency = <400000>;
206 pinctrl-names = "default";
207 pinctrl-0 = <&pinctrl_i2c2_default>;
213 compatible = "st,comms-ssc4-i2c";
214 reg = <0x9843000 0x110>;
215 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
216 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
218 clock-frequency = <400000>;
219 pinctrl-names = "default";
220 pinctrl-0 = <&pinctrl_i2c3_default>;
226 compatible = "st,comms-ssc4-i2c";
227 reg = <0x9844000 0x110>;
228 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
229 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
231 clock-frequency = <400000>;
232 pinctrl-names = "default";
233 pinctrl-0 = <&pinctrl_i2c4_default>;
239 compatible = "st,comms-ssc4-i2c";
240 reg = <0x9845000 0x110>;
241 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
242 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
244 clock-frequency = <400000>;
245 pinctrl-names = "default";
246 pinctrl-0 = <&pinctrl_i2c5_default>;
254 compatible = "st,comms-ssc4-i2c";
255 reg = <0x9540000 0x110>;
256 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
257 clocks = <&clk_sysin>;
259 clock-frequency = <400000>;
260 pinctrl-names = "default";
261 pinctrl-0 = <&pinctrl_i2c10_default>;
267 compatible = "st,comms-ssc4-i2c";
268 reg = <0x9541000 0x110>;
269 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
270 clocks = <&clk_sysin>;
272 clock-frequency = <400000>;
273 pinctrl-names = "default";
274 pinctrl-0 = <&pinctrl_i2c11_default>;
279 usb2_picophy0: phy1 {
280 compatible = "st,stih407-usb2-phy";
282 st,syscfg = <&syscfg_core 0x100 0xf4>;
283 resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
284 <&picophyreset STIH407_PICOPHY0_RESET>;
285 reset-names = "global", "port";
288 miphy28lp_phy: miphy28lp@9b22000 {
289 compatible = "st,miphy28lp-phy";
290 st,syscfg = <&syscfg_core>;
291 #address-cells = <1>;
295 phy_port0: port@9b22000 {
296 reg = <0x9b22000 0xff>,
299 reg-names = "sata-up",
303 st,syscfg = <0x114 0x818 0xe0 0xec>;
306 reset-names = "miphy-sw-rst";
307 resets = <&softreset STIH407_MIPHY0_SOFTRESET>;
310 phy_port1: port@9b2a000 {
311 reg = <0x9b2a000 0xff>,
314 reg-names = "sata-up",
318 st,syscfg = <0x118 0x81c 0xe4 0xf0>;
322 reset-names = "miphy-sw-rst";
323 resets = <&softreset STIH407_MIPHY1_SOFTRESET>;
326 phy_port2: port@8f95000 {
327 reg = <0x8f95000 0xff>,
332 st,syscfg = <0x11c 0x820>;
336 reset-names = "miphy-sw-rst";
337 resets = <&softreset STIH407_MIPHY2_SOFTRESET>;
342 compatible = "st,comms-ssc4-spi";
343 reg = <0x9840000 0x110>;
344 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
345 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
347 pinctrl-0 = <&pinctrl_spi0_default>;
348 pinctrl-names = "default";
349 #address-cells = <1>;
356 compatible = "st,comms-ssc4-spi";
357 reg = <0x9841000 0x110>;
358 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
359 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
366 compatible = "st,comms-ssc4-spi";
367 reg = <0x9842000 0x110>;
368 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
369 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
376 compatible = "st,comms-ssc4-spi";
377 reg = <0x9843000 0x110>;
378 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
379 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
386 compatible = "st,comms-ssc4-spi";
387 reg = <0x9844000 0x110>;
388 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
389 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
397 compatible = "st,comms-ssc4-spi";
398 reg = <0x9540000 0x110>;
399 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
400 clocks = <&clk_sysin>;
407 compatible = "st,comms-ssc4-spi";
408 reg = <0x9541000 0x110>;
409 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
410 clocks = <&clk_sysin>;
417 compatible = "st,comms-ssc4-spi";
418 reg = <0x9542000 0x110>;
419 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
420 clocks = <&clk_sysin>;
426 mmc0: sdhci@09060000 {
427 compatible = "st,sdhci-stih407", "st,sdhci";
429 reg = <0x09060000 0x7ff>, <0x9061008 0x20>;
430 reg-names = "mmc", "top-mmc-delay";
431 interrupts = <GIC_SPI 92 IRQ_TYPE_NONE>;
432 interrupt-names = "mmcirq";
433 pinctrl-names = "default";
434 pinctrl-0 = <&pinctrl_mmc0>;
436 clocks = <&clk_s_c0_flexgen CLK_MMC_0>;
441 mmc1: sdhci@09080000 {
442 compatible = "st,sdhci-stih407", "st,sdhci";
444 reg = <0x09080000 0x7ff>;
446 interrupts = <GIC_SPI 90 IRQ_TYPE_NONE>;
447 interrupt-names = "mmcirq";
448 pinctrl-names = "default";
449 pinctrl-0 = <&pinctrl_sd1>;
451 clocks = <&clk_s_c0_flexgen CLK_MMC_1>;
452 resets = <&softreset STIH407_MMC1_SOFTRESET>;
456 /* Watchdog and Real-Time Clock */
458 compatible = "st,stih407-lpc";
459 reg = <0x8787000 0x1000>;
460 interrupts = <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>;
461 clocks = <&clk_s_d3_flexgen CLK_LPC_0>;
463 st,syscfg = <&syscfg_core>;
464 st,lpc-mode = <ST_LPC_MODE_WDT>;
468 compatible = "st,stih407-lpc";
469 reg = <0x8788000 0x1000>;
470 interrupts = <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>;
471 clocks = <&clk_s_d3_flexgen CLK_LPC_1>;
472 st,lpc-mode = <ST_LPC_MODE_RTC>;