arch/arm/boot/dts/stih407.dtsi

   1 /*
   2  * Copyright (C) 2015 STMicroelectronics Limited.
   3  * Author: Gabriel Fernandez <gabriel.fernandez@linaro.org>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * publishhed by the Free Software Foundation.
   8  */
   9 #include "stih407-clock.dtsi"
  10 #include "stih407-family.dtsi"
  11 / {
  12         soc {
  13                 sti-display-subsystem {
  14                         compatible = "st,sti-display-subsystem";
  15                         #address-cells = <1>;
  16                         #size-cells = <1>;
  17
  18                         assigned-clocks = <&clk_s_d2_quadfs 0>,
  19                                           <&clk_s_d2_quadfs 1>,
  20                                           <&clk_s_c0_pll1 0>,
  21                                           <&clk_s_c0_flexgen CLK_COMPO_DVP>,
  22                                           <&clk_s_c0_flexgen CLK_MAIN_DISP>,
  23                                           <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
  24                                           <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
  25                                           <&clk_s_d2_flexgen CLK_PIX_GDP1>,
  26                                           <&clk_s_d2_flexgen CLK_PIX_GDP2>,
  27                                           <&clk_s_d2_flexgen CLK_PIX_GDP3>,
  28                                           <&clk_s_d2_flexgen CLK_PIX_GDP4>;
  29
  30                         assigned-clock-parents = <0>,
  31                                                  <0>,
  32                                                  <0>,
  33                                                  <&clk_s_c0_pll1 0>,
  34                                                  <&clk_s_c0_pll1 0>,
  35                                                  <&clk_s_d2_quadfs 0>,
  36                                                  <&clk_s_d2_quadfs 1>,
  37                                                  <&clk_s_d2_quadfs 0>,
  38                                                  <&clk_s_d2_quadfs 0>,
  39                                                  <&clk_s_d2_quadfs 0>,
  40                                                  <&clk_s_d2_quadfs 0>;
  41
  42                         assigned-clock-rates = <297000000>,
  43                                                <108000000>,
  44                                                <0>,
  45                                                <400000000>,
  46                                                <400000000>;
  47
  48                         ranges;
  49
  50                         sti-compositor@9d11000 {
  51                                 compatible = "st,stih407-compositor";
  52                                 reg = <0x9d11000 0x1000>;
  53
  54                                 clock-names = "compo_main",
  55                                               "compo_aux",
  56                                               "pix_main",
  57                                               "pix_aux",
  58                                               "pix_gdp1",
  59                                               "pix_gdp2",
  60                                               "pix_gdp3",
  61                                               "pix_gdp4",
  62                                               "main_parent",
  63                                               "aux_parent";
  64
  65                                 clocks = <&clk_s_c0_flexgen CLK_COMPO_DVP>,
  66                                          <&clk_s_c0_flexgen CLK_COMPO_DVP>,
  67                                          <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
  68                                          <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
  69                                          <&clk_s_d2_flexgen CLK_PIX_GDP1>,
  70                                          <&clk_s_d2_flexgen CLK_PIX_GDP2>,
  71                                          <&clk_s_d2_flexgen CLK_PIX_GDP3>,
  72                                          <&clk_s_d2_flexgen CLK_PIX_GDP4>,
  73                                          <&clk_s_d2_quadfs 0>,
  74                                          <&clk_s_d2_quadfs 1>;
  75
  76                                 reset-names = "compo-main", "compo-aux";
  77                                 resets = <&softreset STIH407_COMPO_SOFTRESET>,
  78                                          <&softreset STIH407_COMPO_SOFTRESET>;
  79                                 st,vtg = <&vtg_main>, <&vtg_aux>;
  80                         };
  81
  82                         sti-tvout@8d08000 {
  83                                 compatible = "st,stih407-tvout";
  84                                 reg = <0x8d08000 0x1000>;
  85                                 reg-names = "tvout-reg";
  86                                 reset-names = "tvout";
  87                                 resets = <&softreset STIH407_HDTVOUT_SOFTRESET>;
  88                                 #address-cells = <1>;
  89                                 #size-cells = <1>;
  90                                 assigned-clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
  91                                                   <&clk_s_d2_flexgen CLK_TMDS_HDMI>,
  92                                                   <&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
  93                                                   <&clk_s_d0_flexgen CLK_PCM_0>,
  94                                                   <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
  95                                                   <&clk_s_d2_flexgen CLK_HDDAC>;
  96
  97                                 assigned-clock-parents = <&clk_s_d2_quadfs 0>,
  98                                                          <&clk_tmdsout_hdmi>,
  99                                                          <&clk_s_d2_quadfs 0>,
 100                                                          <&clk_s_d0_quadfs 0>,
 101                                                          <&clk_s_d2_quadfs 0>,
 102                                                          <&clk_s_d2_quadfs 0>;
 103                         };
 104
 105                         sti_hdmi: sti-hdmi@8d04000 {
 106                                 compatible = "st,stih407-hdmi";
 107                                 reg = <0x8d04000 0x1000>;
 108                                 reg-names = "hdmi-reg";
 109                                 interrupts = <GIC_SPI 106 IRQ_TYPE_NONE>;
 110                                 interrupt-names = "irq";
 111                                 clock-names = "pix",
 112                                               "tmds",
 113                                               "phy",
 114                                               "audio",
 115                                               "main_parent",
 116                                               "aux_parent";
 117
 118                                 clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
 119                                          <&clk_s_d2_flexgen CLK_TMDS_HDMI>,
 120                                          <&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
 121                                          <&clk_s_d0_flexgen CLK_PCM_0>,
 122                                          <&clk_s_d2_quadfs 0>,
 123                                          <&clk_s_d2_quadfs 1>;
 124
 125                                 hdmi,hpd-gpio = <&pio5 3>;
 126                                 reset-names = "hdmi";
 127                                 resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>;
 128                                 ddc = <&hdmiddc>;
 129                         };
 130
 131                         sti-hda@8d02000 {
 132                                 compatible = "st,stih407-hda";
 133                                 reg = <0x8d02000 0x400>, <0x92b0120 0x4>;
 134                                 reg-names = "hda-reg", "video-dacs-ctrl";
 135                                 clock-names = "pix",
 136                                               "hddac",
 137                                               "main_parent",
 138                                               "aux_parent";
 139                                 clocks = <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
 140                                          <&clk_s_d2_flexgen CLK_HDDAC>,
 141                                          <&clk_s_d2_quadfs 0>,
 142                                          <&clk_s_d2_quadfs 1>;
 143                         };
 144                 };
 145         };
 146 };