arch/arm/boot/dts/stih407.dtsi

   1 /*
   2  * Copyright (C) 2015 STMicroelectronics Limited.
   3  * Author: Gabriel Fernandez <gabriel.fernandez@linaro.org>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * publishhed by the Free Software Foundation.
   8  */
   9 #include "stih407-clock.dtsi"
  10 #include "stih407-family.dtsi"
  11 / {
  12         soc {
  13                 /* Display */
  14                 vtg_main: sti-vtg-main@8d02800 {
  15                         compatible = "st,vtg";
  16                         reg = <0x8d02800 0x200>;
  17                         interrupts = <GIC_SPI 108 IRQ_TYPE_NONE>;
  18                 };
  19
  20                 vtg_aux: sti-vtg-aux@8d00200 {
  21                         compatible = "st,vtg";
  22                         reg = <0x8d00200 0x100>;
  23                         interrupts = <GIC_SPI 109 IRQ_TYPE_NONE>;
  24                 };
  25
  26                 sti-display-subsystem {
  27                         compatible = "st,sti-display-subsystem";
  28                         #address-cells = <1>;
  29                         #size-cells = <1>;
  30
  31                         assigned-clocks = <&clk_s_d2_quadfs 0>,
  32                                           <&clk_s_d2_quadfs 0>,
  33                                           <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
  34                                           <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
  35                                           <&clk_s_d2_flexgen CLK_PIX_GDP1>,
  36                                           <&clk_s_d2_flexgen CLK_PIX_GDP2>,
  37                                           <&clk_s_d2_flexgen CLK_PIX_GDP3>,
  38                                           <&clk_s_d2_flexgen CLK_PIX_GDP4>;
  39
  40                         assigned-clock-parents = <0>,
  41                                                  <0>,
  42                                                  <&clk_s_d2_quadfs 0>,
  43                                                  <&clk_s_d2_quadfs 0>,
  44                                                  <&clk_s_d2_quadfs 0>,
  45                                                  <&clk_s_d2_quadfs 0>,
  46                                                  <&clk_s_d2_quadfs 0>,
  47                                                  <&clk_s_d2_quadfs 0>;
  48
  49                         assigned-clock-rates = <297000000>, <297000000>;
  50
  51                         ranges;
  52
  53                         sti-compositor@9d11000 {
  54                                 compatible = "st,stih407-compositor";
  55                                 reg = <0x9d11000 0x1000>;
  56
  57                                 clock-names = "compo_main",
  58                                               "compo_aux",
  59                                               "pix_main",
  60                                               "pix_aux",
  61                                               "pix_gdp1",
  62                                               "pix_gdp2",
  63                                               "pix_gdp3",
  64                                               "pix_gdp4",
  65                                               "main_parent",
  66                                               "aux_parent";
  67
  68                                 clocks = <&clk_s_c0_flexgen CLK_COMPO_DVP>,
  69                                          <&clk_s_c0_flexgen CLK_COMPO_DVP>,
  70                                          <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
  71                                          <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
  72                                          <&clk_s_d2_flexgen CLK_PIX_GDP1>,
  73                                          <&clk_s_d2_flexgen CLK_PIX_GDP2>,
  74                                          <&clk_s_d2_flexgen CLK_PIX_GDP3>,
  75                                          <&clk_s_d2_flexgen CLK_PIX_GDP4>,
  76                                          <&clk_s_d2_quadfs 0>,
  77                                          <&clk_s_d2_quadfs 1>;
  78
  79                                 reset-names = "compo-main", "compo-aux";
  80                                 resets = <&softreset STIH407_COMPO_SOFTRESET>,
  81                                          <&softreset STIH407_COMPO_SOFTRESET>;
  82                                 st,vtg = <&vtg_main>, <&vtg_aux>;
  83                         };
  84
  85                         sti-tvout@8d08000 {
  86                                 compatible = "st,stih407-tvout";
  87                                 reg = <0x8d08000 0x1000>;
  88                                 reg-names = "tvout-reg";
  89                                 reset-names = "tvout";
  90                                 resets = <&softreset STIH407_HDTVOUT_SOFTRESET>;
  91                                 #address-cells = <1>;
  92                                 #size-cells = <1>;
  93                                 assigned-clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
  94                                                   <&clk_s_d2_flexgen CLK_TMDS_HDMI>,
  95                                                   <&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
  96                                                   <&clk_s_d0_flexgen CLK_PCM_0>,
  97                                                   <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
  98                                                   <&clk_s_d2_flexgen CLK_HDDAC>;
  99
 100                                 assigned-clock-parents = <&clk_s_d2_quadfs 0>,
 101                                                          <&clk_tmdsout_hdmi>,
 102                                                          <&clk_s_d2_quadfs 0>,
 103                                                          <&clk_s_d0_quadfs 0>,
 104                                                          <&clk_s_d2_quadfs 0>,
 105                                                          <&clk_s_d2_quadfs 0>;
 106                                 ranges;
 107
 108                                 sti-hdmi@8d04000 {
 109                                         compatible = "st,stih407-hdmi";
 110                                         reg = <0x8d04000 0x1000>;
 111                                         reg-names = "hdmi-reg";
 112                                         interrupts = <GIC_SPI 106 IRQ_TYPE_NONE>;
 113                                         interrupt-names = "irq";
 114                                         clock-names = "pix",
 115                                                       "tmds",
 116                                                       "phy",
 117                                                       "audio",
 118                                                       "main_parent",
 119                                                       "aux_parent";
 120
 121                                         clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
 122                                                  <&clk_s_d2_flexgen CLK_TMDS_HDMI>,
 123                                                  <&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
 124                                                  <&clk_s_d0_flexgen CLK_PCM_0>,
 125                                                  <&clk_s_d2_quadfs 0>,
 126                                                  <&clk_s_d2_quadfs 1>;
 127
 128                                         hdmi,hpd-gpio = <&pio5 3>;
 129                                         reset-names = "hdmi";
 130                                         resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>;
 131                                         ddc = <&hdmiddc>;
 132
 133                                 };
 134
 135                                 sti-hda@8d02000 {
 136                                         compatible = "st,stih407-hda";
 137                                         reg = <0x8d02000 0x400>, <0x92b0120 0x4>;
 138                                         reg-names = "hda-reg", "video-dacs-ctrl";
 139                                         clock-names = "pix",
 140                                                       "hddac",
 141                                                       "main_parent",
 142                                                       "aux_parent";
 143                                         clocks = <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
 144                                                  <&clk_s_d2_flexgen CLK_HDDAC>,
 145                                                  <&clk_s_d2_quadfs 0>,
 146                                                  <&clk_s_d2_quadfs 1>;
 147                                 };
 148                         };
 149                 };
 150
 151                 /* COMMS PWM Module */
 152                 pwm0: pwm@9810000 {
 153                         compatible      = "st,sti-pwm";
 154                         status          = "disabled";
 155                         #pwm-cells      = <2>;
 156                         reg             = <0x9810000 0x68>;
 157                         pinctrl-names   = "default";
 158                         pinctrl-0       = <&pinctrl_pwm0_chan0_default>;
 159                         clock-names     = "pwm";
 160                         clocks          = <&clk_sysin>;
 161                 };
 162
 163                 /* SBC PWM Module */
 164                 pwm1: pwm@9510000 {
 165                         compatible      = "st,sti-pwm";
 166                         status          = "disabled";
 167                         #pwm-cells      = <2>;
 168                         reg             = <0x9510000 0x68>;
 169                         pinctrl-names   = "default";
 170                         pinctrl-0       = <&pinctrl_pwm1_chan0_default
 171                                         &pinctrl_pwm1_chan1_default
 172                                         &pinctrl_pwm1_chan2_default
 173                                         &pinctrl_pwm1_chan3_default>;
 174                         clock-names     = "pwm";
 175                         clocks          = <&clk_sysin>;
 176                         st,pwm-num-chan = <4>;
 177                 };
 178         };
 179 };