arch/arm/boot/dts/stm32f429.dtsi

   1 /*
   2  * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  *     You should have received a copy of the GNU General Public
  20  *     License along with this file; if not, write to the Free
  21  *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  22  *     MA 02110-1301 USA
  23  *
  24  * Or, alternatively,
  25  *
  26  *  b) Permission is hereby granted, free of charge, to any person
  27  *     obtaining a copy of this software and associated documentation
  28  *     files (the "Software"), to deal in the Software without
  29  *     restriction, including without limitation the rights to use,
  30  *     copy, modify, merge, publish, distribute, sublicense, and/or
  31  *     sell copies of the Software, and to permit persons to whom the
  32  *     Software is furnished to do so, subject to the following
  33  *     conditions:
  34  *
  35  *     The above copyright notice and this permission notice shall be
  36  *     included in all copies or substantial portions of the Software.
  37  *
  38  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  39  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  40  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  41  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  42  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  43  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  44  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  45  *     OTHER DEALINGS IN THE SOFTWARE.
  46  */
  47
  48 #include "armv7-m.dtsi"
  49 #include <dt-bindings/clock/stm32fx-clock.h>
  50 #include <dt-bindings/mfd/stm32f4-rcc.h>
  51
  52 / {
  53         #address-cells = <1>;
  54         #size-cells = <1>;
  55
  56         clocks {
  57                 clk_hse: clk-hse {
  58                         #clock-cells = <0>;
  59                         compatible = "fixed-clock";
  60                         clock-frequency = <0>;
  61                 };
  62
  63                 clk_lse: clk-lse {
  64                         #clock-cells = <0>;
  65                         compatible = "fixed-clock";
  66                         clock-frequency = <32768>;
  67                 };
  68
  69                 clk_lsi: clk-lsi {
  70                         #clock-cells = <0>;
  71                         compatible = "fixed-clock";
  72                         clock-frequency = <32000>;
  73                 };
  74
  75                 clk_i2s_ckin: i2s-ckin {
  76                         #clock-cells = <0>;
  77                         compatible = "fixed-clock";
  78                         clock-frequency = <0>;
  79                 };
  80         };
  81
  82         soc {
  83                 timer2: timer@40000000 {
  84                         compatible = "st,stm32-timer";
  85                         reg = <0x40000000 0x400>;
  86                         interrupts = <28>;
  87                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
  88                         status = "disabled";
  89                 };
  90
  91                 timers2: timers@40000000 {
  92                         #address-cells = <1>;
  93                         #size-cells = <0>;
  94                         compatible = "st,stm32-timers";
  95                         reg = <0x40000000 0x400>;
  96                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
  97                         clock-names = "int";
  98                         status = "disabled";
  99
 100                         pwm {
 101                                 compatible = "st,stm32-pwm";
 102                                 status = "disabled";
 103                         };
 104
 105                         timer@1 {
 106                                 compatible = "st,stm32-timer-trigger";
 107                                 reg = <1>;
 108                                 status = "disabled";
 109                         };
 110                 };
 111
 112                 timer3: timer@40000400 {
 113                         compatible = "st,stm32-timer";
 114                         reg = <0x40000400 0x400>;
 115                         interrupts = <29>;
 116                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
 117                         status = "disabled";
 118                 };
 119
 120                 timers3: timers@40000400 {
 121                         #address-cells = <1>;
 122                         #size-cells = <0>;
 123                         compatible = "st,stm32-timers";
 124                         reg = <0x40000400 0x400>;
 125                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
 126                         clock-names = "int";
 127                         status = "disabled";
 128
 129                         pwm {
 130                                 compatible = "st,stm32-pwm";
 131                                 status = "disabled";
 132                         };
 133
 134                         timer@2 {
 135                                 compatible = "st,stm32-timer-trigger";
 136                                 reg = <2>;
 137                                 status = "disabled";
 138                         };
 139                 };
 140
 141                 timer4: timer@40000800 {
 142                         compatible = "st,stm32-timer";
 143                         reg = <0x40000800 0x400>;
 144                         interrupts = <30>;
 145                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
 146                         status = "disabled";
 147                 };
 148
 149                 timers4: timers@40000800 {
 150                         #address-cells = <1>;
 151                         #size-cells = <0>;
 152                         compatible = "st,stm32-timers";
 153                         reg = <0x40000800 0x400>;
 154                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
 155                         clock-names = "int";
 156                         status = "disabled";
 157
 158                         pwm {
 159                                 compatible = "st,stm32-pwm";
 160                                 status = "disabled";
 161                         };
 162
 163                         timer@3 {
 164                                 compatible = "st,stm32-timer-trigger";
 165                                 reg = <3>;
 166                                 status = "disabled";
 167                         };
 168                 };
 169
 170                 timer5: timer@40000c00 {
 171                         compatible = "st,stm32-timer";
 172                         reg = <0x40000c00 0x400>;
 173                         interrupts = <50>;
 174                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
 175                 };
 176
 177                 timers5: timers@40000c00 {
 178                         #address-cells = <1>;
 179                         #size-cells = <0>;
 180                         compatible = "st,stm32-timers";
 181                         reg = <0x40000C00 0x400>;
 182                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
 183                         clock-names = "int";
 184                         status = "disabled";
 185
 186                         pwm {
 187                                 compatible = "st,stm32-pwm";
 188                                 status = "disabled";
 189                         };
 190
 191                         timer@4 {
 192                                 compatible = "st,stm32-timer-trigger";
 193                                 reg = <4>;
 194                                 status = "disabled";
 195                         };
 196                 };
 197
 198                 timer6: timer@40001000 {
 199                         compatible = "st,stm32-timer";
 200                         reg = <0x40001000 0x400>;
 201                         interrupts = <54>;
 202                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
 203                         status = "disabled";
 204                 };
 205
 206                 timers6: timers@40001000 {
 207                         #address-cells = <1>;
 208                         #size-cells = <0>;
 209                         compatible = "st,stm32-timers";
 210                         reg = <0x40001000 0x400>;
 211                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
 212                         clock-names = "int";
 213                         status = "disabled";
 214
 215                         timer@5 {
 216                                 compatible = "st,stm32-timer-trigger";
 217                                 reg = <5>;
 218                                 status = "disabled";
 219                         };
 220                 };
 221
 222                 timer7: timer@40001400 {
 223                         compatible = "st,stm32-timer";
 224                         reg = <0x40001400 0x400>;
 225                         interrupts = <55>;
 226                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
 227                         status = "disabled";
 228                 };
 229
 230                 timers7: timers@40001400 {
 231                         #address-cells = <1>;
 232                         #size-cells = <0>;
 233                         compatible = "st,stm32-timers";
 234                         reg = <0x40001400 0x400>;
 235                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
 236                         clock-names = "int";
 237                         status = "disabled";
 238
 239                         timer@6 {
 240                                 compatible = "st,stm32-timer-trigger";
 241                                 reg = <6>;
 242                                 status = "disabled";
 243                         };
 244                 };
 245
 246                 timers12: timers@40001800 {
 247                         #address-cells = <1>;
 248                         #size-cells = <0>;
 249                         compatible = "st,stm32-timers";
 250                         reg = <0x40001800 0x400>;
 251                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>;
 252                         clock-names = "int";
 253                         status = "disabled";
 254
 255                         pwm {
 256                                 compatible = "st,stm32-pwm";
 257                                 status = "disabled";
 258                         };
 259
 260                         timer@11 {
 261                                 compatible = "st,stm32-timer-trigger";
 262                                 reg = <11>;
 263                                 status = "disabled";
 264                         };
 265                 };
 266
 267                 timers13: timers@40001c00 {
 268                         #address-cells = <1>;
 269                         #size-cells = <0>;
 270                         compatible = "st,stm32-timers";
 271                         reg = <0x40001C00 0x400>;
 272                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
 273                         clock-names = "int";
 274                         status = "disabled";
 275
 276                         pwm {
 277                                 compatible = "st,stm32-pwm";
 278                                 status = "disabled";
 279                         };
 280                 };
 281
 282                 timers14: timers@40002000 {
 283                         #address-cells = <1>;
 284                         #size-cells = <0>;
 285                         compatible = "st,stm32-timers";
 286                         reg = <0x40002000 0x400>;
 287                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
 288                         clock-names = "int";
 289                         status = "disabled";
 290
 291                         pwm {
 292                                 compatible = "st,stm32-pwm";
 293                                 status = "disabled";
 294                         };
 295                 };
 296
 297                 rtc: rtc@40002800 {
 298                         compatible = "st,stm32-rtc";
 299                         reg = <0x40002800 0x400>;
 300                         clocks = <&rcc 1 CLK_RTC>;
 301                         clock-names = "ck_rtc";
 302                         assigned-clocks = <&rcc 1 CLK_RTC>;
 303                         assigned-clock-parents = <&rcc 1 CLK_LSE>;
 304                         interrupt-parent = <&exti>;
 305                         interrupts = <17 1>;
 306                         interrupt-names = "alarm";
 307                         st,syscfg = <&pwrcfg 0x00 0x100>;
 308                         status = "disabled";
 309                 };
 310
 311                 iwdg: watchdog@40003000 {
 312                         compatible = "st,stm32-iwdg";
 313                         reg = <0x40003000 0x400>;
 314                         clocks = <&clk_lsi>;
 315                         clock-names = "lsi";
 316                         status = "disabled";
 317                 };
 318
 319                 usart2: serial@40004400 {
 320                         compatible = "st,stm32-uart";
 321                         reg = <0x40004400 0x400>;
 322                         interrupts = <38>;
 323                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART2)>;
 324                         status = "disabled";
 325                 };
 326
 327                 usart3: serial@40004800 {
 328                         compatible = "st,stm32-uart";
 329                         reg = <0x40004800 0x400>;
 330                         interrupts = <39>;
 331                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART3)>;
 332                         status = "disabled";
 333                         dmas = <&dma1 1 4 0x400 0x0>,
 334                                <&dma1 3 4 0x400 0x0>;
 335                         dma-names = "rx", "tx";
 336                 };
 337
 338                 usart4: serial@40004c00 {
 339                         compatible = "st,stm32-uart";
 340                         reg = <0x40004c00 0x400>;
 341                         interrupts = <52>;
 342                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART4)>;
 343                         status = "disabled";
 344                 };
 345
 346                 usart5: serial@40005000 {
 347                         compatible = "st,stm32-uart";
 348                         reg = <0x40005000 0x400>;
 349                         interrupts = <53>;
 350                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART5)>;
 351                         status = "disabled";
 352                 };
 353
 354                 i2c1: i2c@40005400 {
 355                         compatible = "st,stm32f4-i2c";
 356                         reg = <0x40005400 0x400>;
 357                         interrupts = <31>,
 358                                      <32>;
 359                         resets = <&rcc STM32F4_APB1_RESET(I2C1)>;
 360                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>;
 361                         #address-cells = <1>;
 362                         #size-cells = <0>;
 363                         status = "disabled";
 364                 };
 365
 366                 dac: dac@40007400 {
 367                         compatible = "st,stm32f4-dac-core";
 368                         reg = <0x40007400 0x400>;
 369                         resets = <&rcc STM32F4_APB1_RESET(DAC)>;
 370                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(DAC)>;
 371                         clock-names = "pclk";
 372                         #address-cells = <1>;
 373                         #size-cells = <0>;
 374                         status = "disabled";
 375
 376                         dac1: dac@1 {
 377                                 compatible = "st,stm32-dac";
 378                                 #io-channels-cells = <1>;
 379                                 reg = <1>;
 380                                 status = "disabled";
 381                         };
 382
 383                         dac2: dac@2 {
 384                                 compatible = "st,stm32-dac";
 385                                 #io-channels-cells = <1>;
 386                                 reg = <2>;
 387                                 status = "disabled";
 388                         };
 389                 };
 390
 391                 usart7: serial@40007800 {
 392                         compatible = "st,stm32-uart";
 393                         reg = <0x40007800 0x400>;
 394                         interrupts = <82>;
 395                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART7)>;
 396                         status = "disabled";
 397                 };
 398
 399                 usart8: serial@40007c00 {
 400                         compatible = "st,stm32-uart";
 401                         reg = <0x40007c00 0x400>;
 402                         interrupts = <83>;
 403                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART8)>;
 404                         status = "disabled";
 405                 };
 406
 407                 timers1: timers@40010000 {
 408                         #address-cells = <1>;
 409                         #size-cells = <0>;
 410                         compatible = "st,stm32-timers";
 411                         reg = <0x40010000 0x400>;
 412                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM1)>;
 413                         clock-names = "int";
 414                         status = "disabled";
 415
 416                         pwm {
 417                                 compatible = "st,stm32-pwm";
 418                                 status = "disabled";
 419                         };
 420
 421                         timer@0 {
 422                                 compatible = "st,stm32-timer-trigger";
 423                                 reg = <0>;
 424                                 status = "disabled";
 425                         };
 426                 };
 427
 428                 timers8: timers@40010400 {
 429                         #address-cells = <1>;
 430                         #size-cells = <0>;
 431                         compatible = "st,stm32-timers";
 432                         reg = <0x40010400 0x400>;
 433                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM8)>;
 434                         clock-names = "int";
 435                         status = "disabled";
 436
 437                         pwm {
 438                                 compatible = "st,stm32-pwm";
 439                                 status = "disabled";
 440                         };
 441
 442                         timer@7 {
 443                                 compatible = "st,stm32-timer-trigger";
 444                                 reg = <7>;
 445                                 status = "disabled";
 446                         };
 447                 };
 448
 449                 usart1: serial@40011000 {
 450                         compatible = "st,stm32-uart";
 451                         reg = <0x40011000 0x400>;
 452                         interrupts = <37>;
 453                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART1)>;
 454                         status = "disabled";
 455                         dmas = <&dma2 2 4 0x400 0x0>,
 456                                <&dma2 7 4 0x400 0x0>;
 457                         dma-names = "rx", "tx";
 458                 };
 459
 460                 usart6: serial@40011400 {
 461                         compatible = "st,stm32-uart";
 462                         reg = <0x40011400 0x400>;
 463                         interrupts = <71>;
 464                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART6)>;
 465                         status = "disabled";
 466                 };
 467
 468                 adc: adc@40012000 {
 469                         compatible = "st,stm32f4-adc-core";
 470                         reg = <0x40012000 0x400>;
 471                         interrupts = <18>;
 472                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
 473                         clock-names = "adc";
 474                         interrupt-controller;
 475                         #interrupt-cells = <1>;
 476                         #address-cells = <1>;
 477                         #size-cells = <0>;
 478                         status = "disabled";
 479
 480                         adc1: adc@0 {
 481                                 compatible = "st,stm32f4-adc";
 482                                 #io-channel-cells = <1>;
 483                                 reg = <0x0>;
 484                                 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
 485                                 interrupt-parent = <&adc>;
 486                                 interrupts = <0>;
 487                                 dmas = <&dma2 0 0 0x400 0x0>;
 488                                 dma-names = "rx";
 489                                 status = "disabled";
 490                         };
 491
 492                         adc2: adc@100 {
 493                                 compatible = "st,stm32f4-adc";
 494                                 #io-channel-cells = <1>;
 495                                 reg = <0x100>;
 496                                 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC2)>;
 497                                 interrupt-parent = <&adc>;
 498                                 interrupts = <1>;
 499                                 dmas = <&dma2 3 1 0x400 0x0>;
 500                                 dma-names = "rx";
 501                                 status = "disabled";
 502                         };
 503
 504                         adc3: adc@200 {
 505                                 compatible = "st,stm32f4-adc";
 506                                 #io-channel-cells = <1>;
 507                                 reg = <0x200>;
 508                                 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC3)>;
 509                                 interrupt-parent = <&adc>;
 510                                 interrupts = <2>;
 511                                 dmas = <&dma2 1 2 0x400 0x0>;
 512                                 dma-names = "rx";
 513                                 status = "disabled";
 514                         };
 515                 };
 516
 517                 sdio: sdio@40012c00 {
 518                         compatible = "arm,pl180", "arm,primecell";
 519                         arm,primecell-periphid = <0x00880180>;
 520                         reg = <0x40012c00 0x400>;
 521                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(SDIO)>;
 522                         clock-names = "apb_pclk";
 523                         interrupts = <49>;
 524                         max-frequency = <48000000>;
 525                         status = "disabled";
 526                 };
 527
 528                 syscfg: system-config@40013800 {
 529                         compatible = "syscon";
 530                         reg = <0x40013800 0x400>;
 531                 };
 532
 533                 exti: interrupt-controller@40013c00 {
 534                         compatible = "st,stm32-exti";
 535                         interrupt-controller;
 536                         #interrupt-cells = <2>;
 537                         reg = <0x40013C00 0x400>;
 538                         interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
 539                 };
 540
 541                 timers9: timers@40014000 {
 542                         #address-cells = <1>;
 543                         #size-cells = <0>;
 544                         compatible = "st,stm32-timers";
 545                         reg = <0x40014000 0x400>;
 546                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM9)>;
 547                         clock-names = "int";
 548                         status = "disabled";
 549
 550                         pwm {
 551                                 compatible = "st,stm32-pwm";
 552                                 status = "disabled";
 553                         };
 554
 555                         timer@8 {
 556                                 compatible = "st,stm32-timer-trigger";
 557                                 reg = <8>;
 558                                 status = "disabled";
 559                         };
 560                 };
 561
 562                 timers10: timers@40014400 {
 563                         #address-cells = <1>;
 564                         #size-cells = <0>;
 565                         compatible = "st,stm32-timers";
 566                         reg = <0x40014400 0x400>;
 567                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>;
 568                         clock-names = "int";
 569                         status = "disabled";
 570
 571                         pwm {
 572                                 compatible = "st,stm32-pwm";
 573                                 status = "disabled";
 574                         };
 575                 };
 576
 577                 timers11: timers@40014800 {
 578                         #address-cells = <1>;
 579                         #size-cells = <0>;
 580                         compatible = "st,stm32-timers";
 581                         reg = <0x40014800 0x400>;
 582                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>;
 583                         clock-names = "int";
 584                         status = "disabled";
 585
 586                         pwm {
 587                                 compatible = "st,stm32-pwm";
 588                                 status = "disabled";
 589                         };
 590                 };
 591
 592                 pwrcfg: power-config@40007000 {
 593                         compatible = "syscon";
 594                         reg = <0x40007000 0x400>;
 595                 };
 596
 597                 ltdc: display-controller@40016800 {
 598                         compatible = "st,stm32-ltdc";
 599                         reg = <0x40016800 0x200>;
 600                         interrupts = <88>, <89>;
 601                         resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
 602                         clocks = <&rcc 1 CLK_LCD>;
 603                         clock-names = "lcd";
 604                         status = "disabled";
 605                 };
 606
 607                 crc: crc@40023000 {
 608                         compatible = "st,stm32f4-crc";
 609                         reg = <0x40023000 0x400>;
 610                         clocks = <&rcc 0 STM32F4_AHB1_CLOCK(CRC)>;
 611                         status = "disabled";
 612                 };
 613
 614                 rcc: rcc@40023810 {
 615                         #reset-cells = <1>;
 616                         #clock-cells = <2>;
 617                         compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
 618                         reg = <0x40023800 0x400>;
 619                         clocks = <&clk_hse>, <&clk_i2s_ckin>;
 620                         st,syscfg = <&pwrcfg>;
 621                         assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
 622                         assigned-clock-rates = <1000000>;
 623                 };
 624
 625                 dma1: dma-controller@40026000 {
 626                         compatible = "st,stm32-dma";
 627                         reg = <0x40026000 0x400>;
 628                         interrupts = <11>,
 629                                      <12>,
 630                                      <13>,
 631                                      <14>,
 632                                      <15>,
 633                                      <16>,
 634                                      <17>,
 635                                      <47>;
 636                         clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA1)>;
 637                         #dma-cells = <4>;
 638                 };
 639
 640                 dma2: dma-controller@40026400 {
 641                         compatible = "st,stm32-dma";
 642                         reg = <0x40026400 0x400>;
 643                         interrupts = <56>,
 644                                      <57>,
 645                                      <58>,
 646                                      <59>,
 647                                      <60>,
 648                                      <68>,
 649                                      <69>,
 650                                      <70>;
 651                         clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2)>;
 652                         #dma-cells = <4>;
 653                         st,mem2mem;
 654                 };
 655
 656                 mac: ethernet@40028000 {
 657                         compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
 658                         reg = <0x40028000 0x8000>;
 659                         reg-names = "stmmaceth";
 660                         interrupts = <61>;
 661                         interrupt-names = "macirq";
 662                         clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
 663                         clocks = <&rcc 0 STM32F4_AHB1_CLOCK(ETHMAC)>,
 664                                         <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACTX)>,
 665                                         <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACRX)>;
 666                         st,syscon = <&syscfg 0x4>;
 667                         snps,pbl = <8>;
 668                         snps,mixed-burst;
 669                         status = "disabled";
 670                 };
 671
 672                 usbotg_hs: usb@40040000 {
 673                         compatible = "snps,dwc2";
 674                         reg = <0x40040000 0x40000>;
 675                         interrupts = <77>;
 676                         clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHS)>;
 677                         clock-names = "otg";
 678                         status = "disabled";
 679                 };
 680
 681                 usbotg_fs: usb@50000000 {
 682                         compatible = "st,stm32f4x9-fsotg";
 683                         reg = <0x50000000 0x40000>;
 684                         interrupts = <67>;
 685                         clocks = <&rcc 0 39>;
 686                         clock-names = "otg";
 687                         status = "disabled";
 688                 };
 689
 690                 dcmi: dcmi@50050000 {
 691                         compatible = "st,stm32-dcmi";
 692                         reg = <0x50050000 0x400>;
 693                         interrupts = <78>;
 694                         resets = <&rcc STM32F4_AHB2_RESET(DCMI)>;
 695                         clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>;
 696                         clock-names = "mclk";
 697                         pinctrl-names = "default";
 698                         pinctrl-0 = <&dcmi_pins>;
 699                         dmas = <&dma2 1 1 0x414 0x3>;
 700                         dma-names = "tx";
 701                         status = "disabled";
 702                 };
 703
 704                 rng: rng@50060800 {
 705                         compatible = "st,stm32-rng";
 706                         reg = <0x50060800 0x400>;
 707                         interrupts = <80>;
 708                         clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>;
 709
 710                 };
 711         };
 712 };
 713
 714 &systick {
 715         clocks = <&rcc 1 SYSTICK>;
 716         status = "okay";
 717 };