2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public
20 * License along with this file; if not, write to the Free
21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
48 #include "skeleton.dtsi"
49 #include "armv7-m.dtsi"
50 #include <dt-bindings/pinctrl/stm32f429-pinfunc.h>
51 #include <dt-bindings/clock/stm32fx-clock.h>
52 #include <dt-bindings/mfd/stm32f4-rcc.h>
58 compatible = "fixed-clock";
59 clock-frequency = <0>;
64 compatible = "fixed-clock";
65 clock-frequency = <32768>;
70 compatible = "fixed-clock";
71 clock-frequency = <32000>;
74 clk_i2s_ckin: i2s-ckin {
76 compatible = "fixed-clock";
77 clock-frequency = <0>;
82 timer2: timer@40000000 {
83 compatible = "st,stm32-timer";
84 reg = <0x40000000 0x400>;
86 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
90 timers2: timers@40000000 {
93 compatible = "st,stm32-timers";
94 reg = <0x40000000 0x400>;
95 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
100 compatible = "st,stm32-pwm";
105 compatible = "st,stm32-timer-trigger";
111 timer3: timer@40000400 {
112 compatible = "st,stm32-timer";
113 reg = <0x40000400 0x400>;
115 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
119 timers3: timers@40000400 {
120 #address-cells = <1>;
122 compatible = "st,stm32-timers";
123 reg = <0x40000400 0x400>;
124 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
129 compatible = "st,stm32-pwm";
134 compatible = "st,stm32-timer-trigger";
140 timer4: timer@40000800 {
141 compatible = "st,stm32-timer";
142 reg = <0x40000800 0x400>;
144 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
148 timers4: timers@40000800 {
149 #address-cells = <1>;
151 compatible = "st,stm32-timers";
152 reg = <0x40000800 0x400>;
153 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
158 compatible = "st,stm32-pwm";
163 compatible = "st,stm32-timer-trigger";
169 timer5: timer@40000c00 {
170 compatible = "st,stm32-timer";
171 reg = <0x40000c00 0x400>;
173 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
176 timers5: timers@40000c00 {
177 #address-cells = <1>;
179 compatible = "st,stm32-timers";
180 reg = <0x40000C00 0x400>;
181 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
186 compatible = "st,stm32-pwm";
191 compatible = "st,stm32-timer-trigger";
197 timer6: timer@40001000 {
198 compatible = "st,stm32-timer";
199 reg = <0x40001000 0x400>;
201 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
205 timers6: timers@40001000 {
206 #address-cells = <1>;
208 compatible = "st,stm32-timers";
209 reg = <0x40001000 0x400>;
210 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
215 compatible = "st,stm32-timer-trigger";
221 timer7: timer@40001400 {
222 compatible = "st,stm32-timer";
223 reg = <0x40001400 0x400>;
225 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
229 timers7: timers@40001400 {
230 #address-cells = <1>;
232 compatible = "st,stm32-timers";
233 reg = <0x40001400 0x400>;
234 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
239 compatible = "st,stm32-timer-trigger";
245 timers12: timers@40001800 {
246 #address-cells = <1>;
248 compatible = "st,stm32-timers";
249 reg = <0x40001800 0x400>;
250 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>;
255 compatible = "st,stm32-pwm";
260 compatible = "st,stm32-timer-trigger";
266 timers13: timers@40001c00 {
267 #address-cells = <1>;
269 compatible = "st,stm32-timers";
270 reg = <0x40001C00 0x400>;
271 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
276 compatible = "st,stm32-pwm";
281 timers14: timers@40002000 {
282 #address-cells = <1>;
284 compatible = "st,stm32-timers";
285 reg = <0x40002000 0x400>;
286 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
291 compatible = "st,stm32-pwm";
297 compatible = "st,stm32-rtc";
298 reg = <0x40002800 0x400>;
299 clocks = <&rcc 1 CLK_RTC>;
300 clock-names = "ck_rtc";
301 assigned-clocks = <&rcc 1 CLK_RTC>;
302 assigned-clock-parents = <&rcc 1 CLK_LSE>;
303 interrupt-parent = <&exti>;
305 interrupt-names = "alarm";
306 st,syscfg = <&pwrcfg>;
310 iwdg: watchdog@40003000 {
311 compatible = "st,stm32-iwdg";
312 reg = <0x40003000 0x400>;
317 usart2: serial@40004400 {
318 compatible = "st,stm32-usart", "st,stm32-uart";
319 reg = <0x40004400 0x400>;
321 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART2)>;
325 usart3: serial@40004800 {
326 compatible = "st,stm32-usart", "st,stm32-uart";
327 reg = <0x40004800 0x400>;
329 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART3)>;
331 dmas = <&dma1 1 4 0x400 0x0>,
332 <&dma1 3 4 0x400 0x0>;
333 dma-names = "rx", "tx";
336 usart4: serial@40004c00 {
337 compatible = "st,stm32-uart";
338 reg = <0x40004c00 0x400>;
340 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART4)>;
344 usart5: serial@40005000 {
345 compatible = "st,stm32-uart";
346 reg = <0x40005000 0x400>;
348 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART5)>;
353 compatible = "st,stm32f4-i2c";
354 reg = <0x40005400 0x400>;
357 resets = <&rcc STM32F4_APB1_RESET(I2C1)>;
358 clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>;
359 #address-cells = <1>;
364 usart7: serial@40007800 {
365 compatible = "st,stm32-usart", "st,stm32-uart";
366 reg = <0x40007800 0x400>;
368 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART7)>;
372 usart8: serial@40007c00 {
373 compatible = "st,stm32-usart", "st,stm32-uart";
374 reg = <0x40007c00 0x400>;
376 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART8)>;
380 timers1: timers@40010000 {
381 #address-cells = <1>;
383 compatible = "st,stm32-timers";
384 reg = <0x40010000 0x400>;
385 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM1)>;
390 compatible = "st,stm32-pwm";
395 compatible = "st,stm32-timer-trigger";
401 timers8: timers@40010400 {
402 #address-cells = <1>;
404 compatible = "st,stm32-timers";
405 reg = <0x40010400 0x400>;
406 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM8)>;
411 compatible = "st,stm32-pwm";
416 compatible = "st,stm32-timer-trigger";
422 usart1: serial@40011000 {
423 compatible = "st,stm32-usart", "st,stm32-uart";
424 reg = <0x40011000 0x400>;
426 clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART1)>;
428 dmas = <&dma2 2 4 0x400 0x0>,
429 <&dma2 7 4 0x400 0x0>;
430 dma-names = "rx", "tx";
433 usart6: serial@40011400 {
434 compatible = "st,stm32-usart", "st,stm32-uart";
435 reg = <0x40011400 0x400>;
437 clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART6)>;
442 compatible = "st,stm32f4-adc-core";
443 reg = <0x40012000 0x400>;
445 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
447 interrupt-controller;
448 #interrupt-cells = <1>;
449 #address-cells = <1>;
454 compatible = "st,stm32f4-adc";
455 #io-channel-cells = <1>;
457 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
458 interrupt-parent = <&adc>;
460 dmas = <&dma2 0 0 0x400 0x0>;
466 compatible = "st,stm32f4-adc";
467 #io-channel-cells = <1>;
469 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC2)>;
470 interrupt-parent = <&adc>;
472 dmas = <&dma2 3 1 0x400 0x0>;
478 compatible = "st,stm32f4-adc";
479 #io-channel-cells = <1>;
481 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC3)>;
482 interrupt-parent = <&adc>;
484 dmas = <&dma2 1 2 0x400 0x0>;
490 syscfg: system-config@40013800 {
491 compatible = "syscon";
492 reg = <0x40013800 0x400>;
495 exti: interrupt-controller@40013c00 {
496 compatible = "st,stm32-exti";
497 interrupt-controller;
498 #interrupt-cells = <2>;
499 reg = <0x40013C00 0x400>;
500 interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
503 timers9: timers@40014000 {
504 #address-cells = <1>;
506 compatible = "st,stm32-timers";
507 reg = <0x40014000 0x400>;
508 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM9)>;
513 compatible = "st,stm32-pwm";
518 compatible = "st,stm32-timer-trigger";
524 timers10: timers@40014400 {
525 #address-cells = <1>;
527 compatible = "st,stm32-timers";
528 reg = <0x40014400 0x400>;
529 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>;
534 compatible = "st,stm32-pwm";
539 timers11: timers@40014800 {
540 #address-cells = <1>;
542 compatible = "st,stm32-timers";
543 reg = <0x40014800 0x400>;
544 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>;
549 compatible = "st,stm32-pwm";
554 pwrcfg: power-config@40007000 {
555 compatible = "syscon";
556 reg = <0x40007000 0x400>;
559 ltdc: display-controller@40016800 {
560 compatible = "st,stm32-ltdc";
561 reg = <0x40016800 0x200>;
562 interrupts = <88>, <89>;
563 resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
564 clocks = <&rcc 1 CLK_LCD>;
569 pinctrl: pin-controller {
570 #address-cells = <1>;
572 compatible = "st,stm32f429-pinctrl";
573 ranges = <0 0x40020000 0x3000>;
574 interrupt-parent = <&exti>;
575 st,syscfg = <&syscfg 0x8>;
578 gpioa: gpio@40020000 {
581 interrupt-controller;
582 #interrupt-cells = <2>;
584 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>;
585 st,bank-name = "GPIOA";
588 gpiob: gpio@40020400 {
591 interrupt-controller;
592 #interrupt-cells = <2>;
594 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>;
595 st,bank-name = "GPIOB";
598 gpioc: gpio@40020800 {
601 interrupt-controller;
602 #interrupt-cells = <2>;
604 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>;
605 st,bank-name = "GPIOC";
608 gpiod: gpio@40020c00 {
611 interrupt-controller;
612 #interrupt-cells = <2>;
614 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOD)>;
615 st,bank-name = "GPIOD";
618 gpioe: gpio@40021000 {
621 interrupt-controller;
622 #interrupt-cells = <2>;
623 reg = <0x1000 0x400>;
624 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOE)>;
625 st,bank-name = "GPIOE";
628 gpiof: gpio@40021400 {
631 interrupt-controller;
632 #interrupt-cells = <2>;
633 reg = <0x1400 0x400>;
634 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOF)>;
635 st,bank-name = "GPIOF";
638 gpiog: gpio@40021800 {
641 interrupt-controller;
642 #interrupt-cells = <2>;
643 reg = <0x1800 0x400>;
644 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOG)>;
645 st,bank-name = "GPIOG";
648 gpioh: gpio@40021c00 {
651 interrupt-controller;
652 #interrupt-cells = <2>;
653 reg = <0x1c00 0x400>;
654 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOH)>;
655 st,bank-name = "GPIOH";
658 gpioi: gpio@40022000 {
661 interrupt-controller;
662 #interrupt-cells = <2>;
663 reg = <0x2000 0x400>;
664 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOI)>;
665 st,bank-name = "GPIOI";
668 gpioj: gpio@40022400 {
671 interrupt-controller;
672 #interrupt-cells = <2>;
673 reg = <0x2400 0x400>;
674 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOJ)>;
675 st,bank-name = "GPIOJ";
678 gpiok: gpio@40022800 {
681 interrupt-controller;
682 #interrupt-cells = <2>;
683 reg = <0x2800 0x400>;
684 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOK)>;
685 st,bank-name = "GPIOK";
688 usart1_pins_a: usart1@0 {
690 pinmux = <STM32F429_PA9_FUNC_USART1_TX>;
696 pinmux = <STM32F429_PA10_FUNC_USART1_RX>;
701 usart3_pins_a: usart3@0 {
703 pinmux = <STM32F429_PB10_FUNC_USART3_TX>;
709 pinmux = <STM32F429_PB11_FUNC_USART3_RX>;
714 usbotg_fs_pins_a: usbotg_fs@0 {
716 pinmux = <STM32F429_PA10_FUNC_OTG_FS_ID>,
717 <STM32F429_PA11_FUNC_OTG_FS_DM>,
718 <STM32F429_PA12_FUNC_OTG_FS_DP>;
725 usbotg_fs_pins_b: usbotg_fs@1 {
727 pinmux = <STM32F429_PB12_FUNC_OTG_HS_ID>,
728 <STM32F429_PB14_FUNC_OTG_HS_DM>,
729 <STM32F429_PB15_FUNC_OTG_HS_DP>;
736 usbotg_hs_pins_a: usbotg_hs@0 {
738 pinmux = <STM32F429_PH4_FUNC_OTG_HS_ULPI_NXT>,
739 <STM32F429_PI11_FUNC_OTG_HS_ULPI_DIR>,
740 <STM32F429_PC0_FUNC_OTG_HS_ULPI_STP>,
741 <STM32F429_PA5_FUNC_OTG_HS_ULPI_CK>,
742 <STM32F429_PA3_FUNC_OTG_HS_ULPI_D0>,
743 <STM32F429_PB0_FUNC_OTG_HS_ULPI_D1>,
744 <STM32F429_PB1_FUNC_OTG_HS_ULPI_D2>,
745 <STM32F429_PB10_FUNC_OTG_HS_ULPI_D3>,
746 <STM32F429_PB11_FUNC_OTG_HS_ULPI_D4>,
747 <STM32F429_PB12_FUNC_OTG_HS_ULPI_D5>,
748 <STM32F429_PB13_FUNC_OTG_HS_ULPI_D6>,
749 <STM32F429_PB5_FUNC_OTG_HS_ULPI_D7>;
756 ethernet_mii: mii@0 {
758 pinmux = <STM32F429_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>,
759 <STM32F429_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>,
760 <STM32F429_PC2_FUNC_ETH_MII_TXD2>,
761 <STM32F429_PB8_FUNC_ETH_MII_TXD3>,
762 <STM32F429_PC3_FUNC_ETH_MII_TX_CLK>,
763 <STM32F429_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>,
764 <STM32F429_PA2_FUNC_ETH_MDIO>,
765 <STM32F429_PC1_FUNC_ETH_MDC>,
766 <STM32F429_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>,
767 <STM32F429_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>,
768 <STM32F429_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>,
769 <STM32F429_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>,
770 <STM32F429_PH6_FUNC_ETH_MII_RXD2>,
771 <STM32F429_PH7_FUNC_ETH_MII_RXD3>;
776 adc3_in8_pin: adc@200 {
778 pinmux = <STM32F429_PF10_FUNC_ANALOG>;
784 pinmux = <STM32F429_PA8_FUNC_TIM1_CH1>,
785 <STM32F429_PB13_FUNC_TIM1_CH1N>,
786 <STM32F429_PB12_FUNC_TIM1_BKIN>;
792 pinmux = <STM32F429_PB4_FUNC_TIM3_CH1>,
793 <STM32F429_PB5_FUNC_TIM3_CH2>;
799 pinmux = <STM32F429_PB9_FUNC_I2C1_SDA>,
800 <STM32F429_PB6_FUNC_I2C1_SCL>;
809 pinmux = <STM32F429_PI12_FUNC_LCD_HSYNC>,
810 <STM32F429_PI13_FUNC_LCD_VSYNC>,
811 <STM32F429_PI14_FUNC_LCD_CLK>,
812 <STM32F429_PI15_FUNC_LCD_R0>,
813 <STM32F429_PJ0_FUNC_LCD_R1>,
814 <STM32F429_PJ1_FUNC_LCD_R2>,
815 <STM32F429_PJ2_FUNC_LCD_R3>,
816 <STM32F429_PJ3_FUNC_LCD_R4>,
817 <STM32F429_PJ4_FUNC_LCD_R5>,
818 <STM32F429_PJ5_FUNC_LCD_R6>,
819 <STM32F429_PJ6_FUNC_LCD_R7>,
820 <STM32F429_PJ7_FUNC_LCD_G0>,
821 <STM32F429_PJ8_FUNC_LCD_G1>,
822 <STM32F429_PJ9_FUNC_LCD_G2>,
823 <STM32F429_PJ10_FUNC_LCD_G3>,
824 <STM32F429_PJ11_FUNC_LCD_G4>,
825 <STM32F429_PJ12_FUNC_LCD_B0>,
826 <STM32F429_PJ13_FUNC_LCD_B1>,
827 <STM32F429_PJ14_FUNC_LCD_B2>,
828 <STM32F429_PJ15_FUNC_LCD_B3>,
829 <STM32F429_PK0_FUNC_LCD_G5>,
830 <STM32F429_PK1_FUNC_LCD_G6>,
831 <STM32F429_PK2_FUNC_LCD_G7>,
832 <STM32F429_PK3_FUNC_LCD_B4>,
833 <STM32F429_PK4_FUNC_LCD_B5>,
834 <STM32F429_PK5_FUNC_LCD_B6>,
835 <STM32F429_PK6_FUNC_LCD_B7>,
836 <STM32F429_PK7_FUNC_LCD_DE>;
843 pinmux = <STM32F429_PA4_FUNC_DCMI_HSYNC>,
844 <STM32F429_PB7_FUNC_DCMI_VSYNC>,
845 <STM32F429_PA6_FUNC_DCMI_PIXCLK>,
846 <STM32F429_PC6_FUNC_DCMI_D0>,
847 <STM32F429_PC7_FUNC_DCMI_D1>,
848 <STM32F429_PC8_FUNC_DCMI_D2>,
849 <STM32F429_PC9_FUNC_DCMI_D3>,
850 <STM32F429_PC11_FUNC_DCMI_D4>,
851 <STM32F429_PD3_FUNC_DCMI_D5>,
852 <STM32F429_PB8_FUNC_DCMI_D6>,
853 <STM32F429_PE6_FUNC_DCMI_D7>,
854 <STM32F429_PC10_FUNC_DCMI_D8>,
855 <STM32F429_PC12_FUNC_DCMI_D9>,
856 <STM32F429_PD6_FUNC_DCMI_D10>,
857 <STM32F429_PD2_FUNC_DCMI_D11>;
866 compatible = "st,stm32f4-crc";
867 reg = <0x40023000 0x400>;
868 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(CRC)>;
875 compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
876 reg = <0x40023800 0x400>;
877 clocks = <&clk_hse>, <&clk_i2s_ckin>;
878 st,syscfg = <&pwrcfg>;
879 assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
880 assigned-clock-rates = <1000000>;
883 dma1: dma-controller@40026000 {
884 compatible = "st,stm32-dma";
885 reg = <0x40026000 0x400>;
894 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA1)>;
898 dma2: dma-controller@40026400 {
899 compatible = "st,stm32-dma";
900 reg = <0x40026400 0x400>;
909 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2)>;
914 mac: ethernet@40028000 {
915 compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
916 reg = <0x40028000 0x8000>;
917 reg-names = "stmmaceth";
919 interrupt-names = "macirq";
920 clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
921 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(ETHMAC)>,
922 <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACTX)>,
923 <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACRX)>;
924 st,syscon = <&syscfg 0x4>;
930 usbotg_hs: usb@40040000 {
931 compatible = "snps,dwc2";
932 reg = <0x40040000 0x40000>;
934 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHS)>;
939 usbotg_fs: usb@50000000 {
940 compatible = "st,stm32f4x9-fsotg";
941 reg = <0x50000000 0x40000>;
943 clocks = <&rcc 0 39>;
948 dcmi: dcmi@50050000 {
949 compatible = "st,stm32-dcmi";
950 reg = <0x50050000 0x400>;
952 resets = <&rcc STM32F4_AHB2_RESET(DCMI)>;
953 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>;
954 clock-names = "mclk";
955 pinctrl-names = "default";
956 pinctrl-0 = <&dcmi_pins>;
957 dmas = <&dma2 1 1 0x414 0x3>;
963 compatible = "st,stm32-rng";
964 reg = <0x50060800 0x400>;
966 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>;
973 clocks = <&rcc 1 SYSTICK>;