2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public
20 * License along with this file; if not, write to the Free
21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
48 #include "armv7-m.dtsi"
49 #include <dt-bindings/clock/stm32fx-clock.h>
50 #include <dt-bindings/mfd/stm32f4-rcc.h>
59 compatible = "fixed-clock";
60 clock-frequency = <0>;
65 compatible = "fixed-clock";
66 clock-frequency = <32768>;
71 compatible = "fixed-clock";
72 clock-frequency = <32000>;
75 clk_i2s_ckin: i2s-ckin {
77 compatible = "fixed-clock";
78 clock-frequency = <0>;
83 timer2: timer@40000000 {
84 compatible = "st,stm32-timer";
85 reg = <0x40000000 0x400>;
87 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
91 timers2: timers@40000000 {
94 compatible = "st,stm32-timers";
95 reg = <0x40000000 0x400>;
96 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
101 compatible = "st,stm32-pwm";
106 compatible = "st,stm32-timer-trigger";
112 timer3: timer@40000400 {
113 compatible = "st,stm32-timer";
114 reg = <0x40000400 0x400>;
116 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
120 timers3: timers@40000400 {
121 #address-cells = <1>;
123 compatible = "st,stm32-timers";
124 reg = <0x40000400 0x400>;
125 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
130 compatible = "st,stm32-pwm";
135 compatible = "st,stm32-timer-trigger";
141 timer4: timer@40000800 {
142 compatible = "st,stm32-timer";
143 reg = <0x40000800 0x400>;
145 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
149 timers4: timers@40000800 {
150 #address-cells = <1>;
152 compatible = "st,stm32-timers";
153 reg = <0x40000800 0x400>;
154 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
159 compatible = "st,stm32-pwm";
164 compatible = "st,stm32-timer-trigger";
170 timer5: timer@40000c00 {
171 compatible = "st,stm32-timer";
172 reg = <0x40000c00 0x400>;
174 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
177 timers5: timers@40000c00 {
178 #address-cells = <1>;
180 compatible = "st,stm32-timers";
181 reg = <0x40000C00 0x400>;
182 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
187 compatible = "st,stm32-pwm";
192 compatible = "st,stm32-timer-trigger";
198 timer6: timer@40001000 {
199 compatible = "st,stm32-timer";
200 reg = <0x40001000 0x400>;
202 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
206 timers6: timers@40001000 {
207 #address-cells = <1>;
209 compatible = "st,stm32-timers";
210 reg = <0x40001000 0x400>;
211 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
216 compatible = "st,stm32-timer-trigger";
222 timer7: timer@40001400 {
223 compatible = "st,stm32-timer";
224 reg = <0x40001400 0x400>;
226 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
230 timers7: timers@40001400 {
231 #address-cells = <1>;
233 compatible = "st,stm32-timers";
234 reg = <0x40001400 0x400>;
235 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
240 compatible = "st,stm32-timer-trigger";
246 timers12: timers@40001800 {
247 #address-cells = <1>;
249 compatible = "st,stm32-timers";
250 reg = <0x40001800 0x400>;
251 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>;
256 compatible = "st,stm32-pwm";
261 compatible = "st,stm32-timer-trigger";
267 timers13: timers@40001c00 {
268 #address-cells = <1>;
270 compatible = "st,stm32-timers";
271 reg = <0x40001C00 0x400>;
272 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
277 compatible = "st,stm32-pwm";
282 timers14: timers@40002000 {
283 #address-cells = <1>;
285 compatible = "st,stm32-timers";
286 reg = <0x40002000 0x400>;
287 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
292 compatible = "st,stm32-pwm";
298 compatible = "st,stm32-rtc";
299 reg = <0x40002800 0x400>;
300 clocks = <&rcc 1 CLK_RTC>;
301 clock-names = "ck_rtc";
302 assigned-clocks = <&rcc 1 CLK_RTC>;
303 assigned-clock-parents = <&rcc 1 CLK_LSE>;
304 interrupt-parent = <&exti>;
306 interrupt-names = "alarm";
307 st,syscfg = <&pwrcfg 0x00 0x100>;
311 iwdg: watchdog@40003000 {
312 compatible = "st,stm32-iwdg";
313 reg = <0x40003000 0x400>;
320 #address-cells = <1>;
322 compatible = "st,stm32f4-spi";
323 reg = <0x40003800 0x400>;
325 clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI2)>;
330 #address-cells = <1>;
332 compatible = "st,stm32f4-spi";
333 reg = <0x40003c00 0x400>;
335 clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI3)>;
339 usart2: serial@40004400 {
340 compatible = "st,stm32-uart";
341 reg = <0x40004400 0x400>;
343 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART2)>;
347 usart3: serial@40004800 {
348 compatible = "st,stm32-uart";
349 reg = <0x40004800 0x400>;
351 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART3)>;
353 dmas = <&dma1 1 4 0x400 0x0>,
354 <&dma1 3 4 0x400 0x0>;
355 dma-names = "rx", "tx";
358 usart4: serial@40004c00 {
359 compatible = "st,stm32-uart";
360 reg = <0x40004c00 0x400>;
362 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART4)>;
366 usart5: serial@40005000 {
367 compatible = "st,stm32-uart";
368 reg = <0x40005000 0x400>;
370 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART5)>;
375 compatible = "st,stm32f4-i2c";
376 reg = <0x40005400 0x400>;
379 resets = <&rcc STM32F4_APB1_RESET(I2C1)>;
380 clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>;
381 #address-cells = <1>;
387 compatible = "st,stm32f4-dac-core";
388 reg = <0x40007400 0x400>;
389 resets = <&rcc STM32F4_APB1_RESET(DAC)>;
390 clocks = <&rcc 0 STM32F4_APB1_CLOCK(DAC)>;
391 clock-names = "pclk";
392 #address-cells = <1>;
397 compatible = "st,stm32-dac";
398 #io-channels-cells = <1>;
404 compatible = "st,stm32-dac";
405 #io-channels-cells = <1>;
411 usart7: serial@40007800 {
412 compatible = "st,stm32-uart";
413 reg = <0x40007800 0x400>;
415 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART7)>;
419 usart8: serial@40007c00 {
420 compatible = "st,stm32-uart";
421 reg = <0x40007c00 0x400>;
423 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART8)>;
427 timers1: timers@40010000 {
428 #address-cells = <1>;
430 compatible = "st,stm32-timers";
431 reg = <0x40010000 0x400>;
432 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM1)>;
437 compatible = "st,stm32-pwm";
442 compatible = "st,stm32-timer-trigger";
448 timers8: timers@40010400 {
449 #address-cells = <1>;
451 compatible = "st,stm32-timers";
452 reg = <0x40010400 0x400>;
453 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM8)>;
458 compatible = "st,stm32-pwm";
463 compatible = "st,stm32-timer-trigger";
469 usart1: serial@40011000 {
470 compatible = "st,stm32-uart";
471 reg = <0x40011000 0x400>;
473 clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART1)>;
475 dmas = <&dma2 2 4 0x400 0x0>,
476 <&dma2 7 4 0x400 0x0>;
477 dma-names = "rx", "tx";
480 usart6: serial@40011400 {
481 compatible = "st,stm32-uart";
482 reg = <0x40011400 0x400>;
484 clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART6)>;
489 compatible = "st,stm32f4-adc-core";
490 reg = <0x40012000 0x400>;
492 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
494 interrupt-controller;
495 #interrupt-cells = <1>;
496 #address-cells = <1>;
501 compatible = "st,stm32f4-adc";
502 #io-channel-cells = <1>;
504 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
505 interrupt-parent = <&adc>;
507 dmas = <&dma2 0 0 0x400 0x0>;
513 compatible = "st,stm32f4-adc";
514 #io-channel-cells = <1>;
516 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC2)>;
517 interrupt-parent = <&adc>;
519 dmas = <&dma2 3 1 0x400 0x0>;
525 compatible = "st,stm32f4-adc";
526 #io-channel-cells = <1>;
528 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC3)>;
529 interrupt-parent = <&adc>;
531 dmas = <&dma2 1 2 0x400 0x0>;
537 sdio: sdio@40012c00 {
538 compatible = "arm,pl180", "arm,primecell";
539 arm,primecell-periphid = <0x00880180>;
540 reg = <0x40012c00 0x400>;
541 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SDIO)>;
542 clock-names = "apb_pclk";
544 max-frequency = <48000000>;
549 #address-cells = <1>;
551 compatible = "st,stm32f4-spi";
552 reg = <0x40013000 0x400>;
554 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI1)>;
559 #address-cells = <1>;
561 compatible = "st,stm32f4-spi";
562 reg = <0x40013400 0x400>;
564 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI4)>;
568 syscfg: system-config@40013800 {
569 compatible = "syscon";
570 reg = <0x40013800 0x400>;
573 exti: interrupt-controller@40013c00 {
574 compatible = "st,stm32-exti";
575 interrupt-controller;
576 #interrupt-cells = <2>;
577 reg = <0x40013C00 0x400>;
578 interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
581 timers9: timers@40014000 {
582 #address-cells = <1>;
584 compatible = "st,stm32-timers";
585 reg = <0x40014000 0x400>;
586 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM9)>;
591 compatible = "st,stm32-pwm";
596 compatible = "st,stm32-timer-trigger";
602 timers10: timers@40014400 {
603 #address-cells = <1>;
605 compatible = "st,stm32-timers";
606 reg = <0x40014400 0x400>;
607 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>;
612 compatible = "st,stm32-pwm";
617 timers11: timers@40014800 {
618 #address-cells = <1>;
620 compatible = "st,stm32-timers";
621 reg = <0x40014800 0x400>;
622 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>;
627 compatible = "st,stm32-pwm";
633 #address-cells = <1>;
635 compatible = "st,stm32f4-spi";
636 reg = <0x40015000 0x400>;
638 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI5)>;
643 #address-cells = <1>;
645 compatible = "st,stm32f4-spi";
646 reg = <0x40015400 0x400>;
648 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI6)>;
652 pwrcfg: power-config@40007000 {
653 compatible = "syscon";
654 reg = <0x40007000 0x400>;
657 ltdc: display-controller@40016800 {
658 compatible = "st,stm32-ltdc";
659 reg = <0x40016800 0x200>;
660 interrupts = <88>, <89>;
661 resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
662 clocks = <&rcc 1 CLK_LCD>;
668 compatible = "st,stm32f4-crc";
669 reg = <0x40023000 0x400>;
670 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(CRC)>;
677 compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
678 reg = <0x40023800 0x400>;
679 clocks = <&clk_hse>, <&clk_i2s_ckin>;
680 st,syscfg = <&pwrcfg>;
681 assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
682 assigned-clock-rates = <1000000>;
685 dma1: dma-controller@40026000 {
686 compatible = "st,stm32-dma";
687 reg = <0x40026000 0x400>;
696 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA1)>;
700 dma2: dma-controller@40026400 {
701 compatible = "st,stm32-dma";
702 reg = <0x40026400 0x400>;
711 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2)>;
716 mac: ethernet@40028000 {
717 compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
718 reg = <0x40028000 0x8000>;
719 reg-names = "stmmaceth";
721 interrupt-names = "macirq";
722 clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
723 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(ETHMAC)>,
724 <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACTX)>,
725 <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACRX)>;
726 st,syscon = <&syscfg 0x4>;
732 usbotg_hs: usb@40040000 {
733 compatible = "snps,dwc2";
734 reg = <0x40040000 0x40000>;
736 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHS)>;
741 usbotg_fs: usb@50000000 {
742 compatible = "st,stm32f4x9-fsotg";
743 reg = <0x50000000 0x40000>;
745 clocks = <&rcc 0 39>;
750 dcmi: dcmi@50050000 {
751 compatible = "st,stm32-dcmi";
752 reg = <0x50050000 0x400>;
754 resets = <&rcc STM32F4_AHB2_RESET(DCMI)>;
755 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>;
756 clock-names = "mclk";
757 pinctrl-names = "default";
758 pinctrl-0 = <&dcmi_pins>;
759 dmas = <&dma2 1 1 0x414 0x3>;
765 compatible = "st,stm32-rng";
766 reg = <0x50060800 0x400>;
768 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>;
775 clocks = <&rcc 1 SYSTICK>;