2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public
20 * License along with this file; if not, write to the Free
21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
48 #include "armv7-m.dtsi"
49 #include <dt-bindings/clock/stm32fx-clock.h>
50 #include <dt-bindings/mfd/stm32f4-rcc.h>
59 compatible = "fixed-clock";
60 clock-frequency = <0>;
65 compatible = "fixed-clock";
66 clock-frequency = <32768>;
71 compatible = "fixed-clock";
72 clock-frequency = <32000>;
75 clk_i2s_ckin: i2s-ckin {
77 compatible = "fixed-clock";
78 clock-frequency = <0>;
83 timer2: timer@40000000 {
84 compatible = "st,stm32-timer";
85 reg = <0x40000000 0x400>;
87 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
91 timers2: timers@40000000 {
94 compatible = "st,stm32-timers";
95 reg = <0x40000000 0x400>;
96 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
101 compatible = "st,stm32-pwm";
106 compatible = "st,stm32-timer-trigger";
112 timer3: timer@40000400 {
113 compatible = "st,stm32-timer";
114 reg = <0x40000400 0x400>;
116 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
120 timers3: timers@40000400 {
121 #address-cells = <1>;
123 compatible = "st,stm32-timers";
124 reg = <0x40000400 0x400>;
125 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
130 compatible = "st,stm32-pwm";
135 compatible = "st,stm32-timer-trigger";
141 timer4: timer@40000800 {
142 compatible = "st,stm32-timer";
143 reg = <0x40000800 0x400>;
145 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
149 timers4: timers@40000800 {
150 #address-cells = <1>;
152 compatible = "st,stm32-timers";
153 reg = <0x40000800 0x400>;
154 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
159 compatible = "st,stm32-pwm";
164 compatible = "st,stm32-timer-trigger";
170 timer5: timer@40000c00 {
171 compatible = "st,stm32-timer";
172 reg = <0x40000c00 0x400>;
174 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
177 timers5: timers@40000c00 {
178 #address-cells = <1>;
180 compatible = "st,stm32-timers";
181 reg = <0x40000C00 0x400>;
182 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
187 compatible = "st,stm32-pwm";
192 compatible = "st,stm32-timer-trigger";
198 timer6: timer@40001000 {
199 compatible = "st,stm32-timer";
200 reg = <0x40001000 0x400>;
202 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
206 timers6: timers@40001000 {
207 #address-cells = <1>;
209 compatible = "st,stm32-timers";
210 reg = <0x40001000 0x400>;
211 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
216 compatible = "st,stm32-timer-trigger";
222 timer7: timer@40001400 {
223 compatible = "st,stm32-timer";
224 reg = <0x40001400 0x400>;
226 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
230 timers7: timers@40001400 {
231 #address-cells = <1>;
233 compatible = "st,stm32-timers";
234 reg = <0x40001400 0x400>;
235 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
240 compatible = "st,stm32-timer-trigger";
246 timers12: timers@40001800 {
247 #address-cells = <1>;
249 compatible = "st,stm32-timers";
250 reg = <0x40001800 0x400>;
251 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>;
256 compatible = "st,stm32-pwm";
261 compatible = "st,stm32-timer-trigger";
267 timers13: timers@40001c00 {
268 #address-cells = <1>;
270 compatible = "st,stm32-timers";
271 reg = <0x40001C00 0x400>;
272 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
277 compatible = "st,stm32-pwm";
282 timers14: timers@40002000 {
283 #address-cells = <1>;
285 compatible = "st,stm32-timers";
286 reg = <0x40002000 0x400>;
287 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
292 compatible = "st,stm32-pwm";
298 compatible = "st,stm32-rtc";
299 reg = <0x40002800 0x400>;
300 clocks = <&rcc 1 CLK_RTC>;
301 clock-names = "ck_rtc";
302 assigned-clocks = <&rcc 1 CLK_RTC>;
303 assigned-clock-parents = <&rcc 1 CLK_LSE>;
304 interrupt-parent = <&exti>;
306 interrupt-names = "alarm";
307 st,syscfg = <&pwrcfg 0x00 0x100>;
311 iwdg: watchdog@40003000 {
312 compatible = "st,stm32-iwdg";
313 reg = <0x40003000 0x400>;
319 usart2: serial@40004400 {
320 compatible = "st,stm32-uart";
321 reg = <0x40004400 0x400>;
323 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART2)>;
327 usart3: serial@40004800 {
328 compatible = "st,stm32-uart";
329 reg = <0x40004800 0x400>;
331 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART3)>;
333 dmas = <&dma1 1 4 0x400 0x0>,
334 <&dma1 3 4 0x400 0x0>;
335 dma-names = "rx", "tx";
338 usart4: serial@40004c00 {
339 compatible = "st,stm32-uart";
340 reg = <0x40004c00 0x400>;
342 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART4)>;
346 usart5: serial@40005000 {
347 compatible = "st,stm32-uart";
348 reg = <0x40005000 0x400>;
350 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART5)>;
355 compatible = "st,stm32f4-i2c";
356 reg = <0x40005400 0x400>;
359 resets = <&rcc STM32F4_APB1_RESET(I2C1)>;
360 clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>;
361 #address-cells = <1>;
367 compatible = "st,stm32f4-dac-core";
368 reg = <0x40007400 0x400>;
369 resets = <&rcc STM32F4_APB1_RESET(DAC)>;
370 clocks = <&rcc 0 STM32F4_APB1_CLOCK(DAC)>;
371 clock-names = "pclk";
372 #address-cells = <1>;
377 compatible = "st,stm32-dac";
378 #io-channels-cells = <1>;
384 compatible = "st,stm32-dac";
385 #io-channels-cells = <1>;
391 usart7: serial@40007800 {
392 compatible = "st,stm32-uart";
393 reg = <0x40007800 0x400>;
395 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART7)>;
399 usart8: serial@40007c00 {
400 compatible = "st,stm32-uart";
401 reg = <0x40007c00 0x400>;
403 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART8)>;
407 timers1: timers@40010000 {
408 #address-cells = <1>;
410 compatible = "st,stm32-timers";
411 reg = <0x40010000 0x400>;
412 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM1)>;
417 compatible = "st,stm32-pwm";
422 compatible = "st,stm32-timer-trigger";
428 timers8: timers@40010400 {
429 #address-cells = <1>;
431 compatible = "st,stm32-timers";
432 reg = <0x40010400 0x400>;
433 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM8)>;
438 compatible = "st,stm32-pwm";
443 compatible = "st,stm32-timer-trigger";
449 usart1: serial@40011000 {
450 compatible = "st,stm32-uart";
451 reg = <0x40011000 0x400>;
453 clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART1)>;
455 dmas = <&dma2 2 4 0x400 0x0>,
456 <&dma2 7 4 0x400 0x0>;
457 dma-names = "rx", "tx";
460 usart6: serial@40011400 {
461 compatible = "st,stm32-uart";
462 reg = <0x40011400 0x400>;
464 clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART6)>;
469 compatible = "st,stm32f4-adc-core";
470 reg = <0x40012000 0x400>;
472 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
474 interrupt-controller;
475 #interrupt-cells = <1>;
476 #address-cells = <1>;
481 compatible = "st,stm32f4-adc";
482 #io-channel-cells = <1>;
484 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
485 interrupt-parent = <&adc>;
487 dmas = <&dma2 0 0 0x400 0x0>;
493 compatible = "st,stm32f4-adc";
494 #io-channel-cells = <1>;
496 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC2)>;
497 interrupt-parent = <&adc>;
499 dmas = <&dma2 3 1 0x400 0x0>;
505 compatible = "st,stm32f4-adc";
506 #io-channel-cells = <1>;
508 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC3)>;
509 interrupt-parent = <&adc>;
511 dmas = <&dma2 1 2 0x400 0x0>;
517 sdio: sdio@40012c00 {
518 compatible = "arm,pl180", "arm,primecell";
519 arm,primecell-periphid = <0x00880180>;
520 reg = <0x40012c00 0x400>;
521 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SDIO)>;
522 clock-names = "apb_pclk";
524 max-frequency = <48000000>;
528 syscfg: system-config@40013800 {
529 compatible = "syscon";
530 reg = <0x40013800 0x400>;
533 exti: interrupt-controller@40013c00 {
534 compatible = "st,stm32-exti";
535 interrupt-controller;
536 #interrupt-cells = <2>;
537 reg = <0x40013C00 0x400>;
538 interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
541 timers9: timers@40014000 {
542 #address-cells = <1>;
544 compatible = "st,stm32-timers";
545 reg = <0x40014000 0x400>;
546 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM9)>;
551 compatible = "st,stm32-pwm";
556 compatible = "st,stm32-timer-trigger";
562 timers10: timers@40014400 {
563 #address-cells = <1>;
565 compatible = "st,stm32-timers";
566 reg = <0x40014400 0x400>;
567 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>;
572 compatible = "st,stm32-pwm";
577 timers11: timers@40014800 {
578 #address-cells = <1>;
580 compatible = "st,stm32-timers";
581 reg = <0x40014800 0x400>;
582 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>;
587 compatible = "st,stm32-pwm";
592 pwrcfg: power-config@40007000 {
593 compatible = "syscon";
594 reg = <0x40007000 0x400>;
597 ltdc: display-controller@40016800 {
598 compatible = "st,stm32-ltdc";
599 reg = <0x40016800 0x200>;
600 interrupts = <88>, <89>;
601 resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
602 clocks = <&rcc 1 CLK_LCD>;
608 compatible = "st,stm32f4-crc";
609 reg = <0x40023000 0x400>;
610 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(CRC)>;
617 compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
618 reg = <0x40023800 0x400>;
619 clocks = <&clk_hse>, <&clk_i2s_ckin>;
620 st,syscfg = <&pwrcfg>;
621 assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
622 assigned-clock-rates = <1000000>;
625 dma1: dma-controller@40026000 {
626 compatible = "st,stm32-dma";
627 reg = <0x40026000 0x400>;
636 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA1)>;
640 dma2: dma-controller@40026400 {
641 compatible = "st,stm32-dma";
642 reg = <0x40026400 0x400>;
651 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2)>;
656 mac: ethernet@40028000 {
657 compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
658 reg = <0x40028000 0x8000>;
659 reg-names = "stmmaceth";
661 interrupt-names = "macirq";
662 clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
663 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(ETHMAC)>,
664 <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACTX)>,
665 <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACRX)>;
666 st,syscon = <&syscfg 0x4>;
672 usbotg_hs: usb@40040000 {
673 compatible = "snps,dwc2";
674 reg = <0x40040000 0x40000>;
676 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHS)>;
681 usbotg_fs: usb@50000000 {
682 compatible = "st,stm32f4x9-fsotg";
683 reg = <0x50000000 0x40000>;
685 clocks = <&rcc 0 39>;
690 dcmi: dcmi@50050000 {
691 compatible = "st,stm32-dcmi";
692 reg = <0x50050000 0x400>;
694 resets = <&rcc STM32F4_AHB2_RESET(DCMI)>;
695 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>;
696 clock-names = "mclk";
697 pinctrl-names = "default";
698 pinctrl-0 = <&dcmi_pins>;
699 dmas = <&dma2 1 1 0x414 0x3>;
705 compatible = "st,stm32-rng";
706 reg = <0x50060800 0x400>;
708 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>;
715 clocks = <&rcc 1 SYSTICK>;