2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public
20 * License along with this file; if not, write to the Free
21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
48 #include "skeleton.dtsi"
49 #include "armv7-m.dtsi"
50 #include <dt-bindings/clock/stm32fx-clock.h>
51 #include <dt-bindings/mfd/stm32f4-rcc.h>
57 compatible = "fixed-clock";
58 clock-frequency = <0>;
63 compatible = "fixed-clock";
64 clock-frequency = <32768>;
69 compatible = "fixed-clock";
70 clock-frequency = <32000>;
73 clk_i2s_ckin: i2s-ckin {
75 compatible = "fixed-clock";
76 clock-frequency = <0>;
81 timer2: timer@40000000 {
82 compatible = "st,stm32-timer";
83 reg = <0x40000000 0x400>;
85 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
89 timers2: timers@40000000 {
92 compatible = "st,stm32-timers";
93 reg = <0x40000000 0x400>;
94 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
99 compatible = "st,stm32-pwm";
104 compatible = "st,stm32-timer-trigger";
110 timer3: timer@40000400 {
111 compatible = "st,stm32-timer";
112 reg = <0x40000400 0x400>;
114 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
118 timers3: timers@40000400 {
119 #address-cells = <1>;
121 compatible = "st,stm32-timers";
122 reg = <0x40000400 0x400>;
123 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
128 compatible = "st,stm32-pwm";
133 compatible = "st,stm32-timer-trigger";
139 timer4: timer@40000800 {
140 compatible = "st,stm32-timer";
141 reg = <0x40000800 0x400>;
143 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
147 timers4: timers@40000800 {
148 #address-cells = <1>;
150 compatible = "st,stm32-timers";
151 reg = <0x40000800 0x400>;
152 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
157 compatible = "st,stm32-pwm";
162 compatible = "st,stm32-timer-trigger";
168 timer5: timer@40000c00 {
169 compatible = "st,stm32-timer";
170 reg = <0x40000c00 0x400>;
172 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
175 timers5: timers@40000c00 {
176 #address-cells = <1>;
178 compatible = "st,stm32-timers";
179 reg = <0x40000C00 0x400>;
180 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
185 compatible = "st,stm32-pwm";
190 compatible = "st,stm32-timer-trigger";
196 timer6: timer@40001000 {
197 compatible = "st,stm32-timer";
198 reg = <0x40001000 0x400>;
200 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
204 timers6: timers@40001000 {
205 #address-cells = <1>;
207 compatible = "st,stm32-timers";
208 reg = <0x40001000 0x400>;
209 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
214 compatible = "st,stm32-timer-trigger";
220 timer7: timer@40001400 {
221 compatible = "st,stm32-timer";
222 reg = <0x40001400 0x400>;
224 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
228 timers7: timers@40001400 {
229 #address-cells = <1>;
231 compatible = "st,stm32-timers";
232 reg = <0x40001400 0x400>;
233 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
238 compatible = "st,stm32-timer-trigger";
244 timers12: timers@40001800 {
245 #address-cells = <1>;
247 compatible = "st,stm32-timers";
248 reg = <0x40001800 0x400>;
249 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>;
254 compatible = "st,stm32-pwm";
259 compatible = "st,stm32-timer-trigger";
265 timers13: timers@40001c00 {
266 #address-cells = <1>;
268 compatible = "st,stm32-timers";
269 reg = <0x40001C00 0x400>;
270 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
275 compatible = "st,stm32-pwm";
280 timers14: timers@40002000 {
281 #address-cells = <1>;
283 compatible = "st,stm32-timers";
284 reg = <0x40002000 0x400>;
285 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
290 compatible = "st,stm32-pwm";
296 compatible = "st,stm32-rtc";
297 reg = <0x40002800 0x400>;
298 clocks = <&rcc 1 CLK_RTC>;
299 clock-names = "ck_rtc";
300 assigned-clocks = <&rcc 1 CLK_RTC>;
301 assigned-clock-parents = <&rcc 1 CLK_LSE>;
302 interrupt-parent = <&exti>;
304 interrupt-names = "alarm";
305 st,syscfg = <&pwrcfg 0x00 0x100>;
309 iwdg: watchdog@40003000 {
310 compatible = "st,stm32-iwdg";
311 reg = <0x40003000 0x400>;
317 usart2: serial@40004400 {
318 compatible = "st,stm32-uart";
319 reg = <0x40004400 0x400>;
321 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART2)>;
325 usart3: serial@40004800 {
326 compatible = "st,stm32-uart";
327 reg = <0x40004800 0x400>;
329 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART3)>;
331 dmas = <&dma1 1 4 0x400 0x0>,
332 <&dma1 3 4 0x400 0x0>;
333 dma-names = "rx", "tx";
336 usart4: serial@40004c00 {
337 compatible = "st,stm32-uart";
338 reg = <0x40004c00 0x400>;
340 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART4)>;
344 usart5: serial@40005000 {
345 compatible = "st,stm32-uart";
346 reg = <0x40005000 0x400>;
348 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART5)>;
353 compatible = "st,stm32f4-i2c";
354 reg = <0x40005400 0x400>;
357 resets = <&rcc STM32F4_APB1_RESET(I2C1)>;
358 clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>;
359 #address-cells = <1>;
365 compatible = "st,stm32f4-dac-core";
366 reg = <0x40007400 0x400>;
367 resets = <&rcc STM32F4_APB1_RESET(DAC)>;
368 clocks = <&rcc 0 STM32F4_APB1_CLOCK(DAC)>;
369 clock-names = "pclk";
370 #address-cells = <1>;
375 compatible = "st,stm32-dac";
376 #io-channels-cells = <1>;
382 compatible = "st,stm32-dac";
383 #io-channels-cells = <1>;
389 usart7: serial@40007800 {
390 compatible = "st,stm32-uart";
391 reg = <0x40007800 0x400>;
393 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART7)>;
397 usart8: serial@40007c00 {
398 compatible = "st,stm32-uart";
399 reg = <0x40007c00 0x400>;
401 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART8)>;
405 timers1: timers@40010000 {
406 #address-cells = <1>;
408 compatible = "st,stm32-timers";
409 reg = <0x40010000 0x400>;
410 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM1)>;
415 compatible = "st,stm32-pwm";
420 compatible = "st,stm32-timer-trigger";
426 timers8: timers@40010400 {
427 #address-cells = <1>;
429 compatible = "st,stm32-timers";
430 reg = <0x40010400 0x400>;
431 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM8)>;
436 compatible = "st,stm32-pwm";
441 compatible = "st,stm32-timer-trigger";
447 usart1: serial@40011000 {
448 compatible = "st,stm32-uart";
449 reg = <0x40011000 0x400>;
451 clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART1)>;
453 dmas = <&dma2 2 4 0x400 0x0>,
454 <&dma2 7 4 0x400 0x0>;
455 dma-names = "rx", "tx";
458 usart6: serial@40011400 {
459 compatible = "st,stm32-uart";
460 reg = <0x40011400 0x400>;
462 clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART6)>;
467 compatible = "st,stm32f4-adc-core";
468 reg = <0x40012000 0x400>;
470 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
472 interrupt-controller;
473 #interrupt-cells = <1>;
474 #address-cells = <1>;
479 compatible = "st,stm32f4-adc";
480 #io-channel-cells = <1>;
482 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
483 interrupt-parent = <&adc>;
485 dmas = <&dma2 0 0 0x400 0x0>;
491 compatible = "st,stm32f4-adc";
492 #io-channel-cells = <1>;
494 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC2)>;
495 interrupt-parent = <&adc>;
497 dmas = <&dma2 3 1 0x400 0x0>;
503 compatible = "st,stm32f4-adc";
504 #io-channel-cells = <1>;
506 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC3)>;
507 interrupt-parent = <&adc>;
509 dmas = <&dma2 1 2 0x400 0x0>;
515 sdio: sdio@40012c00 {
516 compatible = "arm,pl180", "arm,primecell";
517 arm,primecell-periphid = <0x00880180>;
518 reg = <0x40012c00 0x400>;
519 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SDIO)>;
520 clock-names = "apb_pclk";
522 max-frequency = <48000000>;
526 syscfg: system-config@40013800 {
527 compatible = "syscon";
528 reg = <0x40013800 0x400>;
531 exti: interrupt-controller@40013c00 {
532 compatible = "st,stm32-exti";
533 interrupt-controller;
534 #interrupt-cells = <2>;
535 reg = <0x40013C00 0x400>;
536 interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
539 timers9: timers@40014000 {
540 #address-cells = <1>;
542 compatible = "st,stm32-timers";
543 reg = <0x40014000 0x400>;
544 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM9)>;
549 compatible = "st,stm32-pwm";
554 compatible = "st,stm32-timer-trigger";
560 timers10: timers@40014400 {
561 #address-cells = <1>;
563 compatible = "st,stm32-timers";
564 reg = <0x40014400 0x400>;
565 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>;
570 compatible = "st,stm32-pwm";
575 timers11: timers@40014800 {
576 #address-cells = <1>;
578 compatible = "st,stm32-timers";
579 reg = <0x40014800 0x400>;
580 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>;
585 compatible = "st,stm32-pwm";
590 pwrcfg: power-config@40007000 {
591 compatible = "syscon";
592 reg = <0x40007000 0x400>;
595 ltdc: display-controller@40016800 {
596 compatible = "st,stm32-ltdc";
597 reg = <0x40016800 0x200>;
598 interrupts = <88>, <89>;
599 resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
600 clocks = <&rcc 1 CLK_LCD>;
606 compatible = "st,stm32f4-crc";
607 reg = <0x40023000 0x400>;
608 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(CRC)>;
615 compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
616 reg = <0x40023800 0x400>;
617 clocks = <&clk_hse>, <&clk_i2s_ckin>;
618 st,syscfg = <&pwrcfg>;
619 assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
620 assigned-clock-rates = <1000000>;
623 dma1: dma-controller@40026000 {
624 compatible = "st,stm32-dma";
625 reg = <0x40026000 0x400>;
634 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA1)>;
638 dma2: dma-controller@40026400 {
639 compatible = "st,stm32-dma";
640 reg = <0x40026400 0x400>;
649 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2)>;
654 mac: ethernet@40028000 {
655 compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
656 reg = <0x40028000 0x8000>;
657 reg-names = "stmmaceth";
659 interrupt-names = "macirq";
660 clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
661 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(ETHMAC)>,
662 <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACTX)>,
663 <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACRX)>;
664 st,syscon = <&syscfg 0x4>;
670 usbotg_hs: usb@40040000 {
671 compatible = "snps,dwc2";
672 reg = <0x40040000 0x40000>;
674 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHS)>;
679 usbotg_fs: usb@50000000 {
680 compatible = "st,stm32f4x9-fsotg";
681 reg = <0x50000000 0x40000>;
683 clocks = <&rcc 0 39>;
688 dcmi: dcmi@50050000 {
689 compatible = "st,stm32-dcmi";
690 reg = <0x50050000 0x400>;
692 resets = <&rcc STM32F4_AHB2_RESET(DCMI)>;
693 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>;
694 clock-names = "mclk";
695 pinctrl-names = "default";
696 pinctrl-0 = <&dcmi_pins>;
697 dmas = <&dma2 1 1 0x414 0x3>;
703 compatible = "st,stm32-rng";
704 reg = <0x50060800 0x400>;
706 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>;
713 clocks = <&rcc 1 SYSTICK>;