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[mirror_ubuntu-bionic-kernel.git] / arch / arm / boot / dts / stm32f746.dtsi
1 /*
2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43 #include "skeleton.dtsi"
44 #include "armv7-m.dtsi"
45 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
46 #include <dt-bindings/clock/stm32fx-clock.h>
47 #include <dt-bindings/mfd/stm32f7-rcc.h>
48
49 / {
50 clocks {
51 clk_hse: clk-hse {
52 #clock-cells = <0>;
53 compatible = "fixed-clock";
54 clock-frequency = <0>;
55 };
56
57 clk-lse {
58 #clock-cells = <0>;
59 compatible = "fixed-clock";
60 clock-frequency = <32768>;
61 };
62
63 clk-lsi {
64 #clock-cells = <0>;
65 compatible = "fixed-clock";
66 clock-frequency = <32000>;
67 };
68
69 clk_i2s_ckin: clk-i2s-ckin {
70 #clock-cells = <0>;
71 compatible = "fixed-clock";
72 clock-frequency = <48000000>;
73 };
74 };
75
76 soc {
77 timer2: timer@40000000 {
78 compatible = "st,stm32-timer";
79 reg = <0x40000000 0x400>;
80 interrupts = <28>;
81 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
82 status = "disabled";
83 };
84
85 timers2: timers@40000000 {
86 #address-cells = <1>;
87 #size-cells = <0>;
88 compatible = "st,stm32-timers";
89 reg = <0x40000000 0x400>;
90 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
91 clock-names = "int";
92 status = "disabled";
93
94 pwm {
95 compatible = "st,stm32-pwm";
96 status = "disabled";
97 };
98
99 timer@1 {
100 compatible = "st,stm32-timer-trigger";
101 reg = <1>;
102 status = "disabled";
103 };
104 };
105
106 timer3: timer@40000400 {
107 compatible = "st,stm32-timer";
108 reg = <0x40000400 0x400>;
109 interrupts = <29>;
110 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
111 status = "disabled";
112 };
113
114 timers3: timers@40000400 {
115 #address-cells = <1>;
116 #size-cells = <0>;
117 compatible = "st,stm32-timers";
118 reg = <0x40000400 0x400>;
119 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
120 clock-names = "int";
121 status = "disabled";
122
123 pwm {
124 compatible = "st,stm32-pwm";
125 status = "disabled";
126 };
127
128 timer@2 {
129 compatible = "st,stm32-timer-trigger";
130 reg = <2>;
131 status = "disabled";
132 };
133 };
134
135 timer4: timer@40000800 {
136 compatible = "st,stm32-timer";
137 reg = <0x40000800 0x400>;
138 interrupts = <30>;
139 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
140 status = "disabled";
141 };
142
143 timers4: timers@40000800 {
144 #address-cells = <1>;
145 #size-cells = <0>;
146 compatible = "st,stm32-timers";
147 reg = <0x40000800 0x400>;
148 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
149 clock-names = "int";
150 status = "disabled";
151
152 pwm {
153 compatible = "st,stm32-pwm";
154 status = "disabled";
155 };
156
157 timer@3 {
158 compatible = "st,stm32-timer-trigger";
159 reg = <3>;
160 status = "disabled";
161 };
162 };
163
164 timer5: timer@40000c00 {
165 compatible = "st,stm32-timer";
166 reg = <0x40000c00 0x400>;
167 interrupts = <50>;
168 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
169 };
170
171 timers5: timers@40000c00 {
172 #address-cells = <1>;
173 #size-cells = <0>;
174 compatible = "st,stm32-timers";
175 reg = <0x40000C00 0x400>;
176 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
177 clock-names = "int";
178 status = "disabled";
179
180 pwm {
181 compatible = "st,stm32-pwm";
182 status = "disabled";
183 };
184
185 timer@4 {
186 compatible = "st,stm32-timer-trigger";
187 reg = <4>;
188 status = "disabled";
189 };
190 };
191
192 timer6: timer@40001000 {
193 compatible = "st,stm32-timer";
194 reg = <0x40001000 0x400>;
195 interrupts = <54>;
196 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
197 status = "disabled";
198 };
199
200 timers6: timers@40001000 {
201 #address-cells = <1>;
202 #size-cells = <0>;
203 compatible = "st,stm32-timers";
204 reg = <0x40001000 0x400>;
205 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
206 clock-names = "int";
207 status = "disabled";
208
209 timer@5 {
210 compatible = "st,stm32-timer-trigger";
211 reg = <5>;
212 status = "disabled";
213 };
214 };
215
216 timer7: timer@40001400 {
217 compatible = "st,stm32-timer";
218 reg = <0x40001400 0x400>;
219 interrupts = <55>;
220 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
221 status = "disabled";
222 };
223
224 timers7: timers@40001400 {
225 #address-cells = <1>;
226 #size-cells = <0>;
227 compatible = "st,stm32-timers";
228 reg = <0x40001400 0x400>;
229 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
230 clock-names = "int";
231 status = "disabled";
232
233 timer@6 {
234 compatible = "st,stm32-timer-trigger";
235 reg = <6>;
236 status = "disabled";
237 };
238 };
239
240 timers12: timers@40001800 {
241 #address-cells = <1>;
242 #size-cells = <0>;
243 compatible = "st,stm32-timers";
244 reg = <0x40001800 0x400>;
245 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM12)>;
246 clock-names = "int";
247 status = "disabled";
248
249 pwm {
250 compatible = "st,stm32-pwm";
251 status = "disabled";
252 };
253
254 timer@11 {
255 compatible = "st,stm32-timer-trigger";
256 reg = <11>;
257 status = "disabled";
258 };
259 };
260
261 timers13: timers@40001c00 {
262 #address-cells = <1>;
263 #size-cells = <0>;
264 compatible = "st,stm32-timers";
265 reg = <0x40001C00 0x400>;
266 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>;
267 clock-names = "int";
268 status = "disabled";
269
270 pwm {
271 compatible = "st,stm32-pwm";
272 status = "disabled";
273 };
274 };
275
276 timers14: timers@40002000 {
277 #address-cells = <1>;
278 #size-cells = <0>;
279 compatible = "st,stm32-timers";
280 reg = <0x40002000 0x400>;
281 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>;
282 clock-names = "int";
283 status = "disabled";
284
285 pwm {
286 compatible = "st,stm32-pwm";
287 status = "disabled";
288 };
289 };
290
291 rtc: rtc@40002800 {
292 compatible = "st,stm32-rtc";
293 reg = <0x40002800 0x400>;
294 clocks = <&rcc 1 CLK_RTC>;
295 clock-names = "ck_rtc";
296 assigned-clocks = <&rcc 1 CLK_RTC>;
297 assigned-clock-parents = <&rcc 1 CLK_LSE>;
298 interrupt-parent = <&exti>;
299 interrupts = <17 1>;
300 interrupt-names = "alarm";
301 st,syscfg = <&pwrcfg>;
302 status = "disabled";
303 };
304
305 usart2: serial@40004400 {
306 compatible = "st,stm32f7-uart";
307 reg = <0x40004400 0x400>;
308 interrupts = <38>;
309 clocks = <&rcc 1 CLK_USART2>;
310 status = "disabled";
311 };
312
313 usart3: serial@40004800 {
314 compatible = "st,stm32f7-uart";
315 reg = <0x40004800 0x400>;
316 interrupts = <39>;
317 clocks = <&rcc 1 CLK_USART3>;
318 status = "disabled";
319 };
320
321 usart4: serial@40004c00 {
322 compatible = "st,stm32f7-uart";
323 reg = <0x40004c00 0x400>;
324 interrupts = <52>;
325 clocks = <&rcc 1 CLK_UART4>;
326 status = "disabled";
327 };
328
329 usart5: serial@40005000 {
330 compatible = "st,stm32f7-uart";
331 reg = <0x40005000 0x400>;
332 interrupts = <53>;
333 clocks = <&rcc 1 CLK_UART5>;
334 status = "disabled";
335 };
336
337 i2c1: i2c@40005400 {
338 compatible = "st,stm32f7-i2c";
339 reg = <0x40005400 0x400>;
340 interrupts = <31>,
341 <32>;
342 resets = <&rcc STM32F7_APB1_RESET(I2C1)>;
343 clocks = <&rcc 1 CLK_I2C1>;
344 #address-cells = <1>;
345 #size-cells = <0>;
346 status = "disabled";
347 };
348
349 cec: cec@40006c00 {
350 compatible = "st,stm32-cec";
351 reg = <0x40006C00 0x400>;
352 interrupts = <94>;
353 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>;
354 clock-names = "cec", "hdmi-cec";
355 status = "disabled";
356 };
357
358 usart7: serial@40007800 {
359 compatible = "st,stm32f7-uart";
360 reg = <0x40007800 0x400>;
361 interrupts = <82>;
362 clocks = <&rcc 1 CLK_UART7>;
363 status = "disabled";
364 };
365
366 usart8: serial@40007c00 {
367 compatible = "st,stm32f7-uart";
368 reg = <0x40007c00 0x400>;
369 interrupts = <83>;
370 clocks = <&rcc 1 CLK_UART8>;
371 status = "disabled";
372 };
373
374 timers1: timers@40010000 {
375 #address-cells = <1>;
376 #size-cells = <0>;
377 compatible = "st,stm32-timers";
378 reg = <0x40010000 0x400>;
379 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM1)>;
380 clock-names = "int";
381 status = "disabled";
382
383 pwm {
384 compatible = "st,stm32-pwm";
385 status = "disabled";
386 };
387
388 timer@0 {
389 compatible = "st,stm32-timer-trigger";
390 reg = <0>;
391 status = "disabled";
392 };
393 };
394
395 timers8: timers@40010400 {
396 #address-cells = <1>;
397 #size-cells = <0>;
398 compatible = "st,stm32-timers";
399 reg = <0x40010400 0x400>;
400 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM8)>;
401 clock-names = "int";
402 status = "disabled";
403
404 pwm {
405 compatible = "st,stm32-pwm";
406 status = "disabled";
407 };
408
409 timer@7 {
410 compatible = "st,stm32-timer-trigger";
411 reg = <7>;
412 status = "disabled";
413 };
414 };
415
416 usart1: serial@40011000 {
417 compatible = "st,stm32f7-uart";
418 reg = <0x40011000 0x400>;
419 interrupts = <37>;
420 clocks = <&rcc 1 CLK_USART1>;
421 status = "disabled";
422 };
423
424 usart6: serial@40011400 {
425 compatible = "st,stm32f7-uart";
426 reg = <0x40011400 0x400>;
427 interrupts = <71>;
428 clocks = <&rcc 1 CLK_USART6>;
429 status = "disabled";
430 };
431
432 syscfg: system-config@40013800 {
433 compatible = "syscon";
434 reg = <0x40013800 0x400>;
435 };
436
437 exti: interrupt-controller@40013c00 {
438 compatible = "st,stm32-exti";
439 interrupt-controller;
440 #interrupt-cells = <2>;
441 reg = <0x40013C00 0x400>;
442 interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
443 };
444
445 timers9: timers@40014000 {
446 #address-cells = <1>;
447 #size-cells = <0>;
448 compatible = "st,stm32-timers";
449 reg = <0x40014000 0x400>;
450 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM9)>;
451 clock-names = "int";
452 status = "disabled";
453
454 pwm {
455 compatible = "st,stm32-pwm";
456 status = "disabled";
457 };
458
459 timer@8 {
460 compatible = "st,stm32-timer-trigger";
461 reg = <8>;
462 status = "disabled";
463 };
464 };
465
466 timers10: timers@40014400 {
467 #address-cells = <1>;
468 #size-cells = <0>;
469 compatible = "st,stm32-timers";
470 reg = <0x40014400 0x400>;
471 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>;
472 clock-names = "int";
473 status = "disabled";
474
475 pwm {
476 compatible = "st,stm32-pwm";
477 status = "disabled";
478 };
479 };
480
481 timers11: timers@40014800 {
482 #address-cells = <1>;
483 #size-cells = <0>;
484 compatible = "st,stm32-timers";
485 reg = <0x40014800 0x400>;
486 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>;
487 clock-names = "int";
488 status = "disabled";
489
490 pwm {
491 compatible = "st,stm32-pwm";
492 status = "disabled";
493 };
494 };
495
496 pwrcfg: power-config@40007000 {
497 compatible = "syscon";
498 reg = <0x40007000 0x400>;
499 };
500
501 pin-controller {
502 #address-cells = <1>;
503 #size-cells = <1>;
504 compatible = "st,stm32f746-pinctrl";
505 ranges = <0 0x40020000 0x3000>;
506 interrupt-parent = <&exti>;
507 st,syscfg = <&syscfg 0x8>;
508 pins-are-numbered;
509
510 gpioa: gpio@40020000 {
511 gpio-controller;
512 #gpio-cells = <2>;
513 interrupt-controller;
514 #interrupt-cells = <2>;
515 reg = <0x0 0x400>;
516 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>;
517 st,bank-name = "GPIOA";
518 };
519
520 gpiob: gpio@40020400 {
521 gpio-controller;
522 #gpio-cells = <2>;
523 interrupt-controller;
524 #interrupt-cells = <2>;
525 reg = <0x400 0x400>;
526 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>;
527 st,bank-name = "GPIOB";
528 };
529
530 gpioc: gpio@40020800 {
531 gpio-controller;
532 #gpio-cells = <2>;
533 interrupt-controller;
534 #interrupt-cells = <2>;
535 reg = <0x800 0x400>;
536 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>;
537 st,bank-name = "GPIOC";
538 };
539
540 gpiod: gpio@40020c00 {
541 gpio-controller;
542 #gpio-cells = <2>;
543 interrupt-controller;
544 #interrupt-cells = <2>;
545 reg = <0xc00 0x400>;
546 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>;
547 st,bank-name = "GPIOD";
548 };
549
550 gpioe: gpio@40021000 {
551 gpio-controller;
552 #gpio-cells = <2>;
553 interrupt-controller;
554 #interrupt-cells = <2>;
555 reg = <0x1000 0x400>;
556 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>;
557 st,bank-name = "GPIOE";
558 };
559
560 gpiof: gpio@40021400 {
561 gpio-controller;
562 #gpio-cells = <2>;
563 interrupt-controller;
564 #interrupt-cells = <2>;
565 reg = <0x1400 0x400>;
566 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>;
567 st,bank-name = "GPIOF";
568 };
569
570 gpiog: gpio@40021800 {
571 gpio-controller;
572 #gpio-cells = <2>;
573 interrupt-controller;
574 #interrupt-cells = <2>;
575 reg = <0x1800 0x400>;
576 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>;
577 st,bank-name = "GPIOG";
578 };
579
580 gpioh: gpio@40021c00 {
581 gpio-controller;
582 #gpio-cells = <2>;
583 interrupt-controller;
584 #interrupt-cells = <2>;
585 reg = <0x1c00 0x400>;
586 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>;
587 st,bank-name = "GPIOH";
588 };
589
590 gpioi: gpio@40022000 {
591 gpio-controller;
592 #gpio-cells = <2>;
593 interrupt-controller;
594 #interrupt-cells = <2>;
595 reg = <0x2000 0x400>;
596 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>;
597 st,bank-name = "GPIOI";
598 };
599
600 gpioj: gpio@40022400 {
601 gpio-controller;
602 #gpio-cells = <2>;
603 interrupt-controller;
604 #interrupt-cells = <2>;
605 reg = <0x2400 0x400>;
606 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>;
607 st,bank-name = "GPIOJ";
608 };
609
610 gpiok: gpio@40022800 {
611 gpio-controller;
612 #gpio-cells = <2>;
613 interrupt-controller;
614 #interrupt-cells = <2>;
615 reg = <0x2800 0x400>;
616 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>;
617 st,bank-name = "GPIOK";
618 };
619
620 cec_pins_a: cec@0 {
621 pins {
622 pinmux = <STM32_PINMUX('A', 15, AF4)>; /* HDMI CEC */
623 slew-rate = <0>;
624 drive-open-drain;
625 bias-disable;
626 };
627 };
628
629 usart1_pins_a: usart1@0 {
630 pins1 {
631 pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
632 bias-disable;
633 drive-push-pull;
634 slew-rate = <0>;
635 };
636 pins2 {
637 pinmux = <STM32_PINMUX('A', 10, AF7)>; /* USART1_RX */
638 bias-disable;
639 };
640 };
641
642 usart1_pins_b: usart1@1 {
643 pins1 {
644 pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
645 bias-disable;
646 drive-push-pull;
647 slew-rate = <0>;
648 };
649 pins2 {
650 pinmux = <STM32_PINMUX('B', 7, AF7)>; /* USART1_RX */
651 bias-disable;
652 };
653 };
654
655 i2c1_pins_b: i2c1@0 {
656 pins {
657 pinmux = <STM32_PINMUX('B', 9, AF4)>, /* I2C1 SDA */
658 <STM32_PINMUX('B', 8, AF4)>; /* I2C1 SCL */
659 bias-disable;
660 drive-open-drain;
661 slew-rate = <0>;
662 };
663 };
664
665 usbotg_hs_pins_a: usbotg-hs@0 {
666 pins {
667 pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */
668 <STM32_PINMUX('I', 11, AF10)>, /* OTG_HS_ULPI_DIR */
669 <STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
670 <STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */
671 <STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */
672 <STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
673 <STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
674 <STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
675 <STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
676 <STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
677 <STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
678 <STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */
679 bias-disable;
680 drive-push-pull;
681 slew-rate = <2>;
682 };
683 };
684
685 usbotg_hs_pins_b: usbotg-hs@1 {
686 pins {
687 pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */
688 <STM32_PINMUX('C', 2, AF10)>, /* OTG_HS_ULPI_DIR */
689 <STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
690 <STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */
691 <STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */
692 <STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
693 <STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
694 <STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
695 <STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
696 <STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
697 <STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
698 <STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */
699 bias-disable;
700 drive-push-pull;
701 slew-rate = <2>;
702 };
703 };
704
705 usbotg_fs_pins_a: usbotg-fs@0 {
706 pins {
707 pinmux = <STM32_PINMUX('A', 10, AF10)>, /* OTG_FS_ID */
708 <STM32_PINMUX('A', 11, AF10)>, /* OTG_FS_DM */
709 <STM32_PINMUX('A', 12, AF10)>; /* OTG_FS_DP */
710 bias-disable;
711 drive-push-pull;
712 slew-rate = <2>;
713 };
714 };
715 };
716
717 crc: crc@40023000 {
718 compatible = "st,stm32f7-crc";
719 reg = <0x40023000 0x400>;
720 clocks = <&rcc 0 12>;
721 status = "disabled";
722 };
723
724 rcc: rcc@40023800 {
725 #reset-cells = <1>;
726 #clock-cells = <2>;
727 compatible = "st,stm32f746-rcc", "st,stm32-rcc";
728 reg = <0x40023800 0x400>;
729 clocks = <&clk_hse>, <&clk_i2s_ckin>;
730 st,syscfg = <&pwrcfg>;
731 assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
732 assigned-clock-rates = <1000000>;
733 };
734
735 dma1: dma@40026000 {
736 compatible = "st,stm32-dma";
737 reg = <0x40026000 0x400>;
738 interrupts = <11>,
739 <12>,
740 <13>,
741 <14>,
742 <15>,
743 <16>,
744 <17>,
745 <47>;
746 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA1)>;
747 #dma-cells = <4>;
748 status = "disabled";
749 };
750
751 dma2: dma@40026400 {
752 compatible = "st,stm32-dma";
753 reg = <0x40026400 0x400>;
754 interrupts = <56>,
755 <57>,
756 <58>,
757 <59>,
758 <60>,
759 <68>,
760 <69>,
761 <70>;
762 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA2)>;
763 #dma-cells = <4>;
764 st,mem2mem;
765 status = "disabled";
766 };
767
768 usbotg_hs: usb@40040000 {
769 compatible = "st,stm32f7-hsotg";
770 reg = <0x40040000 0x40000>;
771 interrupts = <77>;
772 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHS)>;
773 clock-names = "otg";
774 status = "disabled";
775 };
776
777 usbotg_fs: usb@50000000 {
778 compatible = "st,stm32f4x9-fsotg";
779 reg = <0x50000000 0x40000>;
780 interrupts = <67>;
781 clocks = <&rcc 0 STM32F7_AHB2_CLOCK(OTGFS)>;
782 clock-names = "otg";
783 status = "disabled";
784 };
785 };
786 };
787
788 &systick {
789 clocks = <&rcc 1 0>;
790 status = "okay";
791 };
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