arch/arm/boot/dts/sun4i-a10.dtsi

   1 /*
   2  * Copyright 2012 Stefan Roese
   3  * Stefan Roese <sr@denx.de>
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 /include/ "skeleton.dtsi"
  14
  15 / {
  16         interrupt-parent = <&intc>;
  17
  18         cpus {
  19                 cpu@0 {
  20                         device_type = "cpu";
  21                         compatible = "arm,cortex-a8";
  22                         reg = <0x0>;
  23                 };
  24         };
  25
  26         memory {
  27                 reg = <0x40000000 0x80000000>;
  28         };
  29
  30         clocks {
  31                 #address-cells = <1>;
  32                 #size-cells = <1>;
  33                 ranges;
  34
  35                 /*
  36                  * This is a dummy clock, to be used as placeholder on
  37                  * other mux clocks when a specific parent clock is not
  38                  * yet implemented. It should be dropped when the driver
  39                  * is complete.
  40                  */
  41                 dummy: dummy {
  42                         #clock-cells = <0>;
  43                         compatible = "fixed-clock";
  44                         clock-frequency = <0>;
  45                 };
  46
  47                 osc24M: osc24M@01c20050 {
  48                         #clock-cells = <0>;
  49                         compatible = "allwinner,sun4i-osc-clk";
  50                         reg = <0x01c20050 0x4>;
  51                         clock-frequency = <24000000>;
  52                 };
  53
  54                 osc32k: osc32k {
  55                         #clock-cells = <0>;
  56                         compatible = "fixed-clock";
  57                         clock-frequency = <32768>;
  58                 };
  59
  60                 pll1: pll1@01c20000 {
  61                         #clock-cells = <0>;
  62                         compatible = "allwinner,sun4i-pll1-clk";
  63                         reg = <0x01c20000 0x4>;
  64                         clocks = <&osc24M>;
  65                 };
  66
  67                 /* dummy is 200M */
  68                 cpu: cpu@01c20054 {
  69                         #clock-cells = <0>;
  70                         compatible = "allwinner,sun4i-cpu-clk";
  71                         reg = <0x01c20054 0x4>;
  72                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
  73                 };
  74
  75                 axi: axi@01c20054 {
  76                         #clock-cells = <0>;
  77                         compatible = "allwinner,sun4i-axi-clk";
  78                         reg = <0x01c20054 0x4>;
  79                         clocks = <&cpu>;
  80                 };
  81
  82                 axi_gates: axi_gates@01c2005c {
  83                         #clock-cells = <1>;
  84                         compatible = "allwinner,sun4i-axi-gates-clk";
  85                         reg = <0x01c2005c 0x4>;
  86                         clocks = <&axi>;
  87                         clock-output-names = "axi_dram";
  88                 };
  89
  90                 ahb: ahb@01c20054 {
  91                         #clock-cells = <0>;
  92                         compatible = "allwinner,sun4i-ahb-clk";
  93                         reg = <0x01c20054 0x4>;
  94                         clocks = <&axi>;
  95                 };
  96
  97                 ahb_gates: ahb_gates@01c20060 {
  98                         #clock-cells = <1>;
  99                         compatible = "allwinner,sun4i-ahb-gates-clk";
 100                         reg = <0x01c20060 0x8>;
 101                         clocks = <&ahb>;
 102                         clock-output-names = "ahb_usb0", "ahb_ehci0",
 103                                 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
 104                                 "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
 105                                 "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
 106                                 "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts",
 107                                 "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
 108                                 "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
 109                                 "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
 110                                 "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
 111                                 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
 112                                 "ahb_de_fe1", "ahb_mp", "ahb_mali400";
 113                 };
 114
 115                 apb0: apb0@01c20054 {
 116                         #clock-cells = <0>;
 117                         compatible = "allwinner,sun4i-apb0-clk";
 118                         reg = <0x01c20054 0x4>;
 119                         clocks = <&ahb>;
 120                 };
 121
 122                 apb0_gates: apb0_gates@01c20068 {
 123                         #clock-cells = <1>;
 124                         compatible = "allwinner,sun4i-apb0-gates-clk";
 125                         reg = <0x01c20068 0x4>;
 126                         clocks = <&apb0>;
 127                         clock-output-names = "apb0_codec", "apb0_spdif",
 128                                 "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
 129                                 "apb0_ir1", "apb0_keypad";
 130                 };
 131
 132                 /* dummy is pll62 */
 133                 apb1_mux: apb1_mux@01c20058 {
 134                         #clock-cells = <0>;
 135                         compatible = "allwinner,sun4i-apb1-mux-clk";
 136                         reg = <0x01c20058 0x4>;
 137                         clocks = <&osc24M>, <&dummy>, <&osc32k>;
 138                 };
 139
 140                 apb1: apb1@01c20058 {
 141                         #clock-cells = <0>;
 142                         compatible = "allwinner,sun4i-apb1-clk";
 143                         reg = <0x01c20058 0x4>;
 144                         clocks = <&apb1_mux>;
 145                 };
 146
 147                 apb1_gates: apb1_gates@01c2006c {
 148                         #clock-cells = <1>;
 149                         compatible = "allwinner,sun4i-apb1-gates-clk";
 150                         reg = <0x01c2006c 0x4>;
 151                         clocks = <&apb1>;
 152                         clock-output-names = "apb1_i2c0", "apb1_i2c1",
 153                                 "apb1_i2c2", "apb1_can", "apb1_scr",
 154                                 "apb1_ps20", "apb1_ps21", "apb1_uart0",
 155                                 "apb1_uart1", "apb1_uart2", "apb1_uart3",
 156                                 "apb1_uart4", "apb1_uart5", "apb1_uart6",
 157                                 "apb1_uart7";
 158                 };
 159         };
 160
 161         soc@01c20000 {
 162                 compatible = "simple-bus";
 163                 #address-cells = <1>;
 164                 #size-cells = <1>;
 165                 reg = <0x01c20000 0x300000>;
 166                 ranges;
 167
 168                 intc: interrupt-controller@01c20400 {
 169                         compatible = "allwinner,sun4i-ic";
 170                         reg = <0x01c20400 0x400>;
 171                         interrupt-controller;
 172                         #interrupt-cells = <1>;
 173                 };
 174
 175                 pio: pinctrl@01c20800 {
 176                         compatible = "allwinner,sun4i-a10-pinctrl";
 177                         reg = <0x01c20800 0x400>;
 178                         clocks = <&apb0_gates 5>;
 179                         gpio-controller;
 180                         #address-cells = <1>;
 181                         #size-cells = <0>;
 182                         #gpio-cells = <3>;
 183
 184                         uart0_pins_a: uart0@0 {
 185                                 allwinner,pins = "PB22", "PB23";
 186                                 allwinner,function = "uart0";
 187                                 allwinner,drive = <0>;
 188                                 allwinner,pull = <0>;
 189                         };
 190
 191                         uart0_pins_b: uart0@1 {
 192                                 allwinner,pins = "PF2", "PF4";
 193                                 allwinner,function = "uart0";
 194                                 allwinner,drive = <0>;
 195                                 allwinner,pull = <0>;
 196                         };
 197
 198                         uart1_pins_a: uart1@0 {
 199                                 allwinner,pins = "PA10", "PA11";
 200                                 allwinner,function = "uart1";
 201                                 allwinner,drive = <0>;
 202                                 allwinner,pull = <0>;
 203                         };
 204                 };
 205
 206                 timer@01c20c00 {
 207                         compatible = "allwinner,sun4i-timer";
 208                         reg = <0x01c20c00 0x90>;
 209                         interrupts = <22>;
 210                         clocks = <&osc24M>;
 211                 };
 212
 213                 wdt: watchdog@01c20c90 {
 214                         compatible = "allwinner,sun4i-wdt";
 215                         reg = <0x01c20c90 0x10>;
 216                 };
 217
 218                 uart0: serial@01c28000 {
 219                         compatible = "snps,dw-apb-uart";
 220                         reg = <0x01c28000 0x400>;
 221                         interrupts = <1>;
 222                         reg-shift = <2>;
 223                         reg-io-width = <4>;
 224                         clocks = <&apb1_gates 16>;
 225                         status = "disabled";
 226                 };
 227
 228                 uart1: serial@01c28400 {
 229                         compatible = "snps,dw-apb-uart";
 230                         reg = <0x01c28400 0x400>;
 231                         interrupts = <2>;
 232                         reg-shift = <2>;
 233                         reg-io-width = <4>;
 234                         clocks = <&apb1_gates 17>;
 235                         status = "disabled";
 236                 };
 237
 238                 uart2: serial@01c28800 {
 239                         compatible = "snps,dw-apb-uart";
 240                         reg = <0x01c28800 0x400>;
 241                         interrupts = <3>;
 242                         reg-shift = <2>;
 243                         reg-io-width = <4>;
 244                         clocks = <&apb1_gates 18>;
 245                         status = "disabled";
 246                 };
 247
 248                 uart3: serial@01c28c00 {
 249                         compatible = "snps,dw-apb-uart";
 250                         reg = <0x01c28c00 0x400>;
 251                         interrupts = <4>;
 252                         reg-shift = <2>;
 253                         reg-io-width = <4>;
 254                         clocks = <&apb1_gates 19>;
 255                         status = "disabled";
 256                 };
 257
 258                 uart4: serial@01c29000 {
 259                         compatible = "snps,dw-apb-uart";
 260                         reg = <0x01c29000 0x400>;
 261                         interrupts = <17>;
 262                         reg-shift = <2>;
 263                         reg-io-width = <4>;
 264                         clocks = <&apb1_gates 20>;
 265                         status = "disabled";
 266                 };
 267
 268                 uart5: serial@01c29400 {
 269                         compatible = "snps,dw-apb-uart";
 270                         reg = <0x01c29400 0x400>;
 271                         interrupts = <18>;
 272                         reg-shift = <2>;
 273                         reg-io-width = <4>;
 274                         clocks = <&apb1_gates 21>;
 275                         status = "disabled";
 276                 };
 277
 278                 uart6: serial@01c29800 {
 279                         compatible = "snps,dw-apb-uart";
 280                         reg = <0x01c29800 0x400>;
 281                         interrupts = <19>;
 282                         reg-shift = <2>;
 283                         reg-io-width = <4>;
 284                         clocks = <&apb1_gates 22>;
 285                         status = "disabled";
 286                 };
 287
 288                 uart7: serial@01c29c00 {
 289                         compatible = "snps,dw-apb-uart";
 290                         reg = <0x01c29c00 0x400>;
 291                         interrupts = <20>;
 292                         reg-shift = <2>;
 293                         reg-io-width = <4>;
 294                         clocks = <&apb1_gates 23>;
 295                         status = "disabled";
 296                 };
 297         };
 298 };