2 * Copyright 2013 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
14 /include/ "skeleton.dtsi"
17 interrupt-parent = <&intc>;
29 compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
30 allwinner,pipeline = "de_be0-lcd0-hdmi";
31 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
39 compatible = "arm,cortex-a8";
44 reg = <0x40000000 0x20000000>;
53 * This is a dummy clock, to be used as placeholder on
54 * other mux clocks when a specific parent clock is not
55 * yet implemented. It should be dropped when the driver
60 compatible = "fixed-clock";
61 clock-frequency = <0>;
64 osc24M: clk@01c20050 {
66 compatible = "allwinner,sun4i-a10-osc-clk";
67 reg = <0x01c20050 0x4>;
68 clock-frequency = <24000000>;
69 clock-output-names = "osc24M";
74 compatible = "fixed-clock";
75 clock-frequency = <32768>;
76 clock-output-names = "osc32k";
81 compatible = "allwinner,sun4i-a10-pll1-clk";
82 reg = <0x01c20000 0x4>;
84 clock-output-names = "pll1";
89 compatible = "allwinner,sun4i-a10-pll1-clk";
90 reg = <0x01c20018 0x4>;
92 clock-output-names = "pll4";
97 compatible = "allwinner,sun4i-a10-pll5-clk";
98 reg = <0x01c20020 0x4>;
100 clock-output-names = "pll5_ddr", "pll5_other";
105 compatible = "allwinner,sun4i-a10-pll6-clk";
106 reg = <0x01c20028 0x4>;
108 clock-output-names = "pll6_sata", "pll6_other", "pll6";
114 compatible = "allwinner,sun4i-a10-cpu-clk";
115 reg = <0x01c20054 0x4>;
116 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
117 clock-output-names = "cpu";
122 compatible = "allwinner,sun4i-a10-axi-clk";
123 reg = <0x01c20054 0x4>;
125 clock-output-names = "axi";
128 axi_gates: clk@01c2005c {
130 compatible = "allwinner,sun4i-a10-axi-gates-clk";
131 reg = <0x01c2005c 0x4>;
133 clock-output-names = "axi_dram";
138 compatible = "allwinner,sun4i-a10-ahb-clk";
139 reg = <0x01c20054 0x4>;
141 clock-output-names = "ahb";
144 ahb_gates: clk@01c20060 {
146 compatible = "allwinner,sun5i-a10s-ahb-gates-clk";
147 reg = <0x01c20060 0x8>;
149 clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci",
150 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
151 "ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram",
152 "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
153 "ahb_spi2", "ahb_gps", "ahb_stimer", "ahb_ve",
154 "ahb_tve", "ahb_lcd", "ahb_csi", "ahb_hdmi",
155 "ahb_de_be", "ahb_de_fe", "ahb_iep", "ahb_mali400";
158 apb0: apb0@01c20054 {
160 compatible = "allwinner,sun4i-a10-apb0-clk";
161 reg = <0x01c20054 0x4>;
163 clock-output-names = "apb0";
166 apb0_gates: clk@01c20068 {
168 compatible = "allwinner,sun5i-a10s-apb0-gates-clk";
169 reg = <0x01c20068 0x4>;
171 clock-output-names = "apb0_codec", "apb0_iis", "apb0_pio",
172 "apb0_ir", "apb0_keypad";
177 compatible = "allwinner,sun4i-a10-apb1-clk";
178 reg = <0x01c20058 0x4>;
179 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
180 clock-output-names = "apb1";
183 apb1_gates: clk@01c2006c {
185 compatible = "allwinner,sun5i-a10s-apb1-gates-clk";
186 reg = <0x01c2006c 0x4>;
188 clock-output-names = "apb1_i2c0", "apb1_i2c1",
189 "apb1_i2c2", "apb1_uart0", "apb1_uart1",
190 "apb1_uart2", "apb1_uart3";
193 nand_clk: clk@01c20080 {
195 compatible = "allwinner,sun4i-a10-mod0-clk";
196 reg = <0x01c20080 0x4>;
197 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
198 clock-output-names = "nand";
201 ms_clk: clk@01c20084 {
203 compatible = "allwinner,sun4i-a10-mod0-clk";
204 reg = <0x01c20084 0x4>;
205 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
206 clock-output-names = "ms";
209 mmc0_clk: clk@01c20088 {
211 compatible = "allwinner,sun4i-a10-mod0-clk";
212 reg = <0x01c20088 0x4>;
213 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
214 clock-output-names = "mmc0";
217 mmc1_clk: clk@01c2008c {
219 compatible = "allwinner,sun4i-a10-mod0-clk";
220 reg = <0x01c2008c 0x4>;
221 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
222 clock-output-names = "mmc1";
225 mmc2_clk: clk@01c20090 {
227 compatible = "allwinner,sun4i-a10-mod0-clk";
228 reg = <0x01c20090 0x4>;
229 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
230 clock-output-names = "mmc2";
233 ts_clk: clk@01c20098 {
235 compatible = "allwinner,sun4i-a10-mod0-clk";
236 reg = <0x01c20098 0x4>;
237 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
238 clock-output-names = "ts";
241 ss_clk: clk@01c2009c {
243 compatible = "allwinner,sun4i-a10-mod0-clk";
244 reg = <0x01c2009c 0x4>;
245 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
246 clock-output-names = "ss";
249 spi0_clk: clk@01c200a0 {
251 compatible = "allwinner,sun4i-a10-mod0-clk";
252 reg = <0x01c200a0 0x4>;
253 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
254 clock-output-names = "spi0";
257 spi1_clk: clk@01c200a4 {
259 compatible = "allwinner,sun4i-a10-mod0-clk";
260 reg = <0x01c200a4 0x4>;
261 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
262 clock-output-names = "spi1";
265 spi2_clk: clk@01c200a8 {
267 compatible = "allwinner,sun4i-a10-mod0-clk";
268 reg = <0x01c200a8 0x4>;
269 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
270 clock-output-names = "spi2";
273 ir0_clk: clk@01c200b0 {
275 compatible = "allwinner,sun4i-a10-mod0-clk";
276 reg = <0x01c200b0 0x4>;
277 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
278 clock-output-names = "ir0";
281 usb_clk: clk@01c200cc {
284 compatible = "allwinner,sun5i-a13-usb-clk";
285 reg = <0x01c200cc 0x4>;
287 clock-output-names = "usb_ohci0", "usb_phy";
290 mbus_clk: clk@01c2015c {
292 compatible = "allwinner,sun5i-a13-mbus-clk";
293 reg = <0x01c2015c 0x4>;
294 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
295 clock-output-names = "mbus";
300 compatible = "simple-bus";
301 #address-cells = <1>;
305 dma: dma-controller@01c02000 {
306 compatible = "allwinner,sun4i-a10-dma";
307 reg = <0x01c02000 0x1000>;
309 clocks = <&ahb_gates 6>;
314 compatible = "allwinner,sun4i-a10-spi";
315 reg = <0x01c05000 0x1000>;
317 clocks = <&ahb_gates 20>, <&spi0_clk>;
318 clock-names = "ahb", "mod";
319 dmas = <&dma 1 27>, <&dma 1 26>;
320 dma-names = "rx", "tx";
322 #address-cells = <1>;
327 compatible = "allwinner,sun4i-a10-spi";
328 reg = <0x01c06000 0x1000>;
330 clocks = <&ahb_gates 21>, <&spi1_clk>;
331 clock-names = "ahb", "mod";
332 dmas = <&dma 1 9>, <&dma 1 8>;
333 dma-names = "rx", "tx";
335 #address-cells = <1>;
339 emac: ethernet@01c0b000 {
340 compatible = "allwinner,sun4i-a10-emac";
341 reg = <0x01c0b000 0x1000>;
343 clocks = <&ahb_gates 17>;
348 compatible = "allwinner,sun4i-a10-mdio";
349 reg = <0x01c0b080 0x14>;
351 #address-cells = <1>;
356 compatible = "allwinner,sun5i-a13-mmc";
357 reg = <0x01c0f000 0x1000>;
358 clocks = <&ahb_gates 8>, <&mmc0_clk>;
359 clock-names = "ahb", "mmc";
365 compatible = "allwinner,sun5i-a13-mmc";
366 reg = <0x01c10000 0x1000>;
367 clocks = <&ahb_gates 9>, <&mmc1_clk>;
368 clock-names = "ahb", "mmc";
374 compatible = "allwinner,sun5i-a13-mmc";
375 reg = <0x01c11000 0x1000>;
376 clocks = <&ahb_gates 10>, <&mmc2_clk>;
377 clock-names = "ahb", "mmc";
382 usbphy: phy@01c13400 {
384 compatible = "allwinner,sun5i-a13-usb-phy";
385 reg = <0x01c13400 0x10 0x01c14800 0x4>;
386 reg-names = "phy_ctrl", "pmu1";
387 clocks = <&usb_clk 8>;
388 clock-names = "usb_phy";
389 resets = <&usb_clk 0>, <&usb_clk 1>;
390 reset-names = "usb0_reset", "usb1_reset";
394 ehci0: usb@01c14000 {
395 compatible = "allwinner,sun5i-a10s-ehci", "generic-ehci";
396 reg = <0x01c14000 0x100>;
398 clocks = <&ahb_gates 1>;
404 ohci0: usb@01c14400 {
405 compatible = "allwinner,sun5i-a10s-ohci", "generic-ohci";
406 reg = <0x01c14400 0x100>;
408 clocks = <&usb_clk 6>, <&ahb_gates 2>;
415 compatible = "allwinner,sun4i-a10-spi";
416 reg = <0x01c17000 0x1000>;
418 clocks = <&ahb_gates 22>, <&spi2_clk>;
419 clock-names = "ahb", "mod";
420 dmas = <&dma 1 29>, <&dma 1 28>;
421 dma-names = "rx", "tx";
423 #address-cells = <1>;
427 intc: interrupt-controller@01c20400 {
428 compatible = "allwinner,sun4i-a10-ic";
429 reg = <0x01c20400 0x400>;
430 interrupt-controller;
431 #interrupt-cells = <1>;
434 pio: pinctrl@01c20800 {
435 compatible = "allwinner,sun5i-a10s-pinctrl";
436 reg = <0x01c20800 0x400>;
438 clocks = <&apb0_gates 5>;
440 interrupt-controller;
441 #interrupt-cells = <2>;
445 uart0_pins_a: uart0@0 {
446 allwinner,pins = "PB19", "PB20";
447 allwinner,function = "uart0";
448 allwinner,drive = <0>;
449 allwinner,pull = <0>;
452 uart2_pins_a: uart2@0 {
453 allwinner,pins = "PC18", "PC19";
454 allwinner,function = "uart2";
455 allwinner,drive = <0>;
456 allwinner,pull = <0>;
459 uart3_pins_a: uart3@0 {
460 allwinner,pins = "PG9", "PG10";
461 allwinner,function = "uart3";
462 allwinner,drive = <0>;
463 allwinner,pull = <0>;
466 emac_pins_a: emac0@0 {
467 allwinner,pins = "PA0", "PA1", "PA2",
468 "PA3", "PA4", "PA5", "PA6",
469 "PA7", "PA8", "PA9", "PA10",
470 "PA11", "PA12", "PA13", "PA14",
472 allwinner,function = "emac";
473 allwinner,drive = <0>;
474 allwinner,pull = <0>;
477 i2c0_pins_a: i2c0@0 {
478 allwinner,pins = "PB0", "PB1";
479 allwinner,function = "i2c0";
480 allwinner,drive = <0>;
481 allwinner,pull = <0>;
484 i2c1_pins_a: i2c1@0 {
485 allwinner,pins = "PB15", "PB16";
486 allwinner,function = "i2c1";
487 allwinner,drive = <0>;
488 allwinner,pull = <0>;
491 i2c2_pins_a: i2c2@0 {
492 allwinner,pins = "PB17", "PB18";
493 allwinner,function = "i2c2";
494 allwinner,drive = <0>;
495 allwinner,pull = <0>;
498 mmc0_pins_a: mmc0@0 {
499 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
500 allwinner,function = "mmc0";
501 allwinner,drive = <2>;
502 allwinner,pull = <0>;
505 mmc1_pins_a: mmc1@0 {
506 allwinner,pins = "PG3","PG4","PG5","PG6","PG7","PG8";
507 allwinner,function = "mmc1";
508 allwinner,drive = <2>;
509 allwinner,pull = <0>;
514 compatible = "allwinner,sun4i-a10-timer";
515 reg = <0x01c20c00 0x90>;
520 wdt: watchdog@01c20c90 {
521 compatible = "allwinner,sun4i-a10-wdt";
522 reg = <0x01c20c90 0x10>;
525 sid: eeprom@01c23800 {
526 compatible = "allwinner,sun4i-a10-sid";
527 reg = <0x01c23800 0x10>;
531 compatible = "allwinner,sun4i-a10-ts";
532 reg = <0x01c25000 0x100>;
536 uart0: serial@01c28000 {
537 compatible = "snps,dw-apb-uart";
538 reg = <0x01c28000 0x400>;
542 clocks = <&apb1_gates 16>;
546 uart1: serial@01c28400 {
547 compatible = "snps,dw-apb-uart";
548 reg = <0x01c28400 0x400>;
552 clocks = <&apb1_gates 17>;
556 uart2: serial@01c28800 {
557 compatible = "snps,dw-apb-uart";
558 reg = <0x01c28800 0x400>;
562 clocks = <&apb1_gates 18>;
566 uart3: serial@01c28c00 {
567 compatible = "snps,dw-apb-uart";
568 reg = <0x01c28c00 0x400>;
572 clocks = <&apb1_gates 19>;
577 #address-cells = <1>;
579 compatible = "allwinner,sun5i-a10s-i2c", "allwinner,sun4i-a10-i2c";
580 reg = <0x01c2ac00 0x400>;
582 clocks = <&apb1_gates 0>;
587 #address-cells = <1>;
589 compatible = "allwinner,sun5i-a10s-i2c", "allwinner,sun4i-a10-i2c";
590 reg = <0x01c2b000 0x400>;
592 clocks = <&apb1_gates 1>;
597 #address-cells = <1>;
599 compatible = "allwinner,sun5i-a10s-i2c", "allwinner,sun4i-a10-i2c";
600 reg = <0x01c2b400 0x400>;
602 clocks = <&apb1_gates 2>;
607 compatible = "allwinner,sun5i-a13-hstimer";
608 reg = <0x01c60000 0x1000>;
609 interrupts = <82>, <83>;
610 clocks = <&ahb_gates 28>;