arch/arm/boot/dts/sun5i.dtsi

   1 /*
   2  * Copyright 2012-2015 Maxime Ripard
   3  *
   4  * Maxime Ripard <maxime.ripard@free-electrons.com>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This library is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This library is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 #include "skeleton.dtsi"
  46
  47 #include <dt-bindings/clock/sun5i-ccu.h>
  48 #include <dt-bindings/dma/sun4i-a10.h>
  49 #include <dt-bindings/pinctrl/sun4i-a10.h>
  50 #include <dt-bindings/reset/sun5i-ccu.h>
  51
  52 / {
  53         interrupt-parent = <&intc>;
  54
  55         cpus {
  56                 #address-cells = <1>;
  57                 #size-cells = <0>;
  58
  59                 cpu0: cpu@0 {
  60                         device_type = "cpu";
  61                         compatible = "arm,cortex-a8";
  62                         reg = <0x0>;
  63                         clocks = <&ccu CLK_CPU>;
  64                 };
  65         };
  66
  67         clocks {
  68                 #address-cells = <1>;
  69                 #size-cells = <1>;
  70                 ranges;
  71
  72                 osc24M: clk@01c20050 {
  73                         #clock-cells = <0>;
  74                         compatible = "fixed-clock";
  75                         clock-frequency = <24000000>;
  76                         clock-output-names = "osc24M";
  77                 };
  78
  79                 osc32k: clk@0 {
  80                         #clock-cells = <0>;
  81                         compatible = "fixed-clock";
  82                         clock-frequency = <32768>;
  83                         clock-output-names = "osc32k";
  84                 };
  85         };
  86
  87         soc@01c00000 {
  88                 compatible = "simple-bus";
  89                 #address-cells = <1>;
  90                 #size-cells = <1>;
  91                 ranges;
  92
  93                 sram-controller@01c00000 {
  94                         compatible = "allwinner,sun4i-a10-sram-controller";
  95                         reg = <0x01c00000 0x30>;
  96                         #address-cells = <1>;
  97                         #size-cells = <1>;
  98                         ranges;
  99
 100                         sram_a: sram@00000000 {
 101                                 compatible = "mmio-sram";
 102                                 reg = <0x00000000 0xc000>;
 103                                 #address-cells = <1>;
 104                                 #size-cells = <1>;
 105                                 ranges = <0 0x00000000 0xc000>;
 106                         };
 107
 108                         sram_d: sram@00010000 {
 109                                 compatible = "mmio-sram";
 110                                 reg = <0x00010000 0x1000>;
 111                                 #address-cells = <1>;
 112                                 #size-cells = <1>;
 113                                 ranges = <0 0x00010000 0x1000>;
 114
 115                                 otg_sram: sram-section@0000 {
 116                                         compatible = "allwinner,sun4i-a10-sram-d";
 117                                         reg = <0x0000 0x1000>;
 118                                         status = "disabled";
 119                                 };
 120                         };
 121                 };
 122
 123                 dma: dma-controller@01c02000 {
 124                         compatible = "allwinner,sun4i-a10-dma";
 125                         reg = <0x01c02000 0x1000>;
 126                         interrupts = <27>;
 127                         clocks = <&ccu CLK_AHB_DMA>;
 128                         #dma-cells = <2>;
 129                 };
 130
 131                 spi0: spi@01c05000 {
 132                         compatible = "allwinner,sun4i-a10-spi";
 133                         reg = <0x01c05000 0x1000>;
 134                         interrupts = <10>;
 135                         clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
 136                         clock-names = "ahb", "mod";
 137                         dmas = <&dma SUN4I_DMA_DEDICATED 27>,
 138                                <&dma SUN4I_DMA_DEDICATED 26>;
 139                         dma-names = "rx", "tx";
 140                         status = "disabled";
 141                         #address-cells = <1>;
 142                         #size-cells = <0>;
 143                 };
 144
 145                 spi1: spi@01c06000 {
 146                         compatible = "allwinner,sun4i-a10-spi";
 147                         reg = <0x01c06000 0x1000>;
 148                         interrupts = <11>;
 149                         clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
 150                         clock-names = "ahb", "mod";
 151                         dmas = <&dma SUN4I_DMA_DEDICATED 9>,
 152                                <&dma SUN4I_DMA_DEDICATED 8>;
 153                         dma-names = "rx", "tx";
 154                         status = "disabled";
 155                         #address-cells = <1>;
 156                         #size-cells = <0>;
 157                 };
 158
 159                 mmc0: mmc@01c0f000 {
 160                         compatible = "allwinner,sun5i-a13-mmc";
 161                         reg = <0x01c0f000 0x1000>;
 162                         clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>;
 163                         clock-names = "ahb", "mmc";
 164                         interrupts = <32>;
 165                         status = "disabled";
 166                         #address-cells = <1>;
 167                         #size-cells = <0>;
 168                 };
 169
 170                 mmc1: mmc@01c10000 {
 171                         compatible = "allwinner,sun5i-a13-mmc";
 172                         reg = <0x01c10000 0x1000>;
 173                         clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>;
 174                         clock-names = "ahb", "mmc";
 175                         interrupts = <33>;
 176                         status = "disabled";
 177                         #address-cells = <1>;
 178                         #size-cells = <0>;
 179                 };
 180
 181                 mmc2: mmc@01c11000 {
 182                         compatible = "allwinner,sun5i-a13-mmc";
 183                         reg = <0x01c11000 0x1000>;
 184                         clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>;
 185                         clock-names = "ahb", "mmc";
 186                         interrupts = <34>;
 187                         status = "disabled";
 188                         #address-cells = <1>;
 189                         #size-cells = <0>;
 190                 };
 191
 192                 usb_otg: usb@01c13000 {
 193                         compatible = "allwinner,sun4i-a10-musb";
 194                         reg = <0x01c13000 0x0400>;
 195                         clocks = <&ccu CLK_AHB_OTG>;
 196                         interrupts = <38>;
 197                         interrupt-names = "mc";
 198                         phys = <&usbphy 0>;
 199                         phy-names = "usb";
 200                         extcon = <&usbphy 0>;
 201                         allwinner,sram = <&otg_sram 1>;
 202                         status = "disabled";
 203                 };
 204
 205                 usbphy: phy@01c13400 {
 206                         #phy-cells = <1>;
 207                         compatible = "allwinner,sun5i-a13-usb-phy";
 208                         reg = <0x01c13400 0x10 0x01c14800 0x4>;
 209                         reg-names = "phy_ctrl", "pmu1";
 210                         clocks = <&ccu CLK_USB_PHY0>;
 211                         clock-names = "usb_phy";
 212                         resets = <&ccu RST_USB_PHY0>, <&ccu RST_USB_PHY1>;
 213                         reset-names = "usb0_reset", "usb1_reset";
 214                         status = "disabled";
 215                 };
 216
 217                 ehci0: usb@01c14000 {
 218                         compatible = "allwinner,sun5i-a13-ehci", "generic-ehci";
 219                         reg = <0x01c14000 0x100>;
 220                         interrupts = <39>;
 221                         clocks = <&ccu CLK_AHB_EHCI>;
 222                         phys = <&usbphy 1>;
 223                         phy-names = "usb";
 224                         status = "disabled";
 225                 };
 226
 227                 ohci0: usb@01c14400 {
 228                         compatible = "allwinner,sun5i-a13-ohci", "generic-ohci";
 229                         reg = <0x01c14400 0x100>;
 230                         interrupts = <40>;
 231                         clocks = <&ccu CLK_USB_OHCI>, <&ccu CLK_AHB_OHCI>;
 232                         phys = <&usbphy 1>;
 233                         phy-names = "usb";
 234                         status = "disabled";
 235                 };
 236
 237                 spi2: spi@01c17000 {
 238                         compatible = "allwinner,sun4i-a10-spi";
 239                         reg = <0x01c17000 0x1000>;
 240                         interrupts = <12>;
 241                         clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
 242                         clock-names = "ahb", "mod";
 243                         dmas = <&dma SUN4I_DMA_DEDICATED 29>,
 244                                <&dma SUN4I_DMA_DEDICATED 28>;
 245                         dma-names = "rx", "tx";
 246                         status = "disabled";
 247                         #address-cells = <1>;
 248                         #size-cells = <0>;
 249                 };
 250
 251                 ccu: clock@01c20000 {
 252                         reg = <0x01c20000 0x400>;
 253                         clocks = <&osc24M>, <&osc32k>;
 254                         clock-names = "hosc", "losc";
 255                         #clock-cells = <1>;
 256                         #reset-cells = <1>;
 257                 };
 258
 259                 intc: interrupt-controller@01c20400 {
 260                         compatible = "allwinner,sun4i-a10-ic";
 261                         reg = <0x01c20400 0x400>;
 262                         interrupt-controller;
 263                         #interrupt-cells = <1>;
 264                 };
 265
 266                 pio: pinctrl@01c20800 {
 267                         reg = <0x01c20800 0x400>;
 268                         interrupts = <28>;
 269                         clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
 270                         clock-names = "apb", "hosc", "losc";
 271                         gpio-controller;
 272                         interrupt-controller;
 273                         #interrupt-cells = <3>;
 274                         #gpio-cells = <3>;
 275
 276                         i2c0_pins_a: i2c0@0 {
 277                                 pins = "PB0", "PB1";
 278                                 function = "i2c0";
 279                         };
 280
 281                         i2c1_pins_a: i2c1@0 {
 282                                 pins = "PB15", "PB16";
 283                                 function = "i2c1";
 284                         };
 285
 286                         i2c2_pins_a: i2c2@0 {
 287                                 pins = "PB17", "PB18";
 288                                 function = "i2c2";
 289                         };
 290
 291                         lcd_rgb565_pins: lcd_rgb565@0 {
 292                                 pins = "PD3", "PD4", "PD5", "PD6", "PD7",
 293                                                  "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
 294                                                  "PD19", "PD20", "PD21", "PD22", "PD23",
 295                                                  "PD24", "PD25", "PD26", "PD27";
 296                                 function = "lcd0";
 297                         };
 298
 299                         mmc0_pins_a: mmc0@0 {
 300                                 pins = "PF0", "PF1", "PF2", "PF3",
 301                                        "PF4", "PF5";
 302                                 function = "mmc0";
 303                                 drive-strength = <30>;
 304                                 bias-pull-up;
 305                         };
 306
 307                         mmc2_pins_a: mmc2@0 {
 308                                 pins = "PC6", "PC7", "PC8", "PC9",
 309                                        "PC10", "PC11", "PC12", "PC13",
 310                                        "PC14", "PC15";
 311                                 function = "mmc2";
 312                                 drive-strength = <30>;
 313                                 bias-pull-up;
 314                         };
 315
 316                         mmc2_4bit_pins_a: mmc2-4bit@0 {
 317                                 pins = "PC6", "PC7", "PC8", "PC9",
 318                                        "PC10", "PC11";
 319                                 function = "mmc2";
 320                                 drive-strength = <30>;
 321                                 bias-pull-up;
 322                         };
 323
 324                         spi2_pins_a: spi2@0 {
 325                                 pins = "PE1", "PE2", "PE3";
 326                                 function = "spi2";
 327                         };
 328
 329                         spi2_cs0_pins_a: spi2-cs0@0 {
 330                                 pins = "PE0";
 331                                 function = "spi2";
 332                         };
 333
 334                         uart3_pins_a: uart3@0 {
 335                                 pins = "PG9", "PG10";
 336                                 function = "uart3";
 337                         };
 338
 339                         uart3_pins_cts_rts_a: uart3-cts-rts@0 {
 340                                 pins = "PG11", "PG12";
 341                                 function = "uart3";
 342                         };
 343
 344                         pwm0_pins: pwm0 {
 345                                 pins = "PB2";
 346                                 function = "pwm";
 347                         };
 348                 };
 349
 350                 timer@01c20c00 {
 351                         compatible = "allwinner,sun4i-a10-timer";
 352                         reg = <0x01c20c00 0x90>;
 353                         interrupts = <22>;
 354                         clocks = <&ccu CLK_HOSC>;
 355                 };
 356
 357                 wdt: watchdog@01c20c90 {
 358                         compatible = "allwinner,sun4i-a10-wdt";
 359                         reg = <0x01c20c90 0x10>;
 360                 };
 361
 362                 lradc: lradc@01c22800 {
 363                         compatible = "allwinner,sun4i-a10-lradc-keys";
 364                         reg = <0x01c22800 0x100>;
 365                         interrupts = <31>;
 366                         status = "disabled";
 367                 };
 368
 369                 codec: codec@01c22c00 {
 370                         #sound-dai-cells = <0>;
 371                         compatible = "allwinner,sun4i-a10-codec";
 372                         reg = <0x01c22c00 0x40>;
 373                         interrupts = <30>;
 374                         clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;
 375                         clock-names = "apb", "codec";
 376                         dmas = <&dma SUN4I_DMA_NORMAL 19>,
 377                                <&dma SUN4I_DMA_NORMAL 19>;
 378                         dma-names = "rx", "tx";
 379                         status = "disabled";
 380                 };
 381
 382                 sid: eeprom@01c23800 {
 383                         compatible = "allwinner,sun4i-a10-sid";
 384                         reg = <0x01c23800 0x10>;
 385                 };
 386
 387                 rtp: rtp@01c25000 {
 388                         compatible = "allwinner,sun5i-a13-ts";
 389                         reg = <0x01c25000 0x100>;
 390                         interrupts = <29>;
 391                         #thermal-sensor-cells = <0>;
 392                 };
 393
 394                 uart1: serial@01c28400 {
 395                         compatible = "snps,dw-apb-uart";
 396                         reg = <0x01c28400 0x400>;
 397                         interrupts = <2>;
 398                         reg-shift = <2>;
 399                         reg-io-width = <4>;
 400                         clocks = <&ccu CLK_APB1_UART1>;
 401                         status = "disabled";
 402                 };
 403
 404                 uart3: serial@01c28c00 {
 405                         compatible = "snps,dw-apb-uart";
 406                         reg = <0x01c28c00 0x400>;
 407                         interrupts = <4>;
 408                         reg-shift = <2>;
 409                         reg-io-width = <4>;
 410                         clocks = <&ccu CLK_APB1_UART3>;
 411                         status = "disabled";
 412                 };
 413
 414                 i2c0: i2c@01c2ac00 {
 415                         compatible = "allwinner,sun4i-a10-i2c";
 416                         reg = <0x01c2ac00 0x400>;
 417                         interrupts = <7>;
 418                         clocks = <&ccu CLK_APB1_I2C0>;
 419                         status = "disabled";
 420                         #address-cells = <1>;
 421                         #size-cells = <0>;
 422                 };
 423
 424                 i2c1: i2c@01c2b000 {
 425                         compatible = "allwinner,sun4i-a10-i2c";
 426                         reg = <0x01c2b000 0x400>;
 427                         interrupts = <8>;
 428                         clocks = <&ccu CLK_APB1_I2C1>;
 429                         status = "disabled";
 430                         #address-cells = <1>;
 431                         #size-cells = <0>;
 432                 };
 433
 434                 i2c2: i2c@01c2b400 {
 435                         compatible = "allwinner,sun4i-a10-i2c";
 436                         reg = <0x01c2b400 0x400>;
 437                         interrupts = <9>;
 438                         clocks = <&ccu CLK_APB1_I2C2>;
 439                         status = "disabled";
 440                         #address-cells = <1>;
 441                         #size-cells = <0>;
 442                 };
 443
 444                 timer@01c60000 {
 445                         compatible = "allwinner,sun5i-a13-hstimer";
 446                         reg = <0x01c60000 0x1000>;
 447                         interrupts = <82>, <83>;
 448                         clocks = <&ccu CLK_AHB_HSTIMER>;
 449                 };
 450         };
 451 };