arch/arm/boot/dts/sun5i.dtsi

   1 /*
   2  * Copyright 2012-2015 Maxime Ripard
   3  *
   4  * Maxime Ripard <maxime.ripard@free-electrons.com>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This library is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This library is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 #include "skeleton.dtsi"
  46
  47 #include <dt-bindings/clock/sun4i-a10-pll2.h>
  48 #include <dt-bindings/dma/sun4i-a10.h>
  49 #include <dt-bindings/pinctrl/sun4i-a10.h>
  50
  51 / {
  52         interrupt-parent = <&intc>;
  53
  54         cpus {
  55                 #address-cells = <1>;
  56                 #size-cells = <0>;
  57
  58                 cpu0: cpu@0 {
  59                         device_type = "cpu";
  60                         compatible = "arm,cortex-a8";
  61                         reg = <0x0>;
  62                         clocks = <&cpu>;
  63                 };
  64         };
  65
  66         clocks {
  67                 #address-cells = <1>;
  68                 #size-cells = <1>;
  69                 ranges;
  70
  71                 /*
  72                  * This is a dummy clock, to be used as placeholder on
  73                  * other mux clocks when a specific parent clock is not
  74                  * yet implemented. It should be dropped when the driver
  75                  * is complete.
  76                  */
  77                 dummy: dummy {
  78                         #clock-cells = <0>;
  79                         compatible = "fixed-clock";
  80                         clock-frequency = <0>;
  81                 };
  82
  83                 osc24M: clk@01c20050 {
  84                         #clock-cells = <0>;
  85                         compatible = "allwinner,sun4i-a10-osc-clk";
  86                         reg = <0x01c20050 0x4>;
  87                         clock-frequency = <24000000>;
  88                         clock-output-names = "osc24M";
  89                 };
  90
  91                 osc3M: osc3M_clk {
  92                         compatible = "fixed-factor-clock";
  93                         #clock-cells = <0>;
  94                         clock-div = <8>;
  95                         clock-mult = <1>;
  96                         clocks = <&osc24M>;
  97                         clock-output-names = "osc3M";
  98                 };
  99
 100                 osc32k: clk@0 {
 101                         #clock-cells = <0>;
 102                         compatible = "fixed-clock";
 103                         clock-frequency = <32768>;
 104                         clock-output-names = "osc32k";
 105                 };
 106
 107                 pll1: clk@01c20000 {
 108                         #clock-cells = <0>;
 109                         compatible = "allwinner,sun4i-a10-pll1-clk";
 110                         reg = <0x01c20000 0x4>;
 111                         clocks = <&osc24M>;
 112                         clock-output-names = "pll1";
 113                 };
 114
 115                 pll2: clk@01c20008 {
 116                         #clock-cells = <1>;
 117                         compatible = "allwinner,sun5i-a13-pll2-clk";
 118                         reg = <0x01c20008 0x8>;
 119                         clocks = <&osc24M>;
 120                         clock-output-names = "pll2-1x", "pll2-2x",
 121                                              "pll2-4x", "pll2-8x";
 122                 };
 123
 124                 pll3: clk@01c20010 {
 125                         #clock-cells = <0>;
 126                         compatible = "allwinner,sun4i-a10-pll3-clk";
 127                         reg = <0x01c20010 0x4>;
 128                         clocks = <&osc3M>;
 129                         clock-output-names = "pll3";
 130                 };
 131
 132                 pll3x2: pll3x2_clk {
 133                         compatible = "allwinner,sun4i-a10-pll3-2x-clk", "fixed-factor-clock";
 134                         #clock-cells = <0>;
 135                         clock-div = <1>;
 136                         clock-mult = <2>;
 137                         clocks = <&pll3>;
 138                         clock-output-names = "pll3-2x";
 139                 };
 140
 141                 pll4: clk@01c20018 {
 142                         #clock-cells = <0>;
 143                         compatible = "allwinner,sun4i-a10-pll1-clk";
 144                         reg = <0x01c20018 0x4>;
 145                         clocks = <&osc24M>;
 146                         clock-output-names = "pll4";
 147                 };
 148
 149                 pll5: clk@01c20020 {
 150                         #clock-cells = <1>;
 151                         compatible = "allwinner,sun4i-a10-pll5-clk";
 152                         reg = <0x01c20020 0x4>;
 153                         clocks = <&osc24M>;
 154                         clock-output-names = "pll5_ddr", "pll5_other";
 155                 };
 156
 157                 pll6: clk@01c20028 {
 158                         #clock-cells = <1>;
 159                         compatible = "allwinner,sun4i-a10-pll6-clk";
 160                         reg = <0x01c20028 0x4>;
 161                         clocks = <&osc24M>;
 162                         clock-output-names = "pll6_sata", "pll6_other", "pll6";
 163                 };
 164
 165                 pll7: clk@01c20030 {
 166                         #clock-cells = <0>;
 167                         compatible = "allwinner,sun4i-a10-pll3-clk";
 168                         reg = <0x01c20030 0x4>;
 169                         clocks = <&osc3M>;
 170                         clock-output-names = "pll7";
 171                 };
 172
 173                 pll7x2: pll7x2_clk {
 174                         compatible = "fixed-factor-clock";
 175                         #clock-cells = <0>;
 176                         clock-div = <1>;
 177                         clock-mult = <2>;
 178                         clocks = <&pll7>;
 179                         clock-output-names = "pll7-2x";
 180                 };
 181
 182                 /* dummy is 200M */
 183                 cpu: cpu@01c20054 {
 184                         #clock-cells = <0>;
 185                         compatible = "allwinner,sun4i-a10-cpu-clk";
 186                         reg = <0x01c20054 0x4>;
 187                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
 188                         clock-output-names = "cpu";
 189                 };
 190
 191                 axi: axi@01c20054 {
 192                         #clock-cells = <0>;
 193                         compatible = "allwinner,sun4i-a10-axi-clk";
 194                         reg = <0x01c20054 0x4>;
 195                         clocks = <&cpu>;
 196                         clock-output-names = "axi";
 197                 };
 198
 199                 ahb: ahb@01c20054 {
 200                         #clock-cells = <0>;
 201                         compatible = "allwinner,sun5i-a13-ahb-clk";
 202                         reg = <0x01c20054 0x4>;
 203                         clocks = <&axi>, <&cpu>, <&pll6 1>;
 204                         clock-output-names = "ahb";
 205                         /*
 206                          * Use PLL6 as parent, instead of CPU/AXI
 207                          * which has rate changes due to cpufreq
 208                          */
 209                         assigned-clocks = <&ahb>;
 210                         assigned-clock-parents = <&pll6 1>;
 211                 };
 212
 213                 apb0: apb0@01c20054 {
 214                         #clock-cells = <0>;
 215                         compatible = "allwinner,sun4i-a10-apb0-clk";
 216                         reg = <0x01c20054 0x4>;
 217                         clocks = <&ahb>;
 218                         clock-output-names = "apb0";
 219                 };
 220
 221                 apb1: clk@01c20058 {
 222                         #clock-cells = <0>;
 223                         compatible = "allwinner,sun4i-a10-apb1-clk";
 224                         reg = <0x01c20058 0x4>;
 225                         clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
 226                         clock-output-names = "apb1";
 227                 };
 228
 229                 axi_gates: clk@01c2005c {
 230                         #clock-cells = <1>;
 231                         compatible = "allwinner,sun4i-a10-axi-gates-clk";
 232                         reg = <0x01c2005c 0x4>;
 233                         clocks = <&axi>;
 234                         clock-indices = <0>;
 235                         clock-output-names = "axi_dram";
 236                 };
 237
 238                 nand_clk: clk@01c20080 {
 239                         #clock-cells = <0>;
 240                         compatible = "allwinner,sun4i-a10-mod0-clk";
 241                         reg = <0x01c20080 0x4>;
 242                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 243                         clock-output-names = "nand";
 244                 };
 245
 246                 ms_clk: clk@01c20084 {
 247                         #clock-cells = <0>;
 248                         compatible = "allwinner,sun4i-a10-mod0-clk";
 249                         reg = <0x01c20084 0x4>;
 250                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 251                         clock-output-names = "ms";
 252                 };
 253
 254                 mmc0_clk: clk@01c20088 {
 255                         #clock-cells = <1>;
 256                         compatible = "allwinner,sun4i-a10-mmc-clk";
 257                         reg = <0x01c20088 0x4>;
 258                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 259                         clock-output-names = "mmc0",
 260                                              "mmc0_output",
 261                                              "mmc0_sample";
 262                 };
 263
 264                 mmc1_clk: clk@01c2008c {
 265                         #clock-cells = <1>;
 266                         compatible = "allwinner,sun4i-a10-mmc-clk";
 267                         reg = <0x01c2008c 0x4>;
 268                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 269                         clock-output-names = "mmc1",
 270                                              "mmc1_output",
 271                                              "mmc1_sample";
 272                 };
 273
 274                 mmc2_clk: clk@01c20090 {
 275                         #clock-cells = <1>;
 276                         compatible = "allwinner,sun4i-a10-mmc-clk";
 277                         reg = <0x01c20090 0x4>;
 278                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 279                         clock-output-names = "mmc2",
 280                                              "mmc2_output",
 281                                              "mmc2_sample";
 282                 };
 283
 284                 ts_clk: clk@01c20098 {
 285                         #clock-cells = <0>;
 286                         compatible = "allwinner,sun4i-a10-mod0-clk";
 287                         reg = <0x01c20098 0x4>;
 288                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 289                         clock-output-names = "ts";
 290                 };
 291
 292                 ss_clk: clk@01c2009c {
 293                         #clock-cells = <0>;
 294                         compatible = "allwinner,sun4i-a10-mod0-clk";
 295                         reg = <0x01c2009c 0x4>;
 296                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 297                         clock-output-names = "ss";
 298                 };
 299
 300                 spi0_clk: clk@01c200a0 {
 301                         #clock-cells = <0>;
 302                         compatible = "allwinner,sun4i-a10-mod0-clk";
 303                         reg = <0x01c200a0 0x4>;
 304                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 305                         clock-output-names = "spi0";
 306                 };
 307
 308                 spi1_clk: clk@01c200a4 {
 309                         #clock-cells = <0>;
 310                         compatible = "allwinner,sun4i-a10-mod0-clk";
 311                         reg = <0x01c200a4 0x4>;
 312                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 313                         clock-output-names = "spi1";
 314                 };
 315
 316                 spi2_clk: clk@01c200a8 {
 317                         #clock-cells = <0>;
 318                         compatible = "allwinner,sun4i-a10-mod0-clk";
 319                         reg = <0x01c200a8 0x4>;
 320                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 321                         clock-output-names = "spi2";
 322                 };
 323
 324                 ir0_clk: clk@01c200b0 {
 325                         #clock-cells = <0>;
 326                         compatible = "allwinner,sun4i-a10-mod0-clk";
 327                         reg = <0x01c200b0 0x4>;
 328                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 329                         clock-output-names = "ir0";
 330                 };
 331
 332                 usb_clk: clk@01c200cc {
 333                         #clock-cells = <1>;
 334                         #reset-cells = <1>;
 335                         compatible = "allwinner,sun5i-a13-usb-clk";
 336                         reg = <0x01c200cc 0x4>;
 337                         clocks = <&pll6 1>;
 338                         clock-output-names = "usb_ohci0", "usb_phy";
 339                 };
 340
 341                 codec_clk: clk@01c20140 {
 342                         #clock-cells = <0>;
 343                         compatible = "allwinner,sun4i-a10-codec-clk";
 344                         reg = <0x01c20140 0x4>;
 345                         clocks = <&pll2 SUN4I_A10_PLL2_1X>;
 346                         clock-output-names = "codec";
 347                 };
 348
 349                 mbus_clk: clk@01c2015c {
 350                         #clock-cells = <0>;
 351                         compatible = "allwinner,sun5i-a13-mbus-clk";
 352                         reg = <0x01c2015c 0x4>;
 353                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 354                         clock-output-names = "mbus";
 355                 };
 356         };
 357
 358         soc@01c00000 {
 359                 compatible = "simple-bus";
 360                 #address-cells = <1>;
 361                 #size-cells = <1>;
 362                 ranges;
 363
 364                 sram-controller@01c00000 {
 365                         compatible = "allwinner,sun4i-a10-sram-controller";
 366                         reg = <0x01c00000 0x30>;
 367                         #address-cells = <1>;
 368                         #size-cells = <1>;
 369                         ranges;
 370
 371                         sram_a: sram@00000000 {
 372                                 compatible = "mmio-sram";
 373                                 reg = <0x00000000 0xc000>;
 374                                 #address-cells = <1>;
 375                                 #size-cells = <1>;
 376                                 ranges = <0 0x00000000 0xc000>;
 377                         };
 378
 379                         sram_d: sram@00010000 {
 380                                 compatible = "mmio-sram";
 381                                 reg = <0x00010000 0x1000>;
 382                                 #address-cells = <1>;
 383                                 #size-cells = <1>;
 384                                 ranges = <0 0x00010000 0x1000>;
 385
 386                                 otg_sram: sram-section@0000 {
 387                                         compatible = "allwinner,sun4i-a10-sram-d";
 388                                         reg = <0x0000 0x1000>;
 389                                         status = "disabled";
 390                                 };
 391                         };
 392                 };
 393
 394                 dma: dma-controller@01c02000 {
 395                         compatible = "allwinner,sun4i-a10-dma";
 396                         reg = <0x01c02000 0x1000>;
 397                         interrupts = <27>;
 398                         clocks = <&ahb_gates 6>;
 399                         #dma-cells = <2>;
 400                 };
 401
 402                 spi0: spi@01c05000 {
 403                         compatible = "allwinner,sun4i-a10-spi";
 404                         reg = <0x01c05000 0x1000>;
 405                         interrupts = <10>;
 406                         clocks = <&ahb_gates 20>, <&spi0_clk>;
 407                         clock-names = "ahb", "mod";
 408                         dmas = <&dma SUN4I_DMA_DEDICATED 27>,
 409                                <&dma SUN4I_DMA_DEDICATED 26>;
 410                         dma-names = "rx", "tx";
 411                         status = "disabled";
 412                         #address-cells = <1>;
 413                         #size-cells = <0>;
 414                 };
 415
 416                 spi1: spi@01c06000 {
 417                         compatible = "allwinner,sun4i-a10-spi";
 418                         reg = <0x01c06000 0x1000>;
 419                         interrupts = <11>;
 420                         clocks = <&ahb_gates 21>, <&spi1_clk>;
 421                         clock-names = "ahb", "mod";
 422                         dmas = <&dma SUN4I_DMA_DEDICATED 9>,
 423                                <&dma SUN4I_DMA_DEDICATED 8>;
 424                         dma-names = "rx", "tx";
 425                         status = "disabled";
 426                         #address-cells = <1>;
 427                         #size-cells = <0>;
 428                 };
 429
 430                 mmc0: mmc@01c0f000 {
 431                         compatible = "allwinner,sun5i-a13-mmc";
 432                         reg = <0x01c0f000 0x1000>;
 433                         clocks = <&ahb_gates 8>,
 434                                  <&mmc0_clk 0>,
 435                                  <&mmc0_clk 1>,
 436                                  <&mmc0_clk 2>;
 437                         clock-names = "ahb",
 438                                       "mmc",
 439                                       "output",
 440                                       "sample";
 441                         interrupts = <32>;
 442                         status = "disabled";
 443                         #address-cells = <1>;
 444                         #size-cells = <0>;
 445                 };
 446
 447                 mmc1: mmc@01c10000 {
 448                         compatible = "allwinner,sun5i-a13-mmc";
 449                         reg = <0x01c10000 0x1000>;
 450                         clocks = <&ahb_gates 9>,
 451                                  <&mmc1_clk 0>,
 452                                  <&mmc1_clk 1>,
 453                                  <&mmc1_clk 2>;
 454                         clock-names = "ahb",
 455                                       "mmc",
 456                                       "output",
 457                                       "sample";
 458                         interrupts = <33>;
 459                         status = "disabled";
 460                         #address-cells = <1>;
 461                         #size-cells = <0>;
 462                 };
 463
 464                 mmc2: mmc@01c11000 {
 465                         compatible = "allwinner,sun5i-a13-mmc";
 466                         reg = <0x01c11000 0x1000>;
 467                         clocks = <&ahb_gates 10>,
 468                                  <&mmc2_clk 0>,
 469                                  <&mmc2_clk 1>,
 470                                  <&mmc2_clk 2>;
 471                         clock-names = "ahb",
 472                                       "mmc",
 473                                       "output",
 474                                       "sample";
 475                         interrupts = <34>;
 476                         status = "disabled";
 477                         #address-cells = <1>;
 478                         #size-cells = <0>;
 479                 };
 480
 481                 usb_otg: usb@01c13000 {
 482                         compatible = "allwinner,sun4i-a10-musb";
 483                         reg = <0x01c13000 0x0400>;
 484                         clocks = <&ahb_gates 0>;
 485                         interrupts = <38>;
 486                         interrupt-names = "mc";
 487                         phys = <&usbphy 0>;
 488                         phy-names = "usb";
 489                         extcon = <&usbphy 0>;
 490                         allwinner,sram = <&otg_sram 1>;
 491                         status = "disabled";
 492                 };
 493
 494                 usbphy: phy@01c13400 {
 495                         #phy-cells = <1>;
 496                         compatible = "allwinner,sun5i-a13-usb-phy";
 497                         reg = <0x01c13400 0x10 0x01c14800 0x4>;
 498                         reg-names = "phy_ctrl", "pmu1";
 499                         clocks = <&usb_clk 8>;
 500                         clock-names = "usb_phy";
 501                         resets = <&usb_clk 0>, <&usb_clk 1>;
 502                         reset-names = "usb0_reset", "usb1_reset";
 503                         status = "disabled";
 504                 };
 505
 506                 ehci0: usb@01c14000 {
 507                         compatible = "allwinner,sun5i-a13-ehci", "generic-ehci";
 508                         reg = <0x01c14000 0x100>;
 509                         interrupts = <39>;
 510                         clocks = <&ahb_gates 1>;
 511                         phys = <&usbphy 1>;
 512                         phy-names = "usb";
 513                         status = "disabled";
 514                 };
 515
 516                 ohci0: usb@01c14400 {
 517                         compatible = "allwinner,sun5i-a13-ohci", "generic-ohci";
 518                         reg = <0x01c14400 0x100>;
 519                         interrupts = <40>;
 520                         clocks = <&usb_clk 6>, <&ahb_gates 2>;
 521                         phys = <&usbphy 1>;
 522                         phy-names = "usb";
 523                         status = "disabled";
 524                 };
 525
 526                 spi2: spi@01c17000 {
 527                         compatible = "allwinner,sun4i-a10-spi";
 528                         reg = <0x01c17000 0x1000>;
 529                         interrupts = <12>;
 530                         clocks = <&ahb_gates 22>, <&spi2_clk>;
 531                         clock-names = "ahb", "mod";
 532                         dmas = <&dma SUN4I_DMA_DEDICATED 29>,
 533                                <&dma SUN4I_DMA_DEDICATED 28>;
 534                         dma-names = "rx", "tx";
 535                         status = "disabled";
 536                         #address-cells = <1>;
 537                         #size-cells = <0>;
 538                 };
 539
 540                 intc: interrupt-controller@01c20400 {
 541                         compatible = "allwinner,sun4i-a10-ic";
 542                         reg = <0x01c20400 0x400>;
 543                         interrupt-controller;
 544                         #interrupt-cells = <1>;
 545                 };
 546
 547                 pio: pinctrl@01c20800 {
 548                         reg = <0x01c20800 0x400>;
 549                         interrupts = <28>;
 550                         clocks = <&apb0_gates 5>, <&osc24M>, <&osc32k>;
 551                         clock-names = "apb", "hosc", "losc";
 552                         gpio-controller;
 553                         interrupt-controller;
 554                         #interrupt-cells = <3>;
 555                         #gpio-cells = <3>;
 556
 557                         i2c0_pins_a: i2c0@0 {
 558                                 allwinner,pins = "PB0", "PB1";
 559                                 allwinner,function = "i2c0";
 560                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 561                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 562                         };
 563
 564                         i2c1_pins_a: i2c1@0 {
 565                                 allwinner,pins = "PB15", "PB16";
 566                                 allwinner,function = "i2c1";
 567                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 568                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 569                         };
 570
 571                         i2c2_pins_a: i2c2@0 {
 572                                 allwinner,pins = "PB17", "PB18";
 573                                 allwinner,function = "i2c2";
 574                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 575                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 576                         };
 577
 578                         lcd_rgb565_pins: lcd_rgb565@0 {
 579                                 allwinner,pins = "PD3", "PD4", "PD5", "PD6", "PD7",
 580                                                  "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
 581                                                  "PD19", "PD20", "PD21", "PD22", "PD23",
 582                                                  "PD24", "PD25", "PD26", "PD27";
 583                                 allwinner,function = "lcd0";
 584                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 585                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 586                         };
 587
 588                         mmc0_pins_a: mmc0@0 {
 589                                 allwinner,pins = "PF0", "PF1", "PF2", "PF3",
 590                                                  "PF4", "PF5";
 591                                 allwinner,function = "mmc0";
 592                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 593                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 594                         };
 595
 596                         mmc2_pins_a: mmc2@0 {
 597                                 allwinner,pins = "PC6", "PC7", "PC8", "PC9",
 598                                         "PC10", "PC11", "PC12", "PC13",
 599                                         "PC14", "PC15";
 600                                 allwinner,function = "mmc2";
 601                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 602                                 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
 603                         };
 604
 605                         spi2_pins_a: spi2@0 {
 606                                 allwinner,pins = "PE1", "PE2", "PE3";
 607                                 allwinner,function = "spi2";
 608                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 609                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 610                         };
 611
 612                         spi2_cs0_pins_a: spi2-cs0@0 {
 613                                 allwinner,pins = "PE0";
 614                                 allwinner,function = "spi2";
 615                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 616                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 617                         };
 618
 619                         uart3_pins_a: uart3@0 {
 620                                 allwinner,pins = "PG9", "PG10";
 621                                 allwinner,function = "uart3";
 622                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 623                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 624                         };
 625
 626                         uart3_pins_cts_rts_a: uart3-cts-rts@0 {
 627                                 allwinner,pins = "PG11", "PG12";
 628                                 allwinner,function = "uart3";
 629                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 630                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 631                         };
 632
 633                         pwm0_pins: pwm0 {
 634                                 allwinner,pins = "PB2";
 635                                 allwinner,function = "pwm";
 636                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 637                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 638                         };
 639                 };
 640
 641                 timer@01c20c00 {
 642                         compatible = "allwinner,sun4i-a10-timer";
 643                         reg = <0x01c20c00 0x90>;
 644                         interrupts = <22>;
 645                         clocks = <&osc24M>;
 646                 };
 647
 648                 wdt: watchdog@01c20c90 {
 649                         compatible = "allwinner,sun4i-a10-wdt";
 650                         reg = <0x01c20c90 0x10>;
 651                 };
 652
 653                 lradc: lradc@01c22800 {
 654                         compatible = "allwinner,sun4i-a10-lradc-keys";
 655                         reg = <0x01c22800 0x100>;
 656                         interrupts = <31>;
 657                         status = "disabled";
 658                 };
 659
 660                 codec: codec@01c22c00 {
 661                         #sound-dai-cells = <0>;
 662                         compatible = "allwinner,sun4i-a10-codec";
 663                         reg = <0x01c22c00 0x40>;
 664                         interrupts = <30>;
 665                         clocks = <&apb0_gates 0>, <&codec_clk>;
 666                         clock-names = "apb", "codec";
 667                         dmas = <&dma SUN4I_DMA_NORMAL 19>,
 668                                <&dma SUN4I_DMA_NORMAL 19>;
 669                         dma-names = "rx", "tx";
 670                         status = "disabled";
 671                 };
 672
 673                 sid: eeprom@01c23800 {
 674                         compatible = "allwinner,sun4i-a10-sid";
 675                         reg = <0x01c23800 0x10>;
 676                 };
 677
 678                 rtp: rtp@01c25000 {
 679                         compatible = "allwinner,sun5i-a13-ts";
 680                         reg = <0x01c25000 0x100>;
 681                         interrupts = <29>;
 682                         #thermal-sensor-cells = <0>;
 683                 };
 684
 685                 uart1: serial@01c28400 {
 686                         compatible = "snps,dw-apb-uart";
 687                         reg = <0x01c28400 0x400>;
 688                         interrupts = <2>;
 689                         reg-shift = <2>;
 690                         reg-io-width = <4>;
 691                         clocks = <&apb1_gates 17>;
 692                         status = "disabled";
 693                 };
 694
 695                 uart3: serial@01c28c00 {
 696                         compatible = "snps,dw-apb-uart";
 697                         reg = <0x01c28c00 0x400>;
 698                         interrupts = <4>;
 699                         reg-shift = <2>;
 700                         reg-io-width = <4>;
 701                         clocks = <&apb1_gates 19>;
 702                         status = "disabled";
 703                 };
 704
 705                 i2c0: i2c@01c2ac00 {
 706                         compatible = "allwinner,sun4i-a10-i2c";
 707                         reg = <0x01c2ac00 0x400>;
 708                         interrupts = <7>;
 709                         clocks = <&apb1_gates 0>;
 710                         status = "disabled";
 711                         #address-cells = <1>;
 712                         #size-cells = <0>;
 713                 };
 714
 715                 i2c1: i2c@01c2b000 {
 716                         compatible = "allwinner,sun4i-a10-i2c";
 717                         reg = <0x01c2b000 0x400>;
 718                         interrupts = <8>;
 719                         clocks = <&apb1_gates 1>;
 720                         status = "disabled";
 721                         #address-cells = <1>;
 722                         #size-cells = <0>;
 723                 };
 724
 725                 i2c2: i2c@01c2b400 {
 726                         compatible = "allwinner,sun4i-a10-i2c";
 727                         reg = <0x01c2b400 0x400>;
 728                         interrupts = <9>;
 729                         clocks = <&apb1_gates 2>;
 730                         status = "disabled";
 731                         #address-cells = <1>;
 732                         #size-cells = <0>;
 733                 };
 734
 735                 timer@01c60000 {
 736                         compatible = "allwinner,sun5i-a13-hstimer";
 737                         reg = <0x01c60000 0x1000>;
 738                         interrupts = <82>, <83>;
 739                         clocks = <&ahb_gates 28>;
 740                 };
 741         };
 742 };