2 * Copyright 2012-2015 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This library is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This library is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
45 #include "skeleton.dtsi"
47 #include <dt-bindings/clock/sun5i-ccu.h>
48 #include <dt-bindings/dma/sun4i-a10.h>
49 #include <dt-bindings/pinctrl/sun4i-a10.h>
50 #include <dt-bindings/reset/sun5i-ccu.h>
53 interrupt-parent = <&intc>;
61 compatible = "arm,cortex-a8";
63 clocks = <&ccu CLK_CPU>;
72 osc24M: clk@01c20050 {
74 compatible = "fixed-clock";
75 clock-frequency = <24000000>;
76 clock-output-names = "osc24M";
81 compatible = "fixed-clock";
82 clock-frequency = <32768>;
83 clock-output-names = "osc32k";
88 compatible = "simple-bus";
93 sram-controller@01c00000 {
94 compatible = "allwinner,sun4i-a10-sram-controller";
95 reg = <0x01c00000 0x30>;
100 sram_a: sram@00000000 {
101 compatible = "mmio-sram";
102 reg = <0x00000000 0xc000>;
103 #address-cells = <1>;
105 ranges = <0 0x00000000 0xc000>;
108 sram_d: sram@00010000 {
109 compatible = "mmio-sram";
110 reg = <0x00010000 0x1000>;
111 #address-cells = <1>;
113 ranges = <0 0x00010000 0x1000>;
115 otg_sram: sram-section@0000 {
116 compatible = "allwinner,sun4i-a10-sram-d";
117 reg = <0x0000 0x1000>;
123 dma: dma-controller@01c02000 {
124 compatible = "allwinner,sun4i-a10-dma";
125 reg = <0x01c02000 0x1000>;
127 clocks = <&ccu CLK_AHB_DMA>;
132 compatible = "allwinner,sun4i-a10-spi";
133 reg = <0x01c05000 0x1000>;
135 clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
136 clock-names = "ahb", "mod";
137 dmas = <&dma SUN4I_DMA_DEDICATED 27>,
138 <&dma SUN4I_DMA_DEDICATED 26>;
139 dma-names = "rx", "tx";
141 #address-cells = <1>;
146 compatible = "allwinner,sun4i-a10-spi";
147 reg = <0x01c06000 0x1000>;
149 clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
150 clock-names = "ahb", "mod";
151 dmas = <&dma SUN4I_DMA_DEDICATED 9>,
152 <&dma SUN4I_DMA_DEDICATED 8>;
153 dma-names = "rx", "tx";
155 #address-cells = <1>;
160 compatible = "allwinner,sun5i-a13-mmc";
161 reg = <0x01c0f000 0x1000>;
162 clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>;
163 clock-names = "ahb", "mmc";
166 #address-cells = <1>;
171 compatible = "allwinner,sun5i-a13-mmc";
172 reg = <0x01c10000 0x1000>;
173 clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>;
174 clock-names = "ahb", "mmc";
177 #address-cells = <1>;
182 compatible = "allwinner,sun5i-a13-mmc";
183 reg = <0x01c11000 0x1000>;
184 clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>;
185 clock-names = "ahb", "mmc";
188 #address-cells = <1>;
192 usb_otg: usb@01c13000 {
193 compatible = "allwinner,sun4i-a10-musb";
194 reg = <0x01c13000 0x0400>;
195 clocks = <&ccu CLK_AHB_OTG>;
197 interrupt-names = "mc";
200 extcon = <&usbphy 0>;
201 allwinner,sram = <&otg_sram 1>;
205 usbphy: phy@01c13400 {
207 compatible = "allwinner,sun5i-a13-usb-phy";
208 reg = <0x01c13400 0x10 0x01c14800 0x4>;
209 reg-names = "phy_ctrl", "pmu1";
210 clocks = <&ccu CLK_USB_PHY0>;
211 clock-names = "usb_phy";
212 resets = <&ccu RST_USB_PHY0>, <&ccu RST_USB_PHY1>;
213 reset-names = "usb0_reset", "usb1_reset";
217 ehci0: usb@01c14000 {
218 compatible = "allwinner,sun5i-a13-ehci", "generic-ehci";
219 reg = <0x01c14000 0x100>;
221 clocks = <&ccu CLK_AHB_EHCI>;
227 ohci0: usb@01c14400 {
228 compatible = "allwinner,sun5i-a13-ohci", "generic-ohci";
229 reg = <0x01c14400 0x100>;
231 clocks = <&ccu CLK_USB_OHCI>, <&ccu CLK_AHB_OHCI>;
238 compatible = "allwinner,sun4i-a10-spi";
239 reg = <0x01c17000 0x1000>;
241 clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
242 clock-names = "ahb", "mod";
243 dmas = <&dma SUN4I_DMA_DEDICATED 29>,
244 <&dma SUN4I_DMA_DEDICATED 28>;
245 dma-names = "rx", "tx";
247 #address-cells = <1>;
251 ccu: clock@01c20000 {
252 reg = <0x01c20000 0x400>;
253 clocks = <&osc24M>, <&osc32k>;
254 clock-names = "hosc", "losc";
259 intc: interrupt-controller@01c20400 {
260 compatible = "allwinner,sun4i-a10-ic";
261 reg = <0x01c20400 0x400>;
262 interrupt-controller;
263 #interrupt-cells = <1>;
266 pio: pinctrl@01c20800 {
267 reg = <0x01c20800 0x400>;
269 clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
270 clock-names = "apb", "hosc", "losc";
272 interrupt-controller;
273 #interrupt-cells = <3>;
276 i2c0_pins_a: i2c0@0 {
277 allwinner,pins = "PB0", "PB1";
278 allwinner,function = "i2c0";
279 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
280 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
283 i2c1_pins_a: i2c1@0 {
284 allwinner,pins = "PB15", "PB16";
285 allwinner,function = "i2c1";
286 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
287 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
290 i2c2_pins_a: i2c2@0 {
291 allwinner,pins = "PB17", "PB18";
292 allwinner,function = "i2c2";
293 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
294 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
297 lcd_rgb565_pins: lcd_rgb565@0 {
298 allwinner,pins = "PD3", "PD4", "PD5", "PD6", "PD7",
299 "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
300 "PD19", "PD20", "PD21", "PD22", "PD23",
301 "PD24", "PD25", "PD26", "PD27";
302 allwinner,function = "lcd0";
303 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
304 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
307 mmc0_pins_a: mmc0@0 {
308 allwinner,pins = "PF0", "PF1", "PF2", "PF3",
310 allwinner,function = "mmc0";
311 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
312 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
315 mmc2_pins_a: mmc2@0 {
316 allwinner,pins = "PC6", "PC7", "PC8", "PC9",
317 "PC10", "PC11", "PC12", "PC13",
319 allwinner,function = "mmc2";
320 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
321 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
324 spi2_pins_a: spi2@0 {
325 allwinner,pins = "PE1", "PE2", "PE3";
326 allwinner,function = "spi2";
327 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
328 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
331 spi2_cs0_pins_a: spi2-cs0@0 {
332 allwinner,pins = "PE0";
333 allwinner,function = "spi2";
334 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
335 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
338 uart3_pins_a: uart3@0 {
339 allwinner,pins = "PG9", "PG10";
340 allwinner,function = "uart3";
341 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
342 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
345 uart3_pins_cts_rts_a: uart3-cts-rts@0 {
346 allwinner,pins = "PG11", "PG12";
347 allwinner,function = "uart3";
348 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
349 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
353 allwinner,pins = "PB2";
354 allwinner,function = "pwm";
355 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
356 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
361 compatible = "allwinner,sun4i-a10-timer";
362 reg = <0x01c20c00 0x90>;
364 clocks = <&ccu CLK_HOSC>;
367 wdt: watchdog@01c20c90 {
368 compatible = "allwinner,sun4i-a10-wdt";
369 reg = <0x01c20c90 0x10>;
372 lradc: lradc@01c22800 {
373 compatible = "allwinner,sun4i-a10-lradc-keys";
374 reg = <0x01c22800 0x100>;
379 codec: codec@01c22c00 {
380 #sound-dai-cells = <0>;
381 compatible = "allwinner,sun4i-a10-codec";
382 reg = <0x01c22c00 0x40>;
384 clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;
385 clock-names = "apb", "codec";
386 dmas = <&dma SUN4I_DMA_NORMAL 19>,
387 <&dma SUN4I_DMA_NORMAL 19>;
388 dma-names = "rx", "tx";
392 sid: eeprom@01c23800 {
393 compatible = "allwinner,sun4i-a10-sid";
394 reg = <0x01c23800 0x10>;
398 compatible = "allwinner,sun5i-a13-ts";
399 reg = <0x01c25000 0x100>;
401 #thermal-sensor-cells = <0>;
404 uart1: serial@01c28400 {
405 compatible = "snps,dw-apb-uart";
406 reg = <0x01c28400 0x400>;
410 clocks = <&ccu CLK_APB1_UART1>;
414 uart3: serial@01c28c00 {
415 compatible = "snps,dw-apb-uart";
416 reg = <0x01c28c00 0x400>;
420 clocks = <&ccu CLK_APB1_UART3>;
425 compatible = "allwinner,sun4i-a10-i2c";
426 reg = <0x01c2ac00 0x400>;
428 clocks = <&ccu CLK_APB1_I2C0>;
430 #address-cells = <1>;
435 compatible = "allwinner,sun4i-a10-i2c";
436 reg = <0x01c2b000 0x400>;
438 clocks = <&ccu CLK_APB1_I2C1>;
440 #address-cells = <1>;
445 compatible = "allwinner,sun4i-a10-i2c";
446 reg = <0x01c2b400 0x400>;
448 clocks = <&ccu CLK_APB1_I2C2>;
450 #address-cells = <1>;
455 compatible = "allwinner,sun5i-a13-hstimer";
456 reg = <0x01c60000 0x1000>;
457 interrupts = <82>, <83>;
458 clocks = <&ccu CLK_AHB_HSTIMER>;