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x86/ioapic: Restore IO-APIC irq_chip retrigger callback
[mirror_ubuntu-zesty-kernel.git] / arch / arm / boot / dts / sun6i-a31.dtsi
1 /*
2 * Copyright 2013 Maxime Ripard
3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * Or, alternatively,
22 *
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
30 * conditions:
31 *
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
34 *
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
43 */
44
45 #include "skeleton.dtsi"
46
47 #include <dt-bindings/interrupt-controller/arm-gic.h>
48 #include <dt-bindings/thermal/thermal.h>
49
50 #include <dt-bindings/clock/sun6i-a31-ccu.h>
51 #include <dt-bindings/pinctrl/sun4i-a10.h>
52 #include <dt-bindings/reset/sun6i-a31-ccu.h>
53
54 / {
55 interrupt-parent = <&gic>;
56
57 aliases {
58 ethernet0 = &gmac;
59 };
60
61 chosen {
62 #address-cells = <1>;
63 #size-cells = <1>;
64 ranges;
65
66 simplefb_hdmi: framebuffer@0 {
67 compatible = "allwinner,simple-framebuffer",
68 "simple-framebuffer";
69 allwinner,pipeline = "de_be0-lcd0-hdmi";
70 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
71 <&ccu CLK_AHB1_HDMI>, <&ccu CLK_DRAM_BE0>,
72 <&ccu CLK_IEP_DRC0>, <&ccu CLK_BE0>,
73 <&ccu CLK_LCD0_CH1>, <&ccu CLK_HDMI>;
74 status = "disabled";
75 };
76
77 simplefb_lcd: framebuffer@1 {
78 compatible = "allwinner,simple-framebuffer",
79 "simple-framebuffer";
80 allwinner,pipeline = "de_be0-lcd0";
81 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
82 <&ccu CLK_DRAM_BE0>, <&ccu CLK_IEP_DRC0>,
83 <&ccu CLK_BE0>, <&ccu CLK_LCD0_CH0>;
84 status = "disabled";
85 };
86 };
87
88 timer {
89 compatible = "arm,armv7-timer";
90 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
91 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
92 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
93 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
94 clock-frequency = <24000000>;
95 arm,cpu-registers-not-fw-configured;
96 };
97
98 cpus {
99 enable-method = "allwinner,sun6i-a31";
100 #address-cells = <1>;
101 #size-cells = <0>;
102
103 cpu0: cpu@0 {
104 compatible = "arm,cortex-a7";
105 device_type = "cpu";
106 reg = <0>;
107 clocks = <&ccu CLK_CPU>;
108 clock-latency = <244144>; /* 8 32k periods */
109 operating-points = <
110 /* kHz uV */
111 1008000 1200000
112 864000 1200000
113 720000 1100000
114 480000 1000000
115 >;
116 #cooling-cells = <2>;
117 cooling-min-level = <0>;
118 cooling-max-level = <3>;
119 };
120
121 cpu@1 {
122 compatible = "arm,cortex-a7";
123 device_type = "cpu";
124 reg = <1>;
125 };
126
127 cpu@2 {
128 compatible = "arm,cortex-a7";
129 device_type = "cpu";
130 reg = <2>;
131 };
132
133 cpu@3 {
134 compatible = "arm,cortex-a7";
135 device_type = "cpu";
136 reg = <3>;
137 };
138 };
139
140 thermal-zones {
141 cpu_thermal {
142 /* milliseconds */
143 polling-delay-passive = <250>;
144 polling-delay = <1000>;
145 thermal-sensors = <&rtp>;
146
147 cooling-maps {
148 map0 {
149 trip = <&cpu_alert0>;
150 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
151 };
152 };
153
154 trips {
155 cpu_alert0: cpu_alert0 {
156 /* milliCelsius */
157 temperature = <70000>;
158 hysteresis = <2000>;
159 type = "passive";
160 };
161
162 cpu_crit: cpu_crit {
163 /* milliCelsius */
164 temperature = <100000>;
165 hysteresis = <2000>;
166 type = "critical";
167 };
168 };
169 };
170 };
171
172 memory {
173 reg = <0x40000000 0x80000000>;
174 };
175
176 pmu {
177 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
178 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
179 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
180 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
181 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
182 };
183
184 clocks {
185 #address-cells = <1>;
186 #size-cells = <1>;
187 ranges;
188
189 osc24M: osc24M {
190 #clock-cells = <0>;
191 compatible = "fixed-clock";
192 clock-frequency = <24000000>;
193 };
194
195 osc32k: clk@0 {
196 #clock-cells = <0>;
197 compatible = "fixed-clock";
198 clock-frequency = <32768>;
199 clock-output-names = "osc32k";
200 };
201
202 /*
203 * The following two are dummy clocks, placeholders
204 * used in the gmac_tx clock. The gmac driver will
205 * choose one parent depending on the PHY interface
206 * mode, using clk_set_rate auto-reparenting.
207 *
208 * The actual TX clock rate is not controlled by the
209 * gmac_tx clock.
210 */
211 mii_phy_tx_clk: clk@1 {
212 #clock-cells = <0>;
213 compatible = "fixed-clock";
214 clock-frequency = <25000000>;
215 clock-output-names = "mii_phy_tx";
216 };
217
218 gmac_int_tx_clk: clk@2 {
219 #clock-cells = <0>;
220 compatible = "fixed-clock";
221 clock-frequency = <125000000>;
222 clock-output-names = "gmac_int_tx";
223 };
224
225 gmac_tx_clk: clk@01c200d0 {
226 #clock-cells = <0>;
227 compatible = "allwinner,sun7i-a20-gmac-clk";
228 reg = <0x01c200d0 0x4>;
229 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
230 clock-output-names = "gmac_tx";
231 };
232 };
233
234 de: display-engine {
235 compatible = "allwinner,sun6i-a31-display-engine";
236 allwinner,pipelines = <&fe0>;
237 };
238
239 soc@01c00000 {
240 compatible = "simple-bus";
241 #address-cells = <1>;
242 #size-cells = <1>;
243 ranges;
244
245 dma: dma-controller@01c02000 {
246 compatible = "allwinner,sun6i-a31-dma";
247 reg = <0x01c02000 0x1000>;
248 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
249 clocks = <&ccu CLK_AHB1_DMA>;
250 resets = <&ccu RST_AHB1_DMA>;
251 #dma-cells = <1>;
252 };
253
254 tcon0: lcd-controller@01c0c000 {
255 compatible = "allwinner,sun6i-a31-tcon";
256 reg = <0x01c0c000 0x1000>;
257 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
258 resets = <&ccu RST_AHB1_LCD0>;
259 reset-names = "lcd";
260 clocks = <&ccu CLK_AHB1_LCD0>,
261 <&ccu CLK_LCD0_CH0>,
262 <&ccu CLK_LCD0_CH1>;
263 clock-names = "ahb",
264 "tcon-ch0",
265 "tcon-ch1";
266 clock-output-names = "tcon0-pixel-clock";
267 status = "disabled";
268
269 ports {
270 #address-cells = <1>;
271 #size-cells = <0>;
272
273 tcon0_in: port@0 {
274 #address-cells = <1>;
275 #size-cells = <0>;
276 reg = <0>;
277
278 tcon0_in_drc0: endpoint@0 {
279 reg = <0>;
280 remote-endpoint = <&drc0_out_tcon0>;
281 };
282 };
283
284 tcon0_out: port@1 {
285 #address-cells = <1>;
286 #size-cells = <0>;
287 reg = <1>;
288 };
289 };
290 };
291
292 mmc0: mmc@01c0f000 {
293 compatible = "allwinner,sun7i-a20-mmc";
294 reg = <0x01c0f000 0x1000>;
295 clocks = <&ccu CLK_AHB1_MMC0>,
296 <&ccu CLK_MMC0>,
297 <&ccu CLK_MMC0_OUTPUT>,
298 <&ccu CLK_MMC0_SAMPLE>;
299 clock-names = "ahb",
300 "mmc",
301 "output",
302 "sample";
303 resets = <&ccu RST_AHB1_MMC0>;
304 reset-names = "ahb";
305 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
306 status = "disabled";
307 #address-cells = <1>;
308 #size-cells = <0>;
309 };
310
311 mmc1: mmc@01c10000 {
312 compatible = "allwinner,sun7i-a20-mmc";
313 reg = <0x01c10000 0x1000>;
314 clocks = <&ccu CLK_AHB1_MMC1>,
315 <&ccu CLK_MMC1>,
316 <&ccu CLK_MMC1_OUTPUT>,
317 <&ccu CLK_MMC1_SAMPLE>;
318 clock-names = "ahb",
319 "mmc",
320 "output",
321 "sample";
322 resets = <&ccu RST_AHB1_MMC1>;
323 reset-names = "ahb";
324 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
325 status = "disabled";
326 #address-cells = <1>;
327 #size-cells = <0>;
328 };
329
330 mmc2: mmc@01c11000 {
331 compatible = "allwinner,sun7i-a20-mmc";
332 reg = <0x01c11000 0x1000>;
333 clocks = <&ccu CLK_AHB1_MMC2>,
334 <&ccu CLK_MMC2>,
335 <&ccu CLK_MMC2_OUTPUT>,
336 <&ccu CLK_MMC2_SAMPLE>;
337 clock-names = "ahb",
338 "mmc",
339 "output",
340 "sample";
341 resets = <&ccu RST_AHB1_MMC2>;
342 reset-names = "ahb";
343 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
344 status = "disabled";
345 #address-cells = <1>;
346 #size-cells = <0>;
347 };
348
349 mmc3: mmc@01c12000 {
350 compatible = "allwinner,sun7i-a20-mmc";
351 reg = <0x01c12000 0x1000>;
352 clocks = <&ccu CLK_AHB1_MMC3>,
353 <&ccu CLK_MMC3>,
354 <&ccu CLK_MMC3_OUTPUT>,
355 <&ccu CLK_MMC3_SAMPLE>;
356 clock-names = "ahb",
357 "mmc",
358 "output",
359 "sample";
360 resets = <&ccu RST_AHB1_MMC3>;
361 reset-names = "ahb";
362 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
363 status = "disabled";
364 #address-cells = <1>;
365 #size-cells = <0>;
366 };
367
368 usb_otg: usb@01c19000 {
369 compatible = "allwinner,sun6i-a31-musb";
370 reg = <0x01c19000 0x0400>;
371 clocks = <&ccu CLK_AHB1_OTG>;
372 resets = <&ccu RST_AHB1_OTG>;
373 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
374 interrupt-names = "mc";
375 phys = <&usbphy 0>;
376 phy-names = "usb";
377 extcon = <&usbphy 0>;
378 status = "disabled";
379 };
380
381 usbphy: phy@01c19400 {
382 compatible = "allwinner,sun6i-a31-usb-phy";
383 reg = <0x01c19400 0x10>,
384 <0x01c1a800 0x4>,
385 <0x01c1b800 0x4>;
386 reg-names = "phy_ctrl",
387 "pmu1",
388 "pmu2";
389 clocks = <&ccu CLK_USB_PHY0>,
390 <&ccu CLK_USB_PHY1>,
391 <&ccu CLK_USB_PHY2>;
392 clock-names = "usb0_phy",
393 "usb1_phy",
394 "usb2_phy";
395 resets = <&ccu RST_USB_PHY0>,
396 <&ccu RST_USB_PHY1>,
397 <&ccu RST_USB_PHY2>;
398 reset-names = "usb0_reset",
399 "usb1_reset",
400 "usb2_reset";
401 status = "disabled";
402 #phy-cells = <1>;
403 };
404
405 ehci0: usb@01c1a000 {
406 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
407 reg = <0x01c1a000 0x100>;
408 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
409 clocks = <&ccu CLK_AHB1_EHCI0>;
410 resets = <&ccu RST_AHB1_EHCI0>;
411 phys = <&usbphy 1>;
412 phy-names = "usb";
413 status = "disabled";
414 };
415
416 ohci0: usb@01c1a400 {
417 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
418 reg = <0x01c1a400 0x100>;
419 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
420 clocks = <&ccu CLK_AHB1_OHCI0>, <&ccu CLK_USB_OHCI0>;
421 resets = <&ccu RST_AHB1_OHCI0>;
422 phys = <&usbphy 1>;
423 phy-names = "usb";
424 status = "disabled";
425 };
426
427 ehci1: usb@01c1b000 {
428 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
429 reg = <0x01c1b000 0x100>;
430 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
431 clocks = <&ccu CLK_AHB1_EHCI1>;
432 resets = <&ccu RST_AHB1_EHCI1>;
433 phys = <&usbphy 2>;
434 phy-names = "usb";
435 status = "disabled";
436 };
437
438 ohci1: usb@01c1b400 {
439 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
440 reg = <0x01c1b400 0x100>;
441 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
442 clocks = <&ccu CLK_AHB1_OHCI1>, <&ccu CLK_USB_OHCI1>;
443 resets = <&ccu RST_AHB1_OHCI1>;
444 phys = <&usbphy 2>;
445 phy-names = "usb";
446 status = "disabled";
447 };
448
449 ohci2: usb@01c1c400 {
450 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
451 reg = <0x01c1c400 0x100>;
452 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
453 clocks = <&ccu CLK_AHB1_OHCI2>, <&ccu CLK_USB_OHCI2>;
454 resets = <&ccu RST_AHB1_OHCI2>;
455 status = "disabled";
456 };
457
458 ccu: clock@01c20000 {
459 compatible = "allwinner,sun6i-a31-ccu";
460 reg = <0x01c20000 0x400>;
461 clocks = <&osc24M>, <&osc32k>;
462 clock-names = "hosc", "losc";
463 #clock-cells = <1>;
464 #reset-cells = <1>;
465 };
466
467 pio: pinctrl@01c20800 {
468 compatible = "allwinner,sun6i-a31-pinctrl";
469 reg = <0x01c20800 0x400>;
470 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
471 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
472 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
473 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
474 clocks = <&ccu CLK_APB1_PIO>, <&osc24M>, <&osc32k>;
475 clock-names = "apb", "hosc", "losc";
476 gpio-controller;
477 interrupt-controller;
478 #interrupt-cells = <3>;
479 #gpio-cells = <3>;
480
481 gmac_pins_gmii_a: gmac_gmii@0 {
482 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
483 "PA4", "PA5", "PA6", "PA7",
484 "PA8", "PA9", "PA10", "PA11",
485 "PA12", "PA13", "PA14", "PA15",
486 "PA16", "PA17", "PA18", "PA19",
487 "PA20", "PA21", "PA22", "PA23",
488 "PA24", "PA25", "PA26", "PA27";
489 allwinner,function = "gmac";
490 /*
491 * data lines in GMII mode run at 125MHz and
492 * might need a higher signal drive strength
493 */
494 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
495 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
496 };
497
498 gmac_pins_mii_a: gmac_mii@0 {
499 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
500 "PA8", "PA9", "PA11",
501 "PA12", "PA13", "PA14", "PA19",
502 "PA20", "PA21", "PA22", "PA23",
503 "PA24", "PA26", "PA27";
504 allwinner,function = "gmac";
505 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
506 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
507 };
508
509 gmac_pins_rgmii_a: gmac_rgmii@0 {
510 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
511 "PA9", "PA10", "PA11",
512 "PA12", "PA13", "PA14", "PA19",
513 "PA20", "PA25", "PA26", "PA27";
514 allwinner,function = "gmac";
515 /*
516 * data lines in RGMII mode use DDR mode
517 * and need a higher signal drive strength
518 */
519 allwinner,drive = <SUN4I_PINCTRL_40_MA>;
520 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
521 };
522
523 i2c0_pins_a: i2c0@0 {
524 allwinner,pins = "PH14", "PH15";
525 allwinner,function = "i2c0";
526 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
527 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
528 };
529
530 i2c1_pins_a: i2c1@0 {
531 allwinner,pins = "PH16", "PH17";
532 allwinner,function = "i2c1";
533 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
534 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
535 };
536
537 i2c2_pins_a: i2c2@0 {
538 allwinner,pins = "PH18", "PH19";
539 allwinner,function = "i2c2";
540 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
541 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
542 };
543
544 lcd0_rgb888_pins: lcd0_rgb888 {
545 allwinner,pins = "PD0", "PD1", "PD2", "PD3",
546 "PD4", "PD5", "PD6", "PD7",
547 "PD8", "PD9", "PD10", "PD11",
548 "PD12", "PD13", "PD14", "PD15",
549 "PD16", "PD17", "PD18", "PD19",
550 "PD20", "PD21", "PD22", "PD23",
551 "PD24", "PD25", "PD26", "PD27";
552 allwinner,function = "lcd0";
553 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
554 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
555 };
556
557 mmc0_pins_a: mmc0@0 {
558 allwinner,pins = "PF0", "PF1", "PF2",
559 "PF3", "PF4", "PF5";
560 allwinner,function = "mmc0";
561 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
562 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
563 };
564
565 mmc1_pins_a: mmc1@0 {
566 allwinner,pins = "PG0", "PG1", "PG2", "PG3",
567 "PG4", "PG5";
568 allwinner,function = "mmc1";
569 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
570 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
571 };
572
573 mmc2_pins_a: mmc2@0 {
574 allwinner,pins = "PC6", "PC7", "PC8", "PC9",
575 "PC10", "PC11";
576 allwinner,function = "mmc2";
577 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
578 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
579 };
580
581 mmc2_8bit_emmc_pins: mmc2@1 {
582 allwinner,pins = "PC6", "PC7", "PC8", "PC9",
583 "PC10", "PC11", "PC12",
584 "PC13", "PC14", "PC15",
585 "PC24";
586 allwinner,function = "mmc2";
587 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
588 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
589 };
590
591 mmc3_8bit_emmc_pins: mmc3@1 {
592 allwinner,pins = "PC6", "PC7", "PC8", "PC9",
593 "PC10", "PC11", "PC12",
594 "PC13", "PC14", "PC15",
595 "PC24";
596 allwinner,function = "mmc3";
597 allwinner,drive = <SUN4I_PINCTRL_40_MA>;
598 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
599 };
600
601 uart0_pins_a: uart0@0 {
602 allwinner,pins = "PH20", "PH21";
603 allwinner,function = "uart0";
604 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
605 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
606 };
607 };
608
609 timer@01c20c00 {
610 compatible = "allwinner,sun4i-a10-timer";
611 reg = <0x01c20c00 0xa0>;
612 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
613 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
614 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
615 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
616 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
617 clocks = <&osc24M>;
618 };
619
620 wdt1: watchdog@01c20ca0 {
621 compatible = "allwinner,sun6i-a31-wdt";
622 reg = <0x01c20ca0 0x20>;
623 };
624
625 lradc: lradc@01c22800 {
626 compatible = "allwinner,sun4i-a10-lradc-keys";
627 reg = <0x01c22800 0x100>;
628 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
629 status = "disabled";
630 };
631
632 rtp: rtp@01c25000 {
633 compatible = "allwinner,sun6i-a31-ts";
634 reg = <0x01c25000 0x100>;
635 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
636 #thermal-sensor-cells = <0>;
637 };
638
639 uart0: serial@01c28000 {
640 compatible = "snps,dw-apb-uart";
641 reg = <0x01c28000 0x400>;
642 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
643 reg-shift = <2>;
644 reg-io-width = <4>;
645 clocks = <&ccu CLK_APB2_UART0>;
646 resets = <&ccu RST_APB2_UART0>;
647 dmas = <&dma 6>, <&dma 6>;
648 dma-names = "rx", "tx";
649 status = "disabled";
650 };
651
652 uart1: serial@01c28400 {
653 compatible = "snps,dw-apb-uart";
654 reg = <0x01c28400 0x400>;
655 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
656 reg-shift = <2>;
657 reg-io-width = <4>;
658 clocks = <&ccu CLK_APB2_UART1>;
659 resets = <&ccu RST_APB2_UART1>;
660 dmas = <&dma 7>, <&dma 7>;
661 dma-names = "rx", "tx";
662 status = "disabled";
663 };
664
665 uart2: serial@01c28800 {
666 compatible = "snps,dw-apb-uart";
667 reg = <0x01c28800 0x400>;
668 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
669 reg-shift = <2>;
670 reg-io-width = <4>;
671 clocks = <&ccu CLK_APB2_UART2>;
672 resets = <&ccu RST_APB2_UART2>;
673 dmas = <&dma 8>, <&dma 8>;
674 dma-names = "rx", "tx";
675 status = "disabled";
676 };
677
678 uart3: serial@01c28c00 {
679 compatible = "snps,dw-apb-uart";
680 reg = <0x01c28c00 0x400>;
681 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
682 reg-shift = <2>;
683 reg-io-width = <4>;
684 clocks = <&ccu CLK_APB2_UART3>;
685 resets = <&ccu RST_APB2_UART3>;
686 dmas = <&dma 9>, <&dma 9>;
687 dma-names = "rx", "tx";
688 status = "disabled";
689 };
690
691 uart4: serial@01c29000 {
692 compatible = "snps,dw-apb-uart";
693 reg = <0x01c29000 0x400>;
694 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
695 reg-shift = <2>;
696 reg-io-width = <4>;
697 clocks = <&ccu CLK_APB2_UART4>;
698 resets = <&ccu RST_APB2_UART4>;
699 dmas = <&dma 10>, <&dma 10>;
700 dma-names = "rx", "tx";
701 status = "disabled";
702 };
703
704 uart5: serial@01c29400 {
705 compatible = "snps,dw-apb-uart";
706 reg = <0x01c29400 0x400>;
707 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
708 reg-shift = <2>;
709 reg-io-width = <4>;
710 clocks = <&ccu CLK_APB2_UART5>;
711 resets = <&ccu RST_APB2_UART5>;
712 dmas = <&dma 22>, <&dma 22>;
713 dma-names = "rx", "tx";
714 status = "disabled";
715 };
716
717 i2c0: i2c@01c2ac00 {
718 compatible = "allwinner,sun6i-a31-i2c";
719 reg = <0x01c2ac00 0x400>;
720 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
721 clocks = <&ccu CLK_APB2_I2C0>;
722 resets = <&ccu RST_APB2_I2C0>;
723 status = "disabled";
724 #address-cells = <1>;
725 #size-cells = <0>;
726 };
727
728 i2c1: i2c@01c2b000 {
729 compatible = "allwinner,sun6i-a31-i2c";
730 reg = <0x01c2b000 0x400>;
731 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
732 clocks = <&ccu CLK_APB2_I2C1>;
733 resets = <&ccu RST_APB2_I2C1>;
734 status = "disabled";
735 #address-cells = <1>;
736 #size-cells = <0>;
737 };
738
739 i2c2: i2c@01c2b400 {
740 compatible = "allwinner,sun6i-a31-i2c";
741 reg = <0x01c2b400 0x400>;
742 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
743 clocks = <&ccu CLK_APB2_I2C2>;
744 resets = <&ccu RST_APB2_I2C2>;
745 status = "disabled";
746 #address-cells = <1>;
747 #size-cells = <0>;
748 };
749
750 i2c3: i2c@01c2b800 {
751 compatible = "allwinner,sun6i-a31-i2c";
752 reg = <0x01c2b800 0x400>;
753 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
754 clocks = <&ccu CLK_APB2_I2C3>;
755 resets = <&ccu RST_APB2_I2C3>;
756 status = "disabled";
757 #address-cells = <1>;
758 #size-cells = <0>;
759 };
760
761 gmac: ethernet@01c30000 {
762 compatible = "allwinner,sun7i-a20-gmac";
763 reg = <0x01c30000 0x1054>;
764 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
765 interrupt-names = "macirq";
766 clocks = <&ccu CLK_AHB1_EMAC>, <&gmac_tx_clk>;
767 clock-names = "stmmaceth", "allwinner_gmac_tx";
768 resets = <&ccu RST_AHB1_EMAC>;
769 reset-names = "stmmaceth";
770 snps,pbl = <2>;
771 snps,fixed-burst;
772 snps,force_sf_dma_mode;
773 status = "disabled";
774 #address-cells = <1>;
775 #size-cells = <0>;
776 };
777
778 crypto: crypto-engine@01c15000 {
779 compatible = "allwinner,sun4i-a10-crypto";
780 reg = <0x01c15000 0x1000>;
781 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
782 clocks = <&ccu CLK_AHB1_SS>, <&ccu CLK_SS>;
783 clock-names = "ahb", "mod";
784 resets = <&ccu RST_AHB1_SS>;
785 reset-names = "ahb";
786 };
787
788 codec: codec@01c22c00 {
789 #sound-dai-cells = <0>;
790 compatible = "allwinner,sun6i-a31-codec";
791 reg = <0x01c22c00 0x400>;
792 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
793 clocks = <&ccu CLK_APB1_CODEC>, <&ccu CLK_CODEC>;
794 clock-names = "apb", "codec";
795 resets = <&ccu RST_APB1_CODEC>;
796 dmas = <&dma 15>, <&dma 15>;
797 dma-names = "rx", "tx";
798 status = "disabled";
799 };
800
801 timer@01c60000 {
802 compatible = "allwinner,sun6i-a31-hstimer",
803 "allwinner,sun7i-a20-hstimer";
804 reg = <0x01c60000 0x1000>;
805 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
806 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
807 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
808 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
809 clocks = <&ccu CLK_AHB1_HSTIMER>;
810 resets = <&ccu RST_AHB1_HSTIMER>;
811 };
812
813 spi0: spi@01c68000 {
814 compatible = "allwinner,sun6i-a31-spi";
815 reg = <0x01c68000 0x1000>;
816 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
817 clocks = <&ccu CLK_AHB1_SPI0>, <&ccu CLK_SPI0>;
818 clock-names = "ahb", "mod";
819 dmas = <&dma 23>, <&dma 23>;
820 dma-names = "rx", "tx";
821 resets = <&ccu RST_AHB1_SPI0>;
822 status = "disabled";
823 };
824
825 spi1: spi@01c69000 {
826 compatible = "allwinner,sun6i-a31-spi";
827 reg = <0x01c69000 0x1000>;
828 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
829 clocks = <&ccu CLK_AHB1_SPI1>, <&ccu CLK_SPI1>;
830 clock-names = "ahb", "mod";
831 dmas = <&dma 24>, <&dma 24>;
832 dma-names = "rx", "tx";
833 resets = <&ccu RST_AHB1_SPI1>;
834 status = "disabled";
835 };
836
837 spi2: spi@01c6a000 {
838 compatible = "allwinner,sun6i-a31-spi";
839 reg = <0x01c6a000 0x1000>;
840 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
841 clocks = <&ccu CLK_AHB1_SPI2>, <&ccu CLK_SPI2>;
842 clock-names = "ahb", "mod";
843 dmas = <&dma 25>, <&dma 25>;
844 dma-names = "rx", "tx";
845 resets = <&ccu RST_AHB1_SPI2>;
846 status = "disabled";
847 };
848
849 spi3: spi@01c6b000 {
850 compatible = "allwinner,sun6i-a31-spi";
851 reg = <0x01c6b000 0x1000>;
852 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
853 clocks = <&ccu CLK_AHB1_SPI3>, <&ccu CLK_SPI3>;
854 clock-names = "ahb", "mod";
855 dmas = <&dma 26>, <&dma 26>;
856 dma-names = "rx", "tx";
857 resets = <&ccu RST_AHB1_SPI3>;
858 status = "disabled";
859 };
860
861 gic: interrupt-controller@01c81000 {
862 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
863 reg = <0x01c81000 0x1000>,
864 <0x01c82000 0x1000>,
865 <0x01c84000 0x2000>,
866 <0x01c86000 0x2000>;
867 interrupt-controller;
868 #interrupt-cells = <3>;
869 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
870 };
871
872 fe0: display-frontend@01e00000 {
873 compatible = "allwinner,sun6i-a31-display-frontend";
874 reg = <0x01e00000 0x20000>;
875 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
876 clocks = <&ccu CLK_AHB1_FE0>, <&ccu CLK_FE0>,
877 <&ccu CLK_DRAM_FE0>;
878 clock-names = "ahb", "mod",
879 "ram";
880 resets = <&ccu RST_AHB1_FE0>;
881
882 ports {
883 #address-cells = <1>;
884 #size-cells = <0>;
885
886 fe0_out: port@1 {
887 #address-cells = <1>;
888 #size-cells = <0>;
889 reg = <1>;
890
891 fe0_out_be0: endpoint@0 {
892 reg = <0>;
893 remote-endpoint = <&be0_in_fe0>;
894 };
895 };
896 };
897 };
898
899 be0: display-backend@01e60000 {
900 compatible = "allwinner,sun6i-a31-display-backend";
901 reg = <0x01e60000 0x10000>;
902 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
903 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_BE0>,
904 <&ccu CLK_DRAM_BE0>;
905 clock-names = "ahb", "mod",
906 "ram";
907 resets = <&ccu RST_AHB1_BE0>;
908
909 assigned-clocks = <&ccu CLK_BE0>;
910 assigned-clock-rates = <300000000>;
911
912 ports {
913 #address-cells = <1>;
914 #size-cells = <0>;
915
916 be0_in: port@0 {
917 #address-cells = <1>;
918 #size-cells = <0>;
919 reg = <0>;
920
921 be0_in_fe0: endpoint@0 {
922 reg = <0>;
923 remote-endpoint = <&fe0_out_be0>;
924 };
925 };
926
927 be0_out: port@1 {
928 #address-cells = <1>;
929 #size-cells = <0>;
930 reg = <1>;
931
932 be0_out_drc0: endpoint@0 {
933 reg = <0>;
934 remote-endpoint = <&drc0_in_be0>;
935 };
936 };
937 };
938 };
939
940 drc0: drc@01e70000 {
941 compatible = "allwinner,sun6i-a31-drc";
942 reg = <0x01e70000 0x10000>;
943 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
944 clocks = <&ccu CLK_AHB1_DRC0>, <&ccu CLK_IEP_DRC0>,
945 <&ccu CLK_DRAM_DRC0>;
946 clock-names = "ahb", "mod",
947 "ram";
948 resets = <&ccu RST_AHB1_DRC0>;
949
950 assigned-clocks = <&ccu CLK_IEP_DRC0>;
951 assigned-clock-rates = <300000000>;
952
953 ports {
954 #address-cells = <1>;
955 #size-cells = <0>;
956
957 drc0_in: port@0 {
958 #address-cells = <1>;
959 #size-cells = <0>;
960 reg = <0>;
961
962 drc0_in_be0: endpoint@0 {
963 reg = <0>;
964 remote-endpoint = <&be0_out_drc0>;
965 };
966 };
967
968 drc0_out: port@1 {
969 #address-cells = <1>;
970 #size-cells = <0>;
971 reg = <1>;
972
973 drc0_out_tcon0: endpoint@0 {
974 reg = <0>;
975 remote-endpoint = <&tcon0_in_drc0>;
976 };
977 };
978 };
979 };
980
981 rtc: rtc@01f00000 {
982 compatible = "allwinner,sun6i-a31-rtc";
983 reg = <0x01f00000 0x54>;
984 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
985 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
986 };
987
988 nmi_intc: interrupt-controller@01f00c0c {
989 compatible = "allwinner,sun6i-a31-sc-nmi";
990 interrupt-controller;
991 #interrupt-cells = <2>;
992 reg = <0x01f00c0c 0x38>;
993 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
994 };
995
996 prcm@01f01400 {
997 compatible = "allwinner,sun6i-a31-prcm";
998 reg = <0x01f01400 0x200>;
999
1000 ar100: ar100_clk {
1001 compatible = "allwinner,sun6i-a31-ar100-clk";
1002 #clock-cells = <0>;
1003 clocks = <&osc32k>, <&osc24M>,
1004 <&ccu CLK_PLL_PERIPH>,
1005 <&ccu CLK_PLL_PERIPH>;
1006 clock-output-names = "ar100";
1007 };
1008
1009 ahb0: ahb0_clk {
1010 compatible = "fixed-factor-clock";
1011 #clock-cells = <0>;
1012 clock-div = <1>;
1013 clock-mult = <1>;
1014 clocks = <&ar100>;
1015 clock-output-names = "ahb0";
1016 };
1017
1018 apb0: apb0_clk {
1019 compatible = "allwinner,sun6i-a31-apb0-clk";
1020 #clock-cells = <0>;
1021 clocks = <&ahb0>;
1022 clock-output-names = "apb0";
1023 };
1024
1025 apb0_gates: apb0_gates_clk {
1026 compatible = "allwinner,sun6i-a31-apb0-gates-clk";
1027 #clock-cells = <1>;
1028 clocks = <&apb0>;
1029 clock-output-names = "apb0_pio", "apb0_ir",
1030 "apb0_timer", "apb0_p2wi",
1031 "apb0_uart", "apb0_1wire",
1032 "apb0_i2c";
1033 };
1034
1035 ir_clk: ir_clk {
1036 #clock-cells = <0>;
1037 compatible = "allwinner,sun4i-a10-mod0-clk";
1038 clocks = <&osc32k>, <&osc24M>;
1039 clock-output-names = "ir";
1040 };
1041
1042 apb0_rst: apb0_rst {
1043 compatible = "allwinner,sun6i-a31-clock-reset";
1044 #reset-cells = <1>;
1045 };
1046 };
1047
1048 cpucfg@01f01c00 {
1049 compatible = "allwinner,sun6i-a31-cpuconfig";
1050 reg = <0x01f01c00 0x300>;
1051 };
1052
1053 ir: ir@01f02000 {
1054 compatible = "allwinner,sun5i-a13-ir";
1055 clocks = <&apb0_gates 1>, <&ir_clk>;
1056 clock-names = "apb", "ir";
1057 resets = <&apb0_rst 1>;
1058 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1059 reg = <0x01f02000 0x40>;
1060 status = "disabled";
1061 };
1062
1063 r_pio: pinctrl@01f02c00 {
1064 compatible = "allwinner,sun6i-a31-r-pinctrl";
1065 reg = <0x01f02c00 0x400>;
1066 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
1067 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
1068 clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>;
1069 clock-names = "apb", "hosc", "losc";
1070 resets = <&apb0_rst 0>;
1071 gpio-controller;
1072 interrupt-controller;
1073 #interrupt-cells = <3>;
1074 #size-cells = <0>;
1075 #gpio-cells = <3>;
1076
1077 ir_pins_a: ir@0 {
1078 allwinner,pins = "PL4";
1079 allwinner,function = "s_ir";
1080 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1081 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1082 };
1083
1084 p2wi_pins: p2wi {
1085 allwinner,pins = "PL0", "PL1";
1086 allwinner,function = "s_p2wi";
1087 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1088 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1089 };
1090 };
1091
1092 p2wi: i2c@01f03400 {
1093 compatible = "allwinner,sun6i-a31-p2wi";
1094 reg = <0x01f03400 0x400>;
1095 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1096 clocks = <&apb0_gates 3>;
1097 clock-frequency = <100000>;
1098 resets = <&apb0_rst 3>;
1099 pinctrl-names = "default";
1100 pinctrl-0 = <&p2wi_pins>;
1101 status = "disabled";
1102 #address-cells = <1>;
1103 #size-cells = <0>;
1104 };
1105 };
1106 };
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