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Merge git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6
[mirror_ubuntu-artful-kernel.git] / arch / arm / boot / dts / sun6i-a31.dtsi
1 /*
2 * Copyright 2013 Maxime Ripard
3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * Or, alternatively,
22 *
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
30 * conditions:
31 *
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
34 *
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
43 */
44
45 #include "skeleton.dtsi"
46
47 #include <dt-bindings/interrupt-controller/arm-gic.h>
48 #include <dt-bindings/thermal/thermal.h>
49
50 #include <dt-bindings/pinctrl/sun4i-a10.h>
51
52 / {
53 interrupt-parent = <&gic>;
54
55 aliases {
56 ethernet0 = &gmac;
57 };
58
59 chosen {
60 #address-cells = <1>;
61 #size-cells = <1>;
62 ranges;
63
64 framebuffer@0 {
65 compatible = "allwinner,simple-framebuffer",
66 "simple-framebuffer";
67 allwinner,pipeline = "de_be0-lcd0-hdmi";
68 clocks = <&pll6 0>;
69 status = "disabled";
70 };
71
72 framebuffer@1 {
73 compatible = "allwinner,simple-framebuffer",
74 "simple-framebuffer";
75 allwinner,pipeline = "de_be0-lcd0";
76 clocks = <&pll6 0>;
77 status = "disabled";
78 };
79 };
80
81 timer {
82 compatible = "arm,armv7-timer";
83 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
84 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
85 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
86 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
87 clock-frequency = <24000000>;
88 arm,cpu-registers-not-fw-configured;
89 };
90
91 cpus {
92 enable-method = "allwinner,sun6i-a31";
93 #address-cells = <1>;
94 #size-cells = <0>;
95
96 cpu0: cpu@0 {
97 compatible = "arm,cortex-a7";
98 device_type = "cpu";
99 reg = <0>;
100 clocks = <&cpu>;
101 clock-latency = <244144>; /* 8 32k periods */
102 operating-points = <
103 /* kHz uV */
104 1008000 1200000
105 864000 1200000
106 720000 1100000
107 480000 1000000
108 >;
109 #cooling-cells = <2>;
110 cooling-min-level = <0>;
111 cooling-max-level = <3>;
112 };
113
114 cpu@1 {
115 compatible = "arm,cortex-a7";
116 device_type = "cpu";
117 reg = <1>;
118 };
119
120 cpu@2 {
121 compatible = "arm,cortex-a7";
122 device_type = "cpu";
123 reg = <2>;
124 };
125
126 cpu@3 {
127 compatible = "arm,cortex-a7";
128 device_type = "cpu";
129 reg = <3>;
130 };
131 };
132
133 thermal-zones {
134 cpu_thermal {
135 /* milliseconds */
136 polling-delay-passive = <250>;
137 polling-delay = <1000>;
138 thermal-sensors = <&rtp>;
139
140 cooling-maps {
141 map0 {
142 trip = <&cpu_alert0>;
143 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
144 };
145 };
146
147 trips {
148 cpu_alert0: cpu_alert0 {
149 /* milliCelsius */
150 temperature = <70000>;
151 hysteresis = <2000>;
152 type = "passive";
153 };
154
155 cpu_crit: cpu_crit {
156 /* milliCelsius */
157 temperature = <100000>;
158 hysteresis = <2000>;
159 type = "critical";
160 };
161 };
162 };
163 };
164
165 memory {
166 reg = <0x40000000 0x80000000>;
167 };
168
169 pmu {
170 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
171 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
172 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
173 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
174 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
175 };
176
177 clocks {
178 #address-cells = <1>;
179 #size-cells = <1>;
180 ranges;
181
182 osc24M: osc24M {
183 #clock-cells = <0>;
184 compatible = "fixed-clock";
185 clock-frequency = <24000000>;
186 };
187
188 osc32k: clk@0 {
189 #clock-cells = <0>;
190 compatible = "fixed-clock";
191 clock-frequency = <32768>;
192 clock-output-names = "osc32k";
193 };
194
195 pll1: clk@01c20000 {
196 #clock-cells = <0>;
197 compatible = "allwinner,sun6i-a31-pll1-clk";
198 reg = <0x01c20000 0x4>;
199 clocks = <&osc24M>;
200 clock-output-names = "pll1";
201 };
202
203 pll6: clk@01c20028 {
204 #clock-cells = <1>;
205 compatible = "allwinner,sun6i-a31-pll6-clk";
206 reg = <0x01c20028 0x4>;
207 clocks = <&osc24M>;
208 clock-output-names = "pll6", "pll6x2";
209 };
210
211 cpu: cpu@01c20050 {
212 #clock-cells = <0>;
213 compatible = "allwinner,sun4i-a10-cpu-clk";
214 reg = <0x01c20050 0x4>;
215
216 /*
217 * PLL1 is listed twice here.
218 * While it looks suspicious, it's actually documented
219 * that way both in the datasheet and in the code from
220 * Allwinner.
221 */
222 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
223 clock-output-names = "cpu";
224 };
225
226 axi: axi@01c20050 {
227 #clock-cells = <0>;
228 compatible = "allwinner,sun4i-a10-axi-clk";
229 reg = <0x01c20050 0x4>;
230 clocks = <&cpu>;
231 clock-output-names = "axi";
232 };
233
234 ahb1: ahb1@01c20054 {
235 #clock-cells = <0>;
236 compatible = "allwinner,sun6i-a31-ahb1-clk";
237 reg = <0x01c20054 0x4>;
238 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
239 clock-output-names = "ahb1";
240
241 /*
242 * Clock AHB1 from PLL6, instead of CPU/AXI which
243 * has rate changes due to cpufreq. Also the DMA
244 * controller requires AHB1 clocked from PLL6.
245 */
246 assigned-clocks = <&ahb1>;
247 assigned-clock-parents = <&pll6 0>;
248 };
249
250 ahb1_gates: clk@01c20060 {
251 #clock-cells = <1>;
252 compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
253 reg = <0x01c20060 0x8>;
254 clocks = <&ahb1>;
255 clock-indices = <1>, <5>,
256 <6>, <8>, <9>,
257 <10>, <11>, <12>,
258 <13>, <14>,
259 <17>, <18>, <19>,
260 <20>, <21>, <22>,
261 <23>, <24>, <26>,
262 <27>, <29>,
263 <30>, <31>, <32>,
264 <36>, <37>, <40>,
265 <43>, <44>, <45>,
266 <46>, <47>, <50>,
267 <52>, <55>, <56>,
268 <57>, <58>;
269 clock-output-names = "ahb1_mipidsi", "ahb1_ss",
270 "ahb1_dma", "ahb1_mmc0", "ahb1_mmc1",
271 "ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1",
272 "ahb1_nand0", "ahb1_sdram",
273 "ahb1_gmac", "ahb1_ts", "ahb1_hstimer",
274 "ahb1_spi0", "ahb1_spi1", "ahb1_spi2",
275 "ahb1_spi3", "ahb1_otg", "ahb1_ehci0",
276 "ahb1_ehci1", "ahb1_ohci0",
277 "ahb1_ohci1", "ahb1_ohci2", "ahb1_ve",
278 "ahb1_lcd0", "ahb1_lcd1", "ahb1_csi",
279 "ahb1_hdmi", "ahb1_de0", "ahb1_de1",
280 "ahb1_fe0", "ahb1_fe1", "ahb1_mp",
281 "ahb1_gpu", "ahb1_deu0", "ahb1_deu1",
282 "ahb1_drc0", "ahb1_drc1";
283 };
284
285 apb1: apb1@01c20054 {
286 #clock-cells = <0>;
287 compatible = "allwinner,sun4i-a10-apb0-clk";
288 reg = <0x01c20054 0x4>;
289 clocks = <&ahb1>;
290 clock-output-names = "apb1";
291 };
292
293 apb1_gates: clk@01c20068 {
294 #clock-cells = <1>;
295 compatible = "allwinner,sun6i-a31-apb1-gates-clk";
296 reg = <0x01c20068 0x4>;
297 clocks = <&apb1>;
298 clock-indices = <0>, <4>,
299 <5>, <12>,
300 <13>;
301 clock-output-names = "apb1_codec", "apb1_digital_mic",
302 "apb1_pio", "apb1_daudio0",
303 "apb1_daudio1";
304 };
305
306 apb2: clk@01c20058 {
307 #clock-cells = <0>;
308 compatible = "allwinner,sun4i-a10-apb1-clk";
309 reg = <0x01c20058 0x4>;
310 clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
311 clock-output-names = "apb2";
312 };
313
314 apb2_gates: clk@01c2006c {
315 #clock-cells = <1>;
316 compatible = "allwinner,sun6i-a31-apb2-gates-clk";
317 reg = <0x01c2006c 0x4>;
318 clocks = <&apb2>;
319 clock-indices = <0>, <1>,
320 <2>, <3>, <16>,
321 <17>, <18>, <19>,
322 <20>, <21>;
323 clock-output-names = "apb2_i2c0", "apb2_i2c1",
324 "apb2_i2c2", "apb2_i2c3",
325 "apb2_uart0", "apb2_uart1",
326 "apb2_uart2", "apb2_uart3",
327 "apb2_uart4", "apb2_uart5";
328 };
329
330 mmc0_clk: clk@01c20088 {
331 #clock-cells = <1>;
332 compatible = "allwinner,sun4i-a10-mmc-clk";
333 reg = <0x01c20088 0x4>;
334 clocks = <&osc24M>, <&pll6 0>;
335 clock-output-names = "mmc0",
336 "mmc0_output",
337 "mmc0_sample";
338 };
339
340 mmc1_clk: clk@01c2008c {
341 #clock-cells = <1>;
342 compatible = "allwinner,sun4i-a10-mmc-clk";
343 reg = <0x01c2008c 0x4>;
344 clocks = <&osc24M>, <&pll6 0>;
345 clock-output-names = "mmc1",
346 "mmc1_output",
347 "mmc1_sample";
348 };
349
350 mmc2_clk: clk@01c20090 {
351 #clock-cells = <1>;
352 compatible = "allwinner,sun4i-a10-mmc-clk";
353 reg = <0x01c20090 0x4>;
354 clocks = <&osc24M>, <&pll6 0>;
355 clock-output-names = "mmc2",
356 "mmc2_output",
357 "mmc2_sample";
358 };
359
360 mmc3_clk: clk@01c20094 {
361 #clock-cells = <1>;
362 compatible = "allwinner,sun4i-a10-mmc-clk";
363 reg = <0x01c20094 0x4>;
364 clocks = <&osc24M>, <&pll6 0>;
365 clock-output-names = "mmc3",
366 "mmc3_output",
367 "mmc3_sample";
368 };
369
370 ss_clk: clk@01c2009c {
371 #clock-cells = <0>;
372 compatible = "allwinner,sun4i-a10-mod0-clk";
373 reg = <0x01c2009c 0x4>;
374 clocks = <&osc24M>, <&pll6 0>;
375 clock-output-names = "ss";
376 };
377
378 spi0_clk: clk@01c200a0 {
379 #clock-cells = <0>;
380 compatible = "allwinner,sun4i-a10-mod0-clk";
381 reg = <0x01c200a0 0x4>;
382 clocks = <&osc24M>, <&pll6 0>;
383 clock-output-names = "spi0";
384 };
385
386 spi1_clk: clk@01c200a4 {
387 #clock-cells = <0>;
388 compatible = "allwinner,sun4i-a10-mod0-clk";
389 reg = <0x01c200a4 0x4>;
390 clocks = <&osc24M>, <&pll6 0>;
391 clock-output-names = "spi1";
392 };
393
394 spi2_clk: clk@01c200a8 {
395 #clock-cells = <0>;
396 compatible = "allwinner,sun4i-a10-mod0-clk";
397 reg = <0x01c200a8 0x4>;
398 clocks = <&osc24M>, <&pll6 0>;
399 clock-output-names = "spi2";
400 };
401
402 spi3_clk: clk@01c200ac {
403 #clock-cells = <0>;
404 compatible = "allwinner,sun4i-a10-mod0-clk";
405 reg = <0x01c200ac 0x4>;
406 clocks = <&osc24M>, <&pll6 0>;
407 clock-output-names = "spi3";
408 };
409
410 usb_clk: clk@01c200cc {
411 #clock-cells = <1>;
412 #reset-cells = <1>;
413 compatible = "allwinner,sun6i-a31-usb-clk";
414 reg = <0x01c200cc 0x4>;
415 clocks = <&osc24M>;
416 clock-indices = <8>, <9>, <10>,
417 <16>, <17>,
418 <18>;
419 clock-output-names = "usb_phy0", "usb_phy1", "usb_phy2",
420 "usb_ohci0", "usb_ohci1",
421 "usb_ohci2";
422 };
423
424 /*
425 * The following two are dummy clocks, placeholders
426 * used in the gmac_tx clock. The gmac driver will
427 * choose one parent depending on the PHY interface
428 * mode, using clk_set_rate auto-reparenting.
429 *
430 * The actual TX clock rate is not controlled by the
431 * gmac_tx clock.
432 */
433 mii_phy_tx_clk: clk@1 {
434 #clock-cells = <0>;
435 compatible = "fixed-clock";
436 clock-frequency = <25000000>;
437 clock-output-names = "mii_phy_tx";
438 };
439
440 gmac_int_tx_clk: clk@2 {
441 #clock-cells = <0>;
442 compatible = "fixed-clock";
443 clock-frequency = <125000000>;
444 clock-output-names = "gmac_int_tx";
445 };
446
447 gmac_tx_clk: clk@01c200d0 {
448 #clock-cells = <0>;
449 compatible = "allwinner,sun7i-a20-gmac-clk";
450 reg = <0x01c200d0 0x4>;
451 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
452 clock-output-names = "gmac_tx";
453 };
454 };
455
456 soc@01c00000 {
457 compatible = "simple-bus";
458 #address-cells = <1>;
459 #size-cells = <1>;
460 ranges;
461
462 dma: dma-controller@01c02000 {
463 compatible = "allwinner,sun6i-a31-dma";
464 reg = <0x01c02000 0x1000>;
465 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
466 clocks = <&ahb1_gates 6>;
467 resets = <&ahb1_rst 6>;
468 #dma-cells = <1>;
469 };
470
471 mmc0: mmc@01c0f000 {
472 compatible = "allwinner,sun5i-a13-mmc";
473 reg = <0x01c0f000 0x1000>;
474 clocks = <&ahb1_gates 8>,
475 <&mmc0_clk 0>,
476 <&mmc0_clk 1>,
477 <&mmc0_clk 2>;
478 clock-names = "ahb",
479 "mmc",
480 "output",
481 "sample";
482 resets = <&ahb1_rst 8>;
483 reset-names = "ahb";
484 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
485 status = "disabled";
486 #address-cells = <1>;
487 #size-cells = <0>;
488 };
489
490 mmc1: mmc@01c10000 {
491 compatible = "allwinner,sun5i-a13-mmc";
492 reg = <0x01c10000 0x1000>;
493 clocks = <&ahb1_gates 9>,
494 <&mmc1_clk 0>,
495 <&mmc1_clk 1>,
496 <&mmc1_clk 2>;
497 clock-names = "ahb",
498 "mmc",
499 "output",
500 "sample";
501 resets = <&ahb1_rst 9>;
502 reset-names = "ahb";
503 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
504 status = "disabled";
505 #address-cells = <1>;
506 #size-cells = <0>;
507 };
508
509 mmc2: mmc@01c11000 {
510 compatible = "allwinner,sun5i-a13-mmc";
511 reg = <0x01c11000 0x1000>;
512 clocks = <&ahb1_gates 10>,
513 <&mmc2_clk 0>,
514 <&mmc2_clk 1>,
515 <&mmc2_clk 2>;
516 clock-names = "ahb",
517 "mmc",
518 "output",
519 "sample";
520 resets = <&ahb1_rst 10>;
521 reset-names = "ahb";
522 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
523 status = "disabled";
524 #address-cells = <1>;
525 #size-cells = <0>;
526 };
527
528 mmc3: mmc@01c12000 {
529 compatible = "allwinner,sun5i-a13-mmc";
530 reg = <0x01c12000 0x1000>;
531 clocks = <&ahb1_gates 11>,
532 <&mmc3_clk 0>,
533 <&mmc3_clk 1>,
534 <&mmc3_clk 2>;
535 clock-names = "ahb",
536 "mmc",
537 "output",
538 "sample";
539 resets = <&ahb1_rst 11>;
540 reset-names = "ahb";
541 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
542 status = "disabled";
543 #address-cells = <1>;
544 #size-cells = <0>;
545 };
546
547 usbphy: phy@01c19400 {
548 compatible = "allwinner,sun6i-a31-usb-phy";
549 reg = <0x01c19400 0x10>,
550 <0x01c1a800 0x4>,
551 <0x01c1b800 0x4>;
552 reg-names = "phy_ctrl",
553 "pmu1",
554 "pmu2";
555 clocks = <&usb_clk 8>,
556 <&usb_clk 9>,
557 <&usb_clk 10>;
558 clock-names = "usb0_phy",
559 "usb1_phy",
560 "usb2_phy";
561 resets = <&usb_clk 0>,
562 <&usb_clk 1>,
563 <&usb_clk 2>;
564 reset-names = "usb0_reset",
565 "usb1_reset",
566 "usb2_reset";
567 status = "disabled";
568 #phy-cells = <1>;
569 };
570
571 ehci0: usb@01c1a000 {
572 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
573 reg = <0x01c1a000 0x100>;
574 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
575 clocks = <&ahb1_gates 26>;
576 resets = <&ahb1_rst 26>;
577 phys = <&usbphy 1>;
578 phy-names = "usb";
579 status = "disabled";
580 };
581
582 ohci0: usb@01c1a400 {
583 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
584 reg = <0x01c1a400 0x100>;
585 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
586 clocks = <&ahb1_gates 29>, <&usb_clk 16>;
587 resets = <&ahb1_rst 29>;
588 phys = <&usbphy 1>;
589 phy-names = "usb";
590 status = "disabled";
591 };
592
593 ehci1: usb@01c1b000 {
594 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
595 reg = <0x01c1b000 0x100>;
596 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
597 clocks = <&ahb1_gates 27>;
598 resets = <&ahb1_rst 27>;
599 phys = <&usbphy 2>;
600 phy-names = "usb";
601 status = "disabled";
602 };
603
604 ohci1: usb@01c1b400 {
605 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
606 reg = <0x01c1b400 0x100>;
607 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
608 clocks = <&ahb1_gates 30>, <&usb_clk 17>;
609 resets = <&ahb1_rst 30>;
610 phys = <&usbphy 2>;
611 phy-names = "usb";
612 status = "disabled";
613 };
614
615 ohci2: usb@01c1c400 {
616 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
617 reg = <0x01c1c400 0x100>;
618 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
619 clocks = <&ahb1_gates 31>, <&usb_clk 18>;
620 resets = <&ahb1_rst 31>;
621 status = "disabled";
622 };
623
624 pio: pinctrl@01c20800 {
625 compatible = "allwinner,sun6i-a31-pinctrl";
626 reg = <0x01c20800 0x400>;
627 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
628 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
629 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
630 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
631 clocks = <&apb1_gates 5>;
632 gpio-controller;
633 interrupt-controller;
634 #interrupt-cells = <2>;
635 #size-cells = <0>;
636 #gpio-cells = <3>;
637
638 uart0_pins_a: uart0@0 {
639 allwinner,pins = "PH20", "PH21";
640 allwinner,function = "uart0";
641 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
642 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
643 };
644
645 i2c0_pins_a: i2c0@0 {
646 allwinner,pins = "PH14", "PH15";
647 allwinner,function = "i2c0";
648 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
649 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
650 };
651
652 i2c1_pins_a: i2c1@0 {
653 allwinner,pins = "PH16", "PH17";
654 allwinner,function = "i2c1";
655 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
656 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
657 };
658
659 i2c2_pins_a: i2c2@0 {
660 allwinner,pins = "PH18", "PH19";
661 allwinner,function = "i2c2";
662 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
663 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
664 };
665
666 mmc0_pins_a: mmc0@0 {
667 allwinner,pins = "PF0", "PF1", "PF2",
668 "PF3", "PF4", "PF5";
669 allwinner,function = "mmc0";
670 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
671 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
672 };
673
674 mmc1_pins_a: mmc1@0 {
675 allwinner,pins = "PG0", "PG1", "PG2", "PG3",
676 "PG4", "PG5";
677 allwinner,function = "mmc1";
678 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
679 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
680 };
681
682 gmac_pins_mii_a: gmac_mii@0 {
683 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
684 "PA8", "PA9", "PA11",
685 "PA12", "PA13", "PA14", "PA19",
686 "PA20", "PA21", "PA22", "PA23",
687 "PA24", "PA26", "PA27";
688 allwinner,function = "gmac";
689 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
690 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
691 };
692
693 gmac_pins_gmii_a: gmac_gmii@0 {
694 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
695 "PA4", "PA5", "PA6", "PA7",
696 "PA8", "PA9", "PA10", "PA11",
697 "PA12", "PA13", "PA14", "PA15",
698 "PA16", "PA17", "PA18", "PA19",
699 "PA20", "PA21", "PA22", "PA23",
700 "PA24", "PA25", "PA26", "PA27";
701 allwinner,function = "gmac";
702 /*
703 * data lines in GMII mode run at 125MHz and
704 * might need a higher signal drive strength
705 */
706 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
707 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
708 };
709
710 gmac_pins_rgmii_a: gmac_rgmii@0 {
711 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
712 "PA9", "PA10", "PA11",
713 "PA12", "PA13", "PA14", "PA19",
714 "PA20", "PA25", "PA26", "PA27";
715 allwinner,function = "gmac";
716 /*
717 * data lines in RGMII mode use DDR mode
718 * and need a higher signal drive strength
719 */
720 allwinner,drive = <SUN4I_PINCTRL_40_MA>;
721 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
722 };
723 };
724
725 ahb1_rst: reset@01c202c0 {
726 #reset-cells = <1>;
727 compatible = "allwinner,sun6i-a31-ahb1-reset";
728 reg = <0x01c202c0 0xc>;
729 };
730
731 apb1_rst: reset@01c202d0 {
732 #reset-cells = <1>;
733 compatible = "allwinner,sun6i-a31-clock-reset";
734 reg = <0x01c202d0 0x4>;
735 };
736
737 apb2_rst: reset@01c202d8 {
738 #reset-cells = <1>;
739 compatible = "allwinner,sun6i-a31-clock-reset";
740 reg = <0x01c202d8 0x4>;
741 };
742
743 timer@01c20c00 {
744 compatible = "allwinner,sun4i-a10-timer";
745 reg = <0x01c20c00 0xa0>;
746 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
747 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
748 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
749 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
750 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
751 clocks = <&osc24M>;
752 };
753
754 wdt1: watchdog@01c20ca0 {
755 compatible = "allwinner,sun6i-a31-wdt";
756 reg = <0x01c20ca0 0x20>;
757 };
758
759 rtp: rtp@01c25000 {
760 compatible = "allwinner,sun6i-a31-ts";
761 reg = <0x01c25000 0x100>;
762 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
763 #thermal-sensor-cells = <0>;
764 };
765
766 uart0: serial@01c28000 {
767 compatible = "snps,dw-apb-uart";
768 reg = <0x01c28000 0x400>;
769 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
770 reg-shift = <2>;
771 reg-io-width = <4>;
772 clocks = <&apb2_gates 16>;
773 resets = <&apb2_rst 16>;
774 dmas = <&dma 6>, <&dma 6>;
775 dma-names = "rx", "tx";
776 status = "disabled";
777 };
778
779 uart1: serial@01c28400 {
780 compatible = "snps,dw-apb-uart";
781 reg = <0x01c28400 0x400>;
782 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
783 reg-shift = <2>;
784 reg-io-width = <4>;
785 clocks = <&apb2_gates 17>;
786 resets = <&apb2_rst 17>;
787 dmas = <&dma 7>, <&dma 7>;
788 dma-names = "rx", "tx";
789 status = "disabled";
790 };
791
792 uart2: serial@01c28800 {
793 compatible = "snps,dw-apb-uart";
794 reg = <0x01c28800 0x400>;
795 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
796 reg-shift = <2>;
797 reg-io-width = <4>;
798 clocks = <&apb2_gates 18>;
799 resets = <&apb2_rst 18>;
800 dmas = <&dma 8>, <&dma 8>;
801 dma-names = "rx", "tx";
802 status = "disabled";
803 };
804
805 uart3: serial@01c28c00 {
806 compatible = "snps,dw-apb-uart";
807 reg = <0x01c28c00 0x400>;
808 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
809 reg-shift = <2>;
810 reg-io-width = <4>;
811 clocks = <&apb2_gates 19>;
812 resets = <&apb2_rst 19>;
813 dmas = <&dma 9>, <&dma 9>;
814 dma-names = "rx", "tx";
815 status = "disabled";
816 };
817
818 uart4: serial@01c29000 {
819 compatible = "snps,dw-apb-uart";
820 reg = <0x01c29000 0x400>;
821 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
822 reg-shift = <2>;
823 reg-io-width = <4>;
824 clocks = <&apb2_gates 20>;
825 resets = <&apb2_rst 20>;
826 dmas = <&dma 10>, <&dma 10>;
827 dma-names = "rx", "tx";
828 status = "disabled";
829 };
830
831 uart5: serial@01c29400 {
832 compatible = "snps,dw-apb-uart";
833 reg = <0x01c29400 0x400>;
834 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
835 reg-shift = <2>;
836 reg-io-width = <4>;
837 clocks = <&apb2_gates 21>;
838 resets = <&apb2_rst 21>;
839 dmas = <&dma 22>, <&dma 22>;
840 dma-names = "rx", "tx";
841 status = "disabled";
842 };
843
844 i2c0: i2c@01c2ac00 {
845 compatible = "allwinner,sun6i-a31-i2c";
846 reg = <0x01c2ac00 0x400>;
847 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
848 clocks = <&apb2_gates 0>;
849 resets = <&apb2_rst 0>;
850 status = "disabled";
851 #address-cells = <1>;
852 #size-cells = <0>;
853 };
854
855 i2c1: i2c@01c2b000 {
856 compatible = "allwinner,sun6i-a31-i2c";
857 reg = <0x01c2b000 0x400>;
858 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
859 clocks = <&apb2_gates 1>;
860 resets = <&apb2_rst 1>;
861 status = "disabled";
862 #address-cells = <1>;
863 #size-cells = <0>;
864 };
865
866 i2c2: i2c@01c2b400 {
867 compatible = "allwinner,sun6i-a31-i2c";
868 reg = <0x01c2b400 0x400>;
869 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
870 clocks = <&apb2_gates 2>;
871 resets = <&apb2_rst 2>;
872 status = "disabled";
873 #address-cells = <1>;
874 #size-cells = <0>;
875 };
876
877 i2c3: i2c@01c2b800 {
878 compatible = "allwinner,sun6i-a31-i2c";
879 reg = <0x01c2b800 0x400>;
880 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
881 clocks = <&apb2_gates 3>;
882 resets = <&apb2_rst 3>;
883 status = "disabled";
884 #address-cells = <1>;
885 #size-cells = <0>;
886 };
887
888 gmac: ethernet@01c30000 {
889 compatible = "allwinner,sun7i-a20-gmac";
890 reg = <0x01c30000 0x1054>;
891 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
892 interrupt-names = "macirq";
893 clocks = <&ahb1_gates 17>, <&gmac_tx_clk>;
894 clock-names = "stmmaceth", "allwinner_gmac_tx";
895 resets = <&ahb1_rst 17>;
896 reset-names = "stmmaceth";
897 snps,pbl = <2>;
898 snps,fixed-burst;
899 snps,force_sf_dma_mode;
900 status = "disabled";
901 #address-cells = <1>;
902 #size-cells = <0>;
903 };
904
905 crypto: crypto-engine@01c15000 {
906 compatible = "allwinner,sun4i-a10-crypto";
907 reg = <0x01c15000 0x1000>;
908 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
909 clocks = <&ahb1_gates 5>, <&ss_clk>;
910 clock-names = "ahb", "mod";
911 resets = <&ahb1_rst 5>;
912 reset-names = "ahb";
913 };
914
915 timer@01c60000 {
916 compatible = "allwinner,sun6i-a31-hstimer",
917 "allwinner,sun7i-a20-hstimer";
918 reg = <0x01c60000 0x1000>;
919 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
920 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
921 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
922 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
923 clocks = <&ahb1_gates 19>;
924 resets = <&ahb1_rst 19>;
925 };
926
927 spi0: spi@01c68000 {
928 compatible = "allwinner,sun6i-a31-spi";
929 reg = <0x01c68000 0x1000>;
930 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
931 clocks = <&ahb1_gates 20>, <&spi0_clk>;
932 clock-names = "ahb", "mod";
933 dmas = <&dma 23>, <&dma 23>;
934 dma-names = "rx", "tx";
935 resets = <&ahb1_rst 20>;
936 status = "disabled";
937 };
938
939 spi1: spi@01c69000 {
940 compatible = "allwinner,sun6i-a31-spi";
941 reg = <0x01c69000 0x1000>;
942 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
943 clocks = <&ahb1_gates 21>, <&spi1_clk>;
944 clock-names = "ahb", "mod";
945 dmas = <&dma 24>, <&dma 24>;
946 dma-names = "rx", "tx";
947 resets = <&ahb1_rst 21>;
948 status = "disabled";
949 };
950
951 spi2: spi@01c6a000 {
952 compatible = "allwinner,sun6i-a31-spi";
953 reg = <0x01c6a000 0x1000>;
954 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
955 clocks = <&ahb1_gates 22>, <&spi2_clk>;
956 clock-names = "ahb", "mod";
957 dmas = <&dma 25>, <&dma 25>;
958 dma-names = "rx", "tx";
959 resets = <&ahb1_rst 22>;
960 status = "disabled";
961 };
962
963 spi3: spi@01c6b000 {
964 compatible = "allwinner,sun6i-a31-spi";
965 reg = <0x01c6b000 0x1000>;
966 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
967 clocks = <&ahb1_gates 23>, <&spi3_clk>;
968 clock-names = "ahb", "mod";
969 dmas = <&dma 26>, <&dma 26>;
970 dma-names = "rx", "tx";
971 resets = <&ahb1_rst 23>;
972 status = "disabled";
973 };
974
975 gic: interrupt-controller@01c81000 {
976 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
977 reg = <0x01c81000 0x1000>,
978 <0x01c82000 0x1000>,
979 <0x01c84000 0x2000>,
980 <0x01c86000 0x2000>;
981 interrupt-controller;
982 #interrupt-cells = <3>;
983 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
984 };
985
986 rtc: rtc@01f00000 {
987 compatible = "allwinner,sun6i-a31-rtc";
988 reg = <0x01f00000 0x54>;
989 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
990 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
991 };
992
993 nmi_intc: interrupt-controller@01f00c0c {
994 compatible = "allwinner,sun6i-a31-sc-nmi";
995 interrupt-controller;
996 #interrupt-cells = <2>;
997 reg = <0x01f00c0c 0x38>;
998 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
999 };
1000
1001 prcm@01f01400 {
1002 compatible = "allwinner,sun6i-a31-prcm";
1003 reg = <0x01f01400 0x200>;
1004
1005 ar100: ar100_clk {
1006 compatible = "allwinner,sun6i-a31-ar100-clk";
1007 #clock-cells = <0>;
1008 clocks = <&osc32k>, <&osc24M>, <&pll6 0>,
1009 <&pll6 0>;
1010 clock-output-names = "ar100";
1011 };
1012
1013 ahb0: ahb0_clk {
1014 compatible = "fixed-factor-clock";
1015 #clock-cells = <0>;
1016 clock-div = <1>;
1017 clock-mult = <1>;
1018 clocks = <&ar100>;
1019 clock-output-names = "ahb0";
1020 };
1021
1022 apb0: apb0_clk {
1023 compatible = "allwinner,sun6i-a31-apb0-clk";
1024 #clock-cells = <0>;
1025 clocks = <&ahb0>;
1026 clock-output-names = "apb0";
1027 };
1028
1029 apb0_gates: apb0_gates_clk {
1030 compatible = "allwinner,sun6i-a31-apb0-gates-clk";
1031 #clock-cells = <1>;
1032 clocks = <&apb0>;
1033 clock-output-names = "apb0_pio", "apb0_ir",
1034 "apb0_timer", "apb0_p2wi",
1035 "apb0_uart", "apb0_1wire",
1036 "apb0_i2c";
1037 };
1038
1039 ir_clk: ir_clk {
1040 #clock-cells = <0>;
1041 compatible = "allwinner,sun4i-a10-mod0-clk";
1042 clocks = <&osc32k>, <&osc24M>;
1043 clock-output-names = "ir";
1044 };
1045
1046 apb0_rst: apb0_rst {
1047 compatible = "allwinner,sun6i-a31-clock-reset";
1048 #reset-cells = <1>;
1049 };
1050 };
1051
1052 cpucfg@01f01c00 {
1053 compatible = "allwinner,sun6i-a31-cpuconfig";
1054 reg = <0x01f01c00 0x300>;
1055 };
1056
1057 ir: ir@01f02000 {
1058 compatible = "allwinner,sun5i-a13-ir";
1059 clocks = <&apb0_gates 1>, <&ir_clk>;
1060 clock-names = "apb", "ir";
1061 resets = <&apb0_rst 1>;
1062 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1063 reg = <0x01f02000 0x40>;
1064 status = "disabled";
1065 };
1066
1067 r_pio: pinctrl@01f02c00 {
1068 compatible = "allwinner,sun6i-a31-r-pinctrl";
1069 reg = <0x01f02c00 0x400>;
1070 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
1071 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
1072 clocks = <&apb0_gates 0>;
1073 resets = <&apb0_rst 0>;
1074 gpio-controller;
1075 interrupt-controller;
1076 #interrupt-cells = <2>;
1077 #size-cells = <0>;
1078 #gpio-cells = <3>;
1079
1080 ir_pins_a: ir@0 {
1081 allwinner,pins = "PL4";
1082 allwinner,function = "s_ir";
1083 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1084 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1085 };
1086
1087 p2wi_pins: p2wi {
1088 allwinner,pins = "PL0", "PL1";
1089 allwinner,function = "s_p2wi";
1090 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1091 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1092 };
1093 };
1094
1095 p2wi: i2c@01f03400 {
1096 compatible = "allwinner,sun6i-a31-p2wi";
1097 reg = <0x01f03400 0x400>;
1098 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1099 clocks = <&apb0_gates 3>;
1100 clock-frequency = <100000>;
1101 resets = <&apb0_rst 3>;
1102 pinctrl-names = "default";
1103 pinctrl-0 = <&p2wi_pins>;
1104 status = "disabled";
1105 #address-cells = <1>;
1106 #size-cells = <0>;
1107 };
1108 };
1109 };
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